Design
for Test
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Validation and Test of
Manufactured Circuits
Goals of Design-for-Test (DFT)
Make testing of manufactured part swift and
comprehensive
DFT Mantra
Provide controllability and observability
Components of DFT strategy
• Provide circuitry to enable test
• Provide test patterns that guarantee reasonable
coverage
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Test Classification

Diagnostic test
» used in chip/board debugging
» defect localization

“go/no go” or production test
» Used in chip production

Parametric test
» x e [v,i] versus x e [0,1]
» check parameters such as NM, Vt, tp, T
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Design for Testability
N inputs
N inputs
Combinational
K outputs
Combinational
K outputs
Logic
Logic
Module
Module
M state regs
(a) Combinational function
(b) Sequential engine
2N patterns
2N+M patterns
Exhaustive test is impossible or unpractical
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Problem:
Controllability/Observability

Combinational Circuits:
controllable and observable - relatively easy to
determine test patterns

Sequential Circuits: State!
Turn into combinational circuits or use self-test

Memory: requires complex patterns
Use self-test
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Test Approaches
Ad-hoc testing
 Scan-based Test
 Self-Test
Problem is getting harder

» increasing complexity and heterogeneous
combination of modules in system-on-a-chip.
» Advanced packaging and assembly techniques
extend problem to the board level
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Generating and Validating
Test-Vectors

Automatic test-pattern generation (ATPG)
» for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output
» majority of available tools: combinational networks only
» sequential ATPG available from academic research

Fault simulation
» determines test coverage of proposed test-vector set
» simulates correct network in parallel with faulty networks

Both require adequate models of faults in
CMOS integrated circuits
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Fault Models
Most Popular - “Stuck - at” model
sa0
(output)
0
1
sa1
(input)
Covers almost all (other)
occurring faults, such as
opens and shorts.
Z
x1


x2
Digital Integrated Circuits

Design Methodologies
x3
,  : x1 sa1
 : x1 sa0 or
x2 sa0
 : Z sa1
© Prentice Hall 1995
Problem with stuck-at model:
CMOS open fault
x1
x2
Z
x1
x2
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short models
This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Problem with stuck-at model:
CMOS short fault
‘0’
‘0’
C
D
A
B
‘0’
A
C
‘1’
B
D
Digital Integrated Circuits
Causes short circuit between
Vdd and GND for A=C=0, B=1
Possible approach:
Supply Current Measurement (IDDQ)
but: not applicable for gigascale
integration
Design Methodologies
© Prentice Hall 1995
Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
Fault enabling
1
1
1
1
Fault propagation
0
sa0
1
Out
1
0
Techniques Used: D-algorithm, Podem
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Ad-hoc Test
data
address
data
test
address
Memory
Memory
select
Processor
Processor
I/O bus
I/O bus
Inserting multiplexer improves testability
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Scan-based Test
ScanIn
Digital Integrated Circuits
Combinational
Logic
A
Register
Register
In
ScanOut
Design Methodologies
Combinational
Out
Logic
B
© Prentice Hall 1995
Polarity-Hold SRL
(Shift-Register Latch)
System Data
System Clock
Scan Data
Shift A Clock
D
C
SI
A
Q
L1
Q
SO
Shift B Clock
B
L2
SO
Introduced at IBM and set as company policy
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Scan-Path Register
OUT
SCAN
PHI2
PHI1
SCANIN
SCANOUT
IN
LOAD
Digital Integrated Circuits
KEEP
Design Methodologies
© Prentice Hall 1995
Scan-based Test —Operation
In 0
Test
In1
Test
ScanIn
Test
In2
Test
Test
In 3
Test
Test
Test
ScanOut
Latch
Latch
Latch
Latch
Out0
Out1
Out2
Out3
Test
1
2
N cycles
scan-in
Digital Integrated Circuits
1 cycle
evaluation
Design Methodologies
N cycles
scan-out
© Prentice Hall 1995
Scan-Path Testing
A
B
REG[1]
REG[0]
REG[2]
REG[3]
SCANIN
+
REG[4]
COMPIN
COMP
REG[5]
SCANOUT
OUT
Partial-Scan can be more effective for pipelined datapaths
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Boundary Scan (JTAG)
Printed-circuit board
Logic
Scan-out
si
so
scan path
normal interconnect
Scan-in
Packaged IC
Bonding Pad
Board testing becomes as problematic as chip testing
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Self-test
(Sub)-Circuit
Stimulus Generator
Under
Response Analyzer
Test
Test Controller
Rapidly becoming more important with increasing
chip-complexity and larger modules
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Linear-Feedback Shift Register (LFSR)
R
R
R
S0
S1
S2
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
Pseudo-Random Pattern Generator
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
Signature Analysis
In
Counter
R
Counts transitions on single-bit stream
 Compression in time
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995
BILBO
D0
B0
D1
D2
B1
ScanOut
mux
ScanIn
R
R
S0
Digital Integrated Circuits
R
S1
B0 B1
Operation mode
1
1
Normal
0
0
1
0
0
1
Scan
Pattern generation or
Signature analysis
Reset
Design Methodologies
S2
© Prentice Hall 1995
BILBO Application
Digital Integrated Circuits
Combinational
Logic
BILBO-B
In
ScanOut
BILBO-A
ScanIn
Design Methodologies
Combinational
Out
Logic
© Prentice Hall 1995
Memory Self-Test
data -in
Memory
data-out
Signature
FSM
Under Test
Analysis
address &
R/W control
Patterns: Writing/Reading 0s, 1s,
Walking 0s, 1s
Galloping 0s, 1s
Digital Integrated Circuits
Design Methodologies
© Prentice Hall 1995