HINP32C
Southern Illinois University
Edwardsville VLSI Design
Research Laboratory
Washington University in Saint
Louis Nuclear Reactions Group

Dr. George L. Engel ,Muthu Sadavisam,Mythreyi Nethi
Department of Electrical and Computer Engineering
VLSI Design Research Laboratory
Southern Illinois University Edwardsville
Jon Elson, Dr. Lee Sobotka, Dr. Robert Charity
Department of Chemistry
Nuclear Reactions Group
Washington University in Saint Louis

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HINP32C is a 32 channel integrated circuit (IC) for use in a series of experiments in low and intermediate energy nuclear physics.
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The IC will be fabricated in the AMIS
0.5
m m, N-well CMOS, double-poly, triple-metal, high-resistance process through MOSIS.
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The die is 6 mm x 6 mm.

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Need for high density signal processing in low and intermediate energy nuclear physics community is widespread
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No commercial chip was found to do exactly what we wanted. Necessary for the “experimenter” to be in the
“designer’s seat”
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Timing, self-triggering, and on chip sparsification non-existent or inadequate
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Gain ranges beyond 50 MeV not available

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Spectroscopy of low lying particle unstable states by resonance decay correlation techniques
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Inverse (d,p) scattering experiments designed to study shell structure and pairing in n-rich nuclei
 Inverse (p,d) reactions examining the n single particle structure of secondary unstable beams
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Particle-particle correlation experiments at intermediate energy designed to refine temperature determinations and to image source characteristics
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Si arrays for detecting
 particles and CZT and
Ge arrays for detecting
 ray’s.

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100 MeV full range with 25 keV (FWHM) resolution
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Time resolution of 500 ps (FWHM) for a monoenergetic 5 MeV a
-particle
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Capable of processing either polarity
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Data sparsification: User selection of either hit channels or all to be read out
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High level of debug capability
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Compatibility with modern pipeline
ADC’s

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Two gain modes: 100 MeV or 500 MeV
 Capable of processing either polarity
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Variable peaking time: 1 m s – 2 m s
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Channel by channel disable of on-chip
CFDs
 Analog multiplicity output (and logical OR)
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Data Sparsification: User selection of either hit channels or all to be read out
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Two time measurement ranges: 250 ns or 1 m s
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Automatic reset of time-to-voltage and peak sampling circuits unless vetoed by user with variable decision time (300 ns –
30 m s)

reset
Reset Logic q (Coulombs)
CSA time (Volts)
Pseudo
CFD
TVC
Slow shaper
Peak sampler energy (Volts)

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Each channel consists of a charge sensitive amplifier
(CSA) with two gain modes: 100 MeV and 500 Mev fullscale.
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The CSA output (30 ns risetime, 50 m se falltime) is split to feed energy and timing branches each of which produce sparsified pulse trains with synchronized addresses for off-chip digitization with a pipelined ADC
Noise slope: 3 e / pF
Noise at 0 pF : 2475 e Noise at 75 pF: 2600 e
Resolution: 25 - 30 keV

Response of Shaper
2.7
2.65
2.6
2.55
2.5
2.45
20
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The energy leg consists of a third-order, tranconductance-C shaping filter with a fast return to baseline, < 20 m s, and variable peaking time: 1 m s - 2 m s.
25
Time (us)
30
Noise plot for CSA & Shaper
35
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This slow-shaper is followed by a continuous-time peak sampling circuit.
Energy resolution is 25-
30 keV in the 100 MeV (FS) mode.
3000
2900
2800
2700
2600
2500
2400
0 20 40 60 80 100 120 140 160
Capacitance (pF)
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This slow-shaper is followed by a continuous-time peak sampling circuit

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The timing leg consists of a pseudo constant fraction discriminator (CFD) composed of a leading edge and a zerocross discriminator.
The zero-crossing discriminator has its offsets dynamically nulled.
CFD Walk Plot
51.0
50.5
50.0
49.5
49.0
48.5
48.0
47.5
47.0
1.00E+04 1.00E+05 1.00E+06
Input Electrons
1.00E+07
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A 6-bit DAC is used to correct offsets associated with the leading-edge circuit as well as to set CFD threshold levels. When the CFD fires it starts a time-to-voltage conversion (TVC).
1.00E+08
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A fast logical ‘OR’ signal and an analog output proportional to the number of channels that were hit are available for use.
The logical ‘OR’ and the analog multiplicity output are also automatically reset unless vetoed by the user.
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The energy leg consists of a third-order, tranconductance-C shaping filter with a fast return to baseline (20 m s) and variable peaking time (1 m s - 2 m s).

The TVC circuit has two measurement ranges:
250ns and 1 m s. The conversion is stopped by a common stop signal applied to all channels.
The TVC circuit as well as the peak sampling circuit is automatically reset after a variable delay time (300 ns – 30 m s) reference to when the
CFD fires, unless vetoed by the user.
The intrinsic time resolution on-chip is 150 ps in the 250 ns range mode.

A common channel provides biasing for the
32 processing channels and contains readout electronics.
A 48-bit configuration register allows the user to selectively disable CFD outputs on a channel by channel basis, select test modes, select processing for either positive or negative CSA pulses, select CSA gain mode,
TVC measurement range, and assign an 8-bit
ID to the chip.
The chip only responds when an externally applied chip address matches the ID stored in the chip's configuration register.

Supply Current Distribution for Single Channel
BIAS
0.829%
Total Current is 6.7mA
CSA
26.965%
CFD
41.047%
SHAPER
15.655%
TVC
0.225%
RESET_LOGIC
0.150%

Area Chart for single channel tvc
3% reset logic
2% sample peak
13% csa
17% cfd
25% shaper
40%

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HINP16C is presently being tested!
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The testing process will take several months
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If HINP16C succeeds then we will move on to HINP32C
 ADDITIONAL PROJECTS
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Peak sampler with digital assist
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Lower-noise version of shaper?
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Multiple sampling PSD chip