Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
Coping with
Interconnect
December 15, 2002
© Digital Integrated Circuits2nd
Interconnect
Impact of Interconnect Parasitics
• Reduce Robustness
• Affect Performance
• Increase delay
• Increase power dissipation
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
© Digital Integrated Circuits2nd
Interconnect
INTERCONNECT
© Digital Integrated Circuits2nd
Interconnect
Capacitive Cross Talk
X
CXY
VX
Y
CY
© Digital Integrated Circuits2nd
Interconnect
Capacitive Cross Talk
Dynamic Node
V DD
CLK
CXY
Y
In 1
In 2
In 3
CY
PDN
X
2.5 V
0V
CLK
3 x 1 mm overlap: 0.19 V disturbance
© Digital Integrated Circuits2nd
Interconnect
Capacitive Cross Talk
Driven Node
0.5
0.45
0.4
X
VX
CXY
RY
0.3
Y
CY
tr↑
0.35
tXY = RY(CXY+CY)
0.25
0.2
0.15
V (Volt)
0.1
0.05
0
0
0.2
0.4
0.6
0.8
1
t (nsec)
Keep time-constant smaller than rise time
© Digital Integrated Circuits2nd
Interconnect
Dealing with Capacitive Cross Talk
Avoid floating nodes
 Protect sensitive nodes
 Make rise and fall times as large as possible
 Differential signaling
 Do not run wires together for a long distance
 Use shielding wires
 Use shielding layers

© Digital Integrated Circuits2nd
Interconnect
Shielding
Shielding
wire
GND
V DD
Shielding
layer
GND
Substrate (GND )
© Digital Integrated Circuits2nd
Interconnect
Cross Talk and Performance
- When neighboring lines
switch in opposite direction of
victim line, delay increases
Cc
DELAY DEPENDENT UPON
ACTIVITY IN NEIGHBORING
WIRES
Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0  Vdd, Vdd  0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
© Digital Integrated Circuits2nd
Interconnect
Impact of Cross Talk on Delay
r is ratio between capacitance to GND and to neighbor
© Digital Integrated Circuits2nd
Interconnect
Structured Predictable Interconnect
V
S G S V S
S
G
S
V
S
V
Example: Dense Wire Fabric ([Sunil Kathri])
Trade-off:
• Cross-coupling capacitance 40x lower, 2% delay variation
• Increase in area and overall capacitance
Also: FPGAs, VPGAs
© Digital Integrated Circuits2nd
Interconnect
Interconnect Projections
Low-k dielectrics



Both delay and power are reduced by dropping interconnect
capacitance
Types of low-k materials include: inorganic (SiO2), organic
(Polyimides) and aerogels (ultra low-k)
The numbers below are on the
conservative side of the NRTS roadmap
Generation
Dielectric
Constant
0.25
mm
3.3
© Digital Integrated Circuits2nd
0.18
mm
2.7
0.13
mm
2.3
0.1
mm
2.0
0.07
mm
1.8
e
0.05
mm
1.5
Interconnect
Encoding Data Avoids Worst-Case
Conditions
In
Encoder
Bus
Decoder
Out
© Digital Integrated Circuits2nd
Interconnect
Driving Large Capacitances
V DD
V in
V out
CL
• Transistor Sizing
• Cascaded Buffers
© Digital Integrated Circuits2nd
Interconnect
Using Cascaded Buffers
In
Out
1
2
0.25 mm process
Cin = 2.5 fF
tp0 = 30 ps
N
CL = 20 pF
F = CL/Cin = 8000
fopt = 3.6 N = 7
tp = 0.76 ns
(See Chapter 5)
© Digital Integrated Circuits2nd
Interconnect
Output Driver Design
Trade off Performance for Area and Energy
Given tpmax find N and f
 Area
f 1
F 1
A
 1  f  f  ...  f A 
A 
A
f 1
f 1
2
N
N 1
driver

Energy
min


2
Edriver  1  f  f 2  ...  f N 1 CiVDD

© Digital Integrated Circuits2nd
min
min
F 1
C
2
2
CiVDD
 L VDD
f 1
f 1
Interconnect
Delay as a Function of F and N
10,000
F = 10,000
tp/tp0
1000
p
t/0
tp
100
F = 1000
10
1
3
5
7
F = 100
9
11
Number of buffer stages N
© Digital Integrated Circuits2nd
Interconnect
Output Driver Design
0.25 mm process, CL = 20 pF
Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns
Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns
© Digital Integrated Circuits2nd
Interconnect
How to Design Large Transistors
D(rain)
Multiple
Contacts
Reduces diffusion capacitance
Reduces gate resistance
S(ource)
G(ate)
small transistors in parallel
© Digital Integrated Circuits2nd
Interconnect
Bonding Pad Design
Bonding Pad
GND
100 mm
Out
VDD
© Digital Integrated Circuits2nd
In
GND
Out
Interconnect
ESD Protection
When a chip is connected to a board, there is
unknown (potentially large) static voltage
difference
 Equalizing potentials requires (large) charge
flow through the pads
 Diodes sink this charge into the substrate –
need guard rings to pick it up.

© Digital Integrated Circuits2nd
Interconnect
ESD Protection
V DD
R
D1
X
PAD
D2
C
Diode
© Digital Integrated Circuits2nd
Interconnect
Chip Packaging
Bonding wire
•Bond wires (~25mm) are used
to connect the package to the chip
Chip
L
Mounting
cavity
L´
Lead
frame
• Pads are arranged in a frame
around the chip
• Pads are relatively large
(~100mm in 0.25mm technology),
with large pitch (100mm)
Pin
•Many chips areas are ‘pad limited’
© Digital Integrated Circuits2nd
Interconnect
Pad Frame
Layout
© Digital Integrated Circuits2nd
Die Photo
Interconnect
Chip Packaging

An alternative is ‘flip-chip’:




Pads are distributed around the chip
The soldering balls are placed on pads
The chip is ‘flipped’ onto the package
Can have many more pads
© Digital Integrated Circuits2nd
Interconnect
Tristate Buffers
V DD
V DD
En
En
Out
Out
In
En
In
En
Increased output drive
Out = In.En + Z.En
© Digital Integrated Circuits2nd
Interconnect
Reducing the swing
tpHL = CL Vswing/2
Iav
 Reducing the swing potentially yields linear
reduction in delay
 Also results in reduction in power dissipation
 Delay penalty is paid by the receiver
 Requires use of “sense amplifier” to restore signal
level
 Frequently designed differentially (e.g. LVDS)
© Digital Integrated Circuits2nd
Interconnect
Single-Ended Static Driver and
Receiver
VDD
VDD
VDD
VDD L
Out
In
VDD L
Out
CL
driver
© Digital Integrated Circuits2nd
receiver
Interconnect
Dynamic Reduced Swing Network
f
VDD
VDD
M2
M4
Bus
In1.f
M1
In2.f
Cbus
Out
M3
Cout
2.5
V
2
V
asym
bus
V
1.5
V(Volt)
sym
f
1
0.5
0
© Digital Integrated Circuits2nd
0
2
4
6
time (ns)
8
10
12
Interconnect
INTERCONNECT
© Digital Integrated Circuits2nd
Interconnect
Impact of Resistance
We have already learned how to drive RC
interconnect
 Impact of resistance is commonly seen in
power supply distribution:

 IR drop
 Voltage variations

Power supply is distributed to minimize the IR
drop and the change in current due to
switching of gates
© Digital Integrated Circuits2nd
Interconnect
RI Introduced Noise
V DD
f
pre
I
R9
V DD 2 D V 9
X
M1
I
DV
DV
R
© Digital Integrated Circuits2nd
Interconnect
Power Dissipation Trends
160
140
120
100
80
60
40
20
0

3.5
2.5
2
1.5
1


0
EV4 EV5 EV6 EV7 EV8

Supply Current
3.5
120
3
100
2.5
80
2
60
1.5
40
1
20
0.5
0
Better cooling technology needed
Supply current is increasing faster!
OnOn-chip signal integrity will be a major
issue
Power and current distribution are critical
Opportunities to slow power growth


Voltage (V)
Current (A)

0.5
140
Power consumption is increasing

3
Voltage (V)
Power (W)
Power Dissipation



Accelerate Vdd scaling
Low κ dielectrics & thinner (Cu)
interconnect
SOI circuit innovations
Clock system design
micromicro-architecture
L
o
w
κ
d i e l e c t r i c s
&
t h i n
n
e r
( C
u
)
0
EV4 EV5 EV6 EV7 EV8
© Digital Integrated Circuits2nd
ASP DAC 2000
19
Interconnect
Resistance and the Power
Distribution Problem
After
Before
• Requires fast and accurate peak current prediction
• Heavily influenced by packaging technology
© Digital Integrated Circuits2nd
Source: Cadence
Interconnect
Power Distribution
Low-level distribution is in Metal 1
 Power has to be ‘strapped’ in higher layers of
metal.
 The spacing is set by IR drop,
electromigration, inductive effects
 Always use multiple contacts on straps

© Digital Integrated Circuits2nd
Interconnect
Power and Ground Distribution
GND
VDD
Logic
Logic
VDD
GND
(a) Finger-shaped network
© Digital Integrated Circuits2nd
VDD
GND
(b) Network with multiple supply pins
Interconnect
3 Metal Layer Approach (EV4)
3rd “coarse and thick” metal layer added to the
technology for EV4 design
Power supplied from two sides of the die via 3rd metal layer
2nd metal layer used to form power grid
90% of 3rd metal layer used for power/clock routing
Metal 3
Metal 2
Metal 1
© Digital Integrated Circuits2nd
Courtesy Compaq
Interconnect
4 Metal Layers Approach (EV5)
4th “coarse and thick” metal layer added to the
technology for EV5 design
Power supplied from four sides of the die
Grid strapping done all in coarse metal
90% of 3rd and 4th metals used for power/clock routing
Metal 4
Metal 3
Metal 2
Metal 1
© Digital Integrated Circuits2nd
Courtesy Compaq
Interconnect
6 Metal Layer Approach – EV6
2 reference plane metal layers added to the
technology for EV6 design
Solid planes dedicated to Vdd/Vss
Significantly lowers resistance of grid
Lowers on-chip inductance
RP2/Vdd
Metal 4
Metal 3
RP1/Vss
Metal 2
Metal 1
© Digital Integrated Circuits2nd
Courtesy Compaq
Interconnect
Electromigration (1)
Limits dc-current to 1 mA/mm
© Digital Integrated Circuits2nd
Interconnect
Electromigration (2)
© Digital Integrated Circuits2nd
Interconnect
Resistivity and Performance
Tr
The distributed rc-line
R1
RN-1
R2
C1
C2
RN
CN-1
CN
Vin
2.5
Delay ~
L2
x = L/4
voltage (V)
Diffused signal
propagation
x= L/10
2
1.5
x = L/2
1
x= L
0.5
0
© Digital Integrated Circuits2nd
0
0.5
1
1.5
2
2.5
3
time (nsec)
3.5
4
4.5
5
Interconnect
The Global Wire Problem
Td  0.377 RwCw  0.693Rd Cout  Rd Cw  RwCout 
Challenges


No further improvements to be expected after the
introduction of Copper (superconducting, optical?)
Design solutions
 Use of fat wires
 Insert repeaters — but might become prohibitive (power, area)
 Efficient chip floorplanning

Towards “communication-based” design
 How to deal with latency?
 Is synchronicity an absolute necessity?
© Digital Integrated Circuits2nd
Interconnect
Interconnect Projections: Copper



Copper is planned in full sub-0.25
mm process flows and large-scale
designs (IBM, Motorola, IEDM97)
With cladding and other effects, Cu
~ 2.2 mW-cm vs. 3.5 for Al(Cu) 
40% reduction in resistance
Electromigration improvement;
100X longer lifetime (IBM,
IEDM97)
 Electromigration is a limiting factor
beyond 0.18 mm if Al is used (HP,
IEDM95)
© Digital Integrated Circuits2nd
Vias
Interconnect
Interconnect:
# of Wiring Layers
# of metal layers is steadily increasing due to:
 = 2.2
mW-cm
M6
• Increasing die size and device count: we need
more wires and longer wires to connect
everything
Tins
• Rising need for a hierarchical wiring network;
M5
W
local wires with high density and global wires with
low RC
S
M4
H
3.5
Minimum Widths (Relative)
4.0
3.5
3.0
M3
3.0
2.5
2.5
2.0
M2
M5
M4
1.5
M1
1.0
poly
0.5
0.25 mm wiring stack
0.0
M3
M2
substrate
© Digital Integrated Circuits2nd
Minimum Spacing (Relative)
M5
2.0
M4
M3
1.5
M1
1.0
Poly
0.5
M2
M1
Poly
0.0
m
m
m
m
m
m
m
m
m
m
Interconnect
Diagonal Wiring
destination
diagonal
y
source
x
Manhattan
• 20+% Interconnect length reduction
• Clock speed
Signal integrity
Power integrity
• 15+% Smaller chips
plus 30+% via reduction
© Digital Integrated Circuits2nd
Courtesy Cadence X-initiative
Interconnect
Using Bypasses
Driver
WL
Polysilicon word line
Metal word line
Driving a word line from both sides
Metal bypass
WL
K cells
Polysilicon word line
Using a metal bypass
© Digital Integrated Circuits2nd
Interconnect
Reducing RC-delay
Repeater
(chapter 5)
© Digital Integrated Circuits2nd
Interconnect
Repeater Insertion (Revisited)
Taking the repeater loading into account
For a given technology and a given interconnect layer, there exists
an optimal length of the wire segments between repeaters. The
delay of these wire segments is independent of the routing layer!
© Digital Integrated Circuits2nd
Interconnect
INTERCONNECT
© Digital Integrated Circuits2nd
Interconnect
L di/dt
V DD
L
i(t)
V ’DD
V out
V in
CL
Impact of inductance on supply
voltages:
• Change in current induces a
change in voltage
• Longer supply lines have larger L
GND ’
L
© Digital Integrated Circuits2nd
Interconnect
2.5
2.5
2
2
1.5
1.5
out
(V)
L di/dt: Simulation
1
0.5
0.5
V
1
0
0
0
0.5
1
1.5
2
x 10
Without inductors
With inductors
0.02
0
decoupled
0
0.5
1
1.5
1
1.5
2
x 10
-9
0.02
0
0
0.5
1
1.5
-9
x 10
1
0.5
2
-9
0.5
L
V (V)
2
x 10
1
0.5
0.04
L
i (A)
0.04
0
-9
0
0
0
0.5
1
time (nsec)
1.5
2
x 10
-9
Input rise/fall time: 50 psec
© Digital Integrated Circuits2nd
0
0.5
1
time (nsec)
1.5
2
x 10
-9
Input rise/fall time: 800 psec
Interconnect
Dealing with Ldi/dt








Separate power pins for I/O pads and chip core.
Multiple power and ground pins.
Careful selection of the positions of the power
and ground pins on the package.
Increase the rise and fall times of the off-chip
signals to the maximum extent allowable.
Schedule current-consuming transitions.
Use advanced packaging technologies.
Add decoupling capacitances on the board.
Add decoupling capacitances on the chip.
© Digital Integrated Circuits2nd
Interconnect
Choosing the Right Pin
Bonding wire
Chip
L
Mounting
cavity
L´
Lead
frame
Pin
© Digital Integrated Circuits2nd
Interconnect
Decoupling Capacitors
1
Board
wiring
Bonding
wire
Cd
SUPPLY
CHIP
2
Decoupling
capacitor
Decoupling capacitors are added:
• on the board (right under the supply pins)
• on the chip (under the supply straps, near large buffers)
© Digital Integrated Circuits2nd
Interconnect
De-coupling Capacitor Ratios

EV4
 total effective switching capacitance = 12.5nF
 128nF of de-coupling capacitance
 de-coupling/switching capacitance ~ 10x

EV5
 13.9nF of switching capacitance
 160nF of de-coupling capacitance

EV6
 34nF of effective switching capacitance
 320nF of de-coupling capacitance -- not enough!
© Digital Integrated Circuits2nd
Source: B. Herrick (Compaq)
Interconnect
EV6 De-coupling Capacitance
Design for Idd= 25 A @ Vdd = 2.2 V, f = 600
MHz
 0.32-µF of on-chip de-coupling capacitance was
added
– Under major busses and around major gridded clock drivers
– Occupies 15-20% of die area
 1-µF 2-cm2 Wirebond Attached Chip Capacitor
(WACC) significantly increases “Near-Chip” decoupling
– 160 Vdd/Vss bondwire pairs on the WACC minimize
inductance
© Digital Integrated Circuits2nd
Source: B. Herrick (Compaq)
Interconnect
EV6 WACC
389 Signal - 198 VDD/VSS Pins
389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
WACC
Microprocessor
Heat Slug
587 IPGA
© Digital Integrated Circuits2nd
Source: B. Herrick (Compaq)
Interconnect
The Transmission Line
l
V in
l
r
l
r
g
c
l
r
g
c
x
g
c
r
V out
g
c
The Wave Equation
© Digital Integrated Circuits2nd
Interconnect
Design Rules of Thumb

Transmission line effects should be considered when the
rise or fall time of the input signal (tr, tf) is smaller than the
time-of-flight of the transmission line (tflight).
tr (tf) << 2.5 tflight

Transmission line effects should only be considered when
the total resistance of the wire is limited:
R < 5 Z0

The transmission line is considered lossless when the total
resistance is substantially smaller than the characteristic
impedance,
R < Z0/2
© Digital Integrated Circuits2nd
Interconnect
Should we be worried?

Transmission line effects
cause overshooting and nonmonotonic behavior
Clock signals in 400 MHz IBM Microprocessor
(measured using e-beam prober) [Restle98]
© Digital Integrated Circuits2nd
Interconnect
Matched Termination
Z0
Z0
ZL
Series Source Termination
ZS
Z0
Z0
Parallel Destination Termination
© Digital Integrated Circuits2nd
Interconnect
Segmented Matched Line Driver
In
VDD
Z0
s0
s1
c1
© Digital Integrated Circuits2nd
s2
c2
ZL
sn
cn
GND
Interconnect
Parallel Termination─
Transistors as Resistors
V dd
2
)V
1.9
Mr
Out
Vdd
Mr
V dd
M rp
M rn
V bb
Out
© Digital Integrated Circuits2nd
Out
NMOS only
1.8
1.7
PMOS only
1.6
1.5
1.4
1.3
NMOS-PMOS
1.2
PMOS
with-1V bias(
1.1
Normalized
Resistance
1
0
0.5
1
1.5
2
2.5
V R (Volt)
Interconnect
Output Driver with Varying
Terminations
4
V
d
3
V
V
2
V DD
in
s
1
L = 2.5 nH
120
L = 2.5 nH
V in
Vs
275
Z 0 = 50 W
C L= 5 pF
Clamping
Diodes
0
V DD
1
0
Vd
1
2
3
4
5
6
7
8
Initial design
CL
4
L= 2.5 nH
o(V)
ut
V
3
V
2
V
V
d
in
s
1
0
1
o(V)
ut
V
0
1
2
3
4
5
6
7
8
time (sec)
Revised design with matched driver impedance
© Digital Integrated Circuits2nd
Interconnect
The “Network-on-a-Chip”
Embedded
Processors
Memory
Sub-system
Interconnect Backplane
Accelators
© Digital Integrated Circuits2nd
Configurable
Accelerators
Peripherals
Interconnect