TAB & GAB
Production Readiness Review
Hal Evans
for the Nevis Group
In a Nutshell


We have the components, the boards, the money…
Should we assemble the TABs and GABs?
Concentrate on

Hardware Design & Testing  Production Readiness
Less Emphasis

H. Evans
Project Justification, Algorithm Devel, Install/Commission
TAB/GAB PRR: 7-Oct-04
1
The Nevis Team
Students
Chad Johnson, Jovan Mitrevski
Postdocs
Sabine Lammers, TBA
Engineers
Jaro Ban, Bill Sippach + Nevis Tech’s
Faculty
Hal Evans, John Parsons
H. Evans
TAB/GAB PRR: 7-Oct-04
2
The Tevatron Landscape
Accelerator Plan: FY 05-09
300
12
2.8e32 !
10
install upgrades
-1
Peak
200
8
Phases
30
-2
-1
Peak Luminosity (x10 cm sec )
250
Total Integrated Luminosity (fb)
DRAFT June04
Total
150
6
current peak L
100
4
50
2
0
0
9/29/03
9/29/04
9/30/05
10/1/06
10/2/07
10/2/08
10/3/09
Date
H. Evans
TAB/GAB PRR: 7-Oct-04
3
Trigger Challenges
Trigger
Run IIa Definition
Example Channel
L1 Rate [kHz]
(no upgrade)
L1 Rate [kHz]
(w/ upgrade)
EM
1 EM TT > 10 GeV
Wev
WHevjj
1.3
0.7
DiEM
1 EM TT > 7 GeV
2 EM TT > 5 GeV
Zee
ZHeejj
0.5
0.1
Muon
1 Mu Pt > 11 GeV
CFT Track
Wv
WHvjj
6
1.1
Di-Mu
2 Mu Pt > 3 GeV
CFT Tracks
Z/
ZHjj
0.4
<0.1
e + Jets
1 EM TT > 7 GeV
2 Had TT > 5 GeV
WHevjj
ttev+jets
0.8
0.2
Mu + Jet
1 Mu Pt > 3 GeV
1 Had TT > 5 GeV
WHvjj
ttv+jets
<0.1
<0.1
Jet+MEt
2 TT > 5 GeV
MEt > 10 GeV
ZHvvbb
2.1
0.8
Mu+EM
1 Mu Pt > 3 GeV + Trk
1 EM TT > 5 GeV
HWW,ZZ
<0.1
<0.1
Iso Trk
1 Iso Trk Pt > 10 GeV
H , Wv
17
1.0
Di-Trk
1 Iso Trk Pt > 10 GeV
2 Trk Pt > 5 GeV
1 Trk matched w/ EM
H
0.6
<0.1
~30
TAB/GAB PRR: 7-Oct-04
3.9
Total
H.Rate
Evans
Luminosity
21032
BC
396 ns
L1 Limit
~3 kHz
4
Meeting the Challenge
Detector
Level 1
2.5 Mhz
Level 2
3 khz
Detector
1 khz
2.5 Mhz
CAL
L1Cal
L2Cal
c/f PS
L1PS
L2PS
CFT
L1CTT
L2CTT
c/f PS
L2STT
CFT
L2Mu
SMT
SMT
MU
FPD
Lumi
L1Mu
L1FPD
Framework
Run IIa
H. Evans
CAL
Level 3
Level 2
3 khz
L1Cal
L2Cal
CalTrk
MU
Global
L2
Level 1
FPD
Lumi
TAB/GAB PRR: 7-Oct-04
L1PS
L1CTT
L2PS
L2CTT
L2STT
L1Mu
L2Mu
L1FPD
Framework
Run IIb
Global
L2
Level 35
L1Cal Overview
Cables: UIC
Cal-Track Match:
Arizona
Digitize
Filter +
E  Et
Find EM
LMs
Build
EM
Find EM+H
LMs
Build
JETs
ADF: Saclay, MSU
Et, Ex, Ey
Sums
H. Evans
TAB:
Nevis
TAB/GAB PRR:
7-Oct-04
Build
TAUs
Construct
And/Or’s
GAB: Nevis
6
Board Rundown
  : In / Out
Custom Board
No
Purpose
ADF: ACD/Dig. Filt.
80
digitize, filter, E-to-Et
SCLD: ADF Timing F’out
4
ADF control/timing
TAB: Trig Algo Board
8
algo’s, Cal-Trk out, sums
GAB: Global Algo Board
1
sums, trigs to FWK
all
VME/SCL Board
1
VME & timing to TAB/GAB
all
Splitter
4
Collect data in parallel w/
IIa System
4 TTs
(8 chan’s)
Match BLS cables to ADF
inputs w/out rerunning
84 / 244
BLS-ADF Cables & Patch
Panels, etc.
H. Evans
TAB/GAB PRR: 7-Oct-04
44 / 44
all
409 / 314
7
Algorithm Flow
Find Local
Maxima
Make
Regions of
Interest
TT Input
(corrected w/ ICR)
























Construct
Objects
Compare to
Thresholds
5
5
5
1
5
5
TT Space
H. Evans
5
5
5
5
5
5
5
5
1
1
1
1
5
6


ROI Space

LM Space
TAB/GAB PRR: 7-Oct-04
Jet Space
8
Objects
Object Outputs
Cuts during Construction
Thresholds (i = 1-7)
EM
ET EM(2x2)
 HD(4x4) < EM(2x2) / 23
 EM(ring) < cut (adc cnts)
ET > EM Thr-i
Jet
ET EM+HD(4x4)
 none
ET > Jet Thr-i
Tau
ET EM+HD(2x2)
R = EM+HD(2x2) / (4x4)
 [(2x2) x (1/4x4)LUT8-bit] 8-bit
=R
ET & R vs Thr
(t.b.d.)
Sums
 EM+HD(4x1) for
 = 2,3,4,5
 currently none
 (TT > thr, || < cut,…)
none
Data Needed for
Declustering
Jet Algo
EM Algo
Had Isolation
X
EM Isolation
ET Cluster
Region
O
O O
O
O
O
O
O
O
O
O
O
X
O
O
O
O
O
O
O
O
O
O
O
O
Tau Algo
RoI
EM + Had
Isolation
RoI / Tau cluster
RoI / EM cluster
Cand. RoI center
H. Evans
X
RoI center used for
compares
TAB/GAB PRR: 7-Oct-04
9
Algo’s vs Architecture
TAB 7
=31-28
TAB 6
=27-24
TAB 5
TAB 4
=23-20
=19-16
TAB 3
TAB 2
=15-12
TAB 1
=11-8
TAB 0
=7-4
=3-0
10
=39-0
=31-28
ADFs
79-70
1.
=39-0
=27-24
ADFs
69-60
=39-0
=23-20
ADFs5950
=39-0
=19-16
ADFs
49-40
ADFs
29-20
ADFs
19-10
=39-0
=3-0
ADFs
9-0
 SW Chip input 9x9
 SW Chip output 4x4
Algo
TTs for 1 LM
LMs / SW
2,0,1
4x4
6x6
2,1,1
6x6
4x4
2,2,1
8x8
2x2
3,-1,1
5x5
5x5
3,0,1
TAB/GAB PRR: 7-Oct-04
7x7
3x3
Minimize Data Sharing
 3 Identical outputs from each
ADF (4x4x2 TTs)
Each TAB:
40x9 inputs & 31x4 outputs
H. Evans
ADFs
39-30
=39-0
=7-4
3. Construct Local Maxima
Use ICR in Jets +
Data to Cal-Track
 All eta to each TAB
2.
=39-0
=11-8
=39-0
=15-12
10
10
10
VME/SCL Board

New Comp. of TAB/GAB system



proposed:
change control:
VME (custom protocol)



not enough space on TAB for
standard VME
D0 Trigger Timing (SCL)
(previously part of GAB)
Why Split off from GAB



VME
interface
Interfaces to


Feb 03
Mar 03
local osc’s & f’out
(standalone runs)
simplifies system design &
maintenance
allows speedy testing of
prototype TAB
Fully Tested:
Jun 03
serial out x9
(VME & SCL)
H. Evans
TAB/GAB PRR: 7-Oct-04
SCL
interface
DONE
11
TAB
Channel Link Receivers (x30)
DC/DC conv
power
VME/SCL
ADF Inputs (x30)
thru custom b’plane
L2/L3 Output
(optical)
Output to GAB
Global Chip
Output to
Cal-Track (x3)
H. Evans
Sliding Windows
Chips (x10)
TAB/GAB PRR: 7-Oct-04
12
GAB
power
VME/SCL
L2/L3
out to
TFW
TAB
Inputs
(x8)
H. Evans
TAB/GAB PRR: 7-Oct-04
13
Data-Eye View of L1Cal
L2Cal
& L3
L2Cal
& L3
18016b
ADF
S.W. 9
Rcv 3
x 10
x 30
x 80
S.W. 0
ADF
TAB
all data xmit &
math operations done
bit-serially @ 90 MHz
H. Evans
4912b
+ 312b sp.
2112b
+ 412b sp.
x8
64b
+ 216b sp.
GAB
CalTrk
TAB/GAB PRR: 7-Oct-04
And/Or
Rcv 0
516b
516b
+ 216b sp.
+516b
216b sp.
368b
+ 68b sp.
Global
10
???16b
+ 16b sp.
CalTrk
14
TAB to GAB Data Path
Intra-TAB: SWGlobal
 Clusters
12 lines


16-EM + 16-H+ 16-TAU
each clust = 3-bits
(highest of 7 thr’s pass)
TAB to GAB: GlobalRcv
 EM Counts
12 words
 H Counts
12 words
 TAU Counts
12 words

 Sum(EM+H Et)


sum over  for each 
 Data for L2/L3

4 lines
6 thr’s – 2 bit counts
S,C,N regions
2 lines
on L1 Accept
 Sum(EM+H)

3 words
Et, Ex, Ey
 Stat/BX/Frame
3 lines
 Stat/Ctrl/…
7 words
 Spare
4 lines
 Spare
3 words
All Formats: www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_gab_comm.html
H. Evans
TAB/GAB PRR: 7-Oct-04
15
Data Transmission
Link
Method
Clock
ADF to TAB
LVDS – Channel Link xmit/rcvr
424 MHz
TAB to GAB
LVDS – Stratix xmit/rcvr
636 MHz
TAB to Cal-Track
Gbit Cu Coax – Arizona SLDB xmit/rcvr
950 MHz
TAB/GAB to L2/L3
G-Link Optical xmit
Optical split for L2/L3 branch
GAB to TFW
ECL Ribbon Cable
SCL to TAB/GAB
Simple Serial Protocol via VME/SCL
clk7, init, turn, l1_accept, pulse, l1_error
VME to TAB/GAB
Simple Serial Protocol via VME/SCL
clk, frame, addr, data, frame-out, data-out
H. Evans
TAB/GAB PRR: 7-Oct-04
7.6 MHz
16
TAB/GAB Timeline
May 03
 VME/SCL prototype received
Jun 03
 TAB prototype received
Jul 03
 VME/SCL prototype testing complete (receives SCL signals at DØ)
Aug 03
 TAB prototype testing complete
Oct 03
 1st prototype integration test
SCLADF,TAB; ADFTAB; TABCal-Track
Feb 04
 GAB prototype received
Mar 04
 2nd prototype integration test
TAB  existing L1Cal VRB
Apr 04
 2 TABs  GAB test
May 04
 TAB/GAB crate custom backplane received, installed, tested
 GAB prototype testing complete (TAB to GAB & internal)
No Layout Problems found with any of the Boards
H. Evans
TAB/GAB PRR: 7-Oct-04
17
Internal TAB Testing
GAB data
TAB
Simulation
MC Events
algo output
(Trigger Rate Tool)
raw TTs
(x-checked w/ tsim_l1cal2b)
Cal-Trk data
L2/L3 data
bit by bit comp
bit by bit comp
TT inputs
SW
algos 9
Chan Link
G-Link
raw TTs
input mem
Global
Algos
algo output
Cal-Trk data
TT inputs
Chan Link
raw TTs
algo output
H. Evans
GAB
GAB data
Cal-Trk
SW
algos 0
VME access
L2/L3 data
• all internal connections tested
(tau only partially)
• using compare’s to debug
TAB/GAB PRR: 7-Oct-04
firmware & simulation
18
Internal GAB Testing
MC Events
TFW data
GAB data
TAB
Simulation
algo output
(Trigger Rate Tool)
raw TTs
Cal-Trk data
rcvr output
L2/L3 data
L2/L3 data
bit by bit comp
input mem
from TAB
G-Link
Rcvr
3
input mem
rcvr output
input mem
from TAB
L2/L3 data
Global
Chip
Rcvr
0
ECL Out
TFW data
rcvr output
input data
• O(10??) events tested (rcvr  Global)  those lines tested
• Global  ECL Xmit signals tested with ECL Test Card
H. Evans
TAB/GAB PRR: 7-Oct-04
19
TAB/GAB I/O
 ADF  TAB

Channel Link Parameters


 SCL Timing & VME


extensively exercised at Nevis
and DØ
used in ADFTAB tests

H. Evans
Clock (MHz)
BER Limit
50
<1.1e-14
60
<2.2e-15
75
<3.0e-15
90
<3.7e-15
At DØ w/ ADF



probed w/ Test Card
insensitive to: PLL range,
deskew, DC balance, preemphasis
error free (parity) xmit for >15
minutes
working on bit-by-bit check
Use of Channel Link provides
clear spec !
TAB/GAB PRR: 7-Oct-04
20
TAB/GAB I/O (cont)
 TAB  L2/L3


several events sent to L1Cal
VRB under DØ timing
TAB events to tape soon
 TAB  GAB

LVDS transmission checked w/
Test Card



safety margin of >400 ps
>109 events TABGAB
O(106) events 2 TABsGAB
 GAB  TFW
 TAB  Cal-Track


sync’ed TAB output w/ L1Muon
board at DØ
varied TAB output & saw corr.
variation in L1Muon Trigger rate

Signal paths checked using ECL
Test Card
 GAB  L2/L3

identical to TAB
 Latency: SW inp  SLDB in
= ~630 ns
All
Internal
External Hardware Paths Checked
H. Evans
TAB/GAB
PRR:&7-Oct-04
21
Remaining Firmware
TAB





Tau algorithm to be verified
Change to Atlas EM algo ?
Finalize L2 output
Finalize monitoring
Simulation of full TAB
GAB

Only skeleton of Global chip firmware exists
Need to add



H. Evans
Trigger Terms
Monitoring
L2 output
TAB/GAB PRR: 7-Oct-04
22
What’s Next ?
 If we’re given the Green Light – produce:


10 TABs
3 GABs
Task
Dur
Start
End
Delivery of rest of components
2w
10/11/04
10/22/04
Assemble boards (mainly Columbia administration)
6w
10/11/04
11/19/04
Test TABs/GABs at Nevis
 goal: run fully populated TAB/GAB crate
 some dependence of availability of engineers
12w
11/22/04
02/11/05
 Testing at Fermilab

Have (nearly) enough hardware now for Nevis + DØ Tests


2 VME/SCLs; 2 TABs; 1 GAB; 2 TAB/GAB crates
Can send out some new boards as they pass tests
H. Evans
TAB/GAB PRR: 7-Oct-04
23
Conclusions
We believe that we’re ready to assemble

hardware has been checked



no changes from prototype
all components ordered (most arrived) + PCBs here
money is in hand (Hal’s CAREER grant)
Risks of Going Forward


TAB: essentially none
GAB: some hardware paths not yet fully tested
Risks of Delay


PCBs are aging (produced ~1 year ago)
Atlas efforts intensifying
THANKS to the Committee for their Help !
H. Evans
TAB/GAB PRR: 7-Oct-04
24
Extra Slides
H. Evans
TAB/GAB PRR: 7-Oct-04
25
“2x2” EM Algo
Simple “1x2 or 2x1” Algorithm
Serial Adders
EM(0,0)
Had Isolation
EM(0,1)
LM
Finder
EM(1,0)
X
EM Isolation
EM(1,1)
RoI / EM cluster
“1x2 or 2x1” EM Algo
Serial Adders
H. Evans
EM(0,0)
Serial Comparators
LM
Finder
EM(0,1)
EM(1,0)
Had
Isolation
X
EM(0,0)
EM
Isolation
• No extra latency
RoI / EM cluster
• Chosen cluster still indexed by LL
corner of 2x2 region
TAB/GAB PRR: 7-Oct-04
26
Data in the TAB
H. Evans
TAB/GAB PRR: 7-Oct-04
27
SW to Global Chip Data
EM/Jet/Tau Results

12 words
for each algo &  = 2,3,4,5 send out 12-bit word encoding highest
threshold (7-1 or 0=none) passed by each of the four ’s in that 

11
i
highest thr =5
09
08
06
highest thr =4
05
03
highest thr =3
Global Sums


02
00
highest thr =2
4 words
for each  = 2,3,4,5 send out 12-bit word containing EM+HD over
four ’s in that 
11
00
 ET (EM+HD) over  = 2,3,4,5
i
Simulation Code for all this
1.
2.
H. Evans
tsim_l1cal2b
standalone
relies on DØ software environ.
being tested w/ hardware
TAB/GAB PRR: 7-Oct-04
28
TAB to GAB Data
 EM/Jet/Tau Results
36 words
for each algo &  = 2,3,4,5 send out encoded 12-bit words for  =
S,C,N containing 2-bit counts of no. of objects passing each of 6
thresholds



11
i
j
cnt thr-6
10
09
08 07
cnt thr-5
06
cnt thr-4
05
04
cnt thr-3
03
02
cnt thr-2
01
00
cnt thr-1
i = 2,3,4,5 ; j = S,C,N
 Global Sums
3 words


2-5
0-39
 ET (EM+HD)
2-5
0-39
 Ex (EM+HD)
2-5
0-39
 Ey (EM+HD)
H. Evans
11
00
TAB/GAB PRR: 7-Oct-04
29
Data to Cal-Track Match
Output from TAB Global Chip (10)
Bits 15 – 08
Bits 07 – 00
1
JET Mask:  = i+3
EM Mask:  = i+3
2
JET Mask:  = i+2
EM Mask:  = i+2
3
JET Mask:  = i+1
EM Mask:  = i+1
4
JET Mask:  = i
EM Mask:  = i
5
0
0
6
0
0
No.
7
Longitudinal Parity
Mask Definition:


Bit 07
Bits 06 – 00
unused
set if threshold j is passed
www.nevis.columbia.edu/~evans/l1cal/hardware/tab/tab_to_caltrack.html
H. Evans
TAB/GAB PRR: 7-Oct-04
30
Short Term Plans
Task
Comments
Timescale
Simulation
Shift studies into high gear
now
TAB  L2/L3
Write data to tape (test unpacking)
Oct
ADFv1  TAB
Long Term Data Transfer Tests
Oct
TAB/GAB
Fully Automated Event Verification
Nov
GAB
Implement 1st And/Or terms
End 04
ADFv2  TAB
First Integration
End 04
H. Evans
TAB/GAB PRR: 7-Oct-04
31
Road to Installation (Jul 05)
1. Operations & Stability
a.
b.
c.
d.
e.
run test system
crashes/deadtime
reliable downloading
monitoring tools
param determination
unpacker/reco stable
meas. in test syst.
use in test syst.
software in place
software in place
data from test syst
2. Trigger Quality
data & MC
a. rates & efficiencies
b. trigger definitions (L1,L2,L3)

pred w/ MC – verify w/ data
in place well beforehand
filter coeff’s, thresholds, and/or terms, trigger list
Note: all of these must be Documented
H. Evans
TAB/GAB PRR: 7-Oct-04
32
Testing Trigger Quality
Splitters  Data Available before Installation

at most 16-EM + 16-H  cannot test Sliding Windows
Possible Chain to Rate/Eff Estimates
1. Define Triggers

trig-list, and/or, thresh, filt. coeff’s
2. Using Splitter Data derive TT response


compare ADF Et(TT) output w/ Precision Readout
 correct MC modeling of Et(TT)
probe pathological cases using TWG
3. MC models TAB Algorithms


sliding windows algorithm is deterministic
use standalone MC to look for algorithm pathologies
4. MC models And/Or terms & Trigger List  Rates & Eff’s

H. Evans
need to test QCD MC vs. Data w/ Run IIa Trigger
TAB/GAB PRR: 7-Oct-04
33