Design and Implementation of VLSI Systems
(EN1600)
Lecture11: Delay Estimation
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’08
Circuit characterization: delay and power
estimation
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Delay estimation
Logical effort for delay estimation
Power estimation
Interconnects and wire engineering
Scaling theory
S. Reda EN160 SP’08
Delay definitions
• tpdr: rising propagation delay
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output crossing VDD/2
• tpd: average propagation delay. tpd = (tpdr + tpdf)/2
• tcdr: rising contamination (best-case) delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination (best-case) delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay. tpd = (tcdr + tcdf)/2
• tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
S. Reda EN160 SP’08
How to calculate delay? Just run SPICE!
• Time consuming
• Not very useful for designers in evaluating different options
and optimizing different parameters
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
• We need a simple way to estimate delay for “what if” scenarios.
• Fidelity vs. accuracy
S. Reda EN160 SP’08
Transistor resistance
In the linear region
• Not accurate, but at least shows that the resistance is proportional
to L/W and decreases with Vgs
• If R/C are for a unit size transistor then a transistor of K unit
width has KC capacitance and R/K resistance
• The resistance of a PMOS transistor = 2× resistance of NMOS
transistor of the same size
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Switch-level RC models
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
g
d
k
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
S. Reda EN160 SP’08
s
d
k
s
kC
g
kC
d
Inverter RC delay estimate
• Estimate the delay of a fanout-of-1 inverter in response to a step
input function
2C
R
A
2 Y
2
1
1
2C
2C
2C
Y
R
C
C
tpd = 6RC
S. Reda EN160 SP’08
2C
R
C
C
C
Elmore delay model
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

t pd 
Ri to sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N
R1
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R2
R3
C1
C2
RN
C3
CN
Example: 3-input NAND gate
• Sketch a 3-input NAND with transistor widths chosen to achieve
effective rise and fall resistances equal to a unit inverter (R).
2
2
2
3
3
3
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Example: 3-input NAND gate
• Annotate the 3-input NAND gate with gate and diffusion capacitance
2C
2
2C
2C
2C
2
2C
2
2C
3C
3C
3C
S. Reda EN160 SP’08
2C
2C
2C
3
3
3
3C
3C
3C
3C
Example: 3-input NAND gate
•
Annotate the 3-input NAND gate with gate and diffusion capacitance
2
2
3
5C
5C
5C
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2
3
3
9C
3C
3C
Computing the rise and fall delays
• Estimate rising and falling propagation delays of a 2input NAND driving h identical gates.
2
2
6C
A
2
B
2x
Y
(6+4h)C
x
R/2
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2C
h copies
2C
R
R/2
Y
4hC
Y
(6+4h)C
t pdr   6  4h  RC
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
Delay components
• Delay has two components:
– Parasitic delay (due to gate own diffusion capacitance)
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
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Contamination delay
• Best-case (contamination) delay can be substantially less than
propagation delay.
• Ex: If both inputs fall simultaneously
2
2
A
2
B
2x
R R
Y
(6+4h)C
6C
Y
4hC
2C
tcdr   3  2h  RC
• Order of inputs also impact propagation delay. Which is better
AB=10 -> 11 or AB=01 ->11?
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Diffusion capacitance
• we assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C
Shared
Contacted
Diffusion
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
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2C
3
7C
3C
3C
Layout Comparison
• Which layout is better?
VDD
A
VDD
B
Y
GND
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A
B
Y
GND