Dedicated to my parents
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ACKNOWLEDGEMENTS
First, I would like to thank my major professor, Dr. Reginald J. Perry for his
guidance and support. I thank Dr. Simon Foo and Dr. Bruce Harvey for their guidance as
members of my supervisory committee. I thank Fermi National Acceleration Laboratory,
Department of Physics, Boston University and the Department of Physics, Florida State
University for giving me the opportunity to work on the D0 project. I thank the National
Science Foundation and the U.S. Department of Energy for funding the D0 project. I
especially thank Dr. Horst Wahl at Department of Physics, FSU for helping me
understand the intricacies of this project from the point of view of a physicist. I thank the
Departments of Electrical and Computer Engineering and Physics at FSU for their
financial support. Finally, I wish to thank my family and friends for their support during
my tenure as a graduate student.
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TABLE OF CONTENTS
List of Tables
List of Figures
Abstract
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X
xi
Chapter
1. INTRODUCTION
2.
1
THE D0 DETECTOR AT THE FERMI NATIONAL
ACCELERATION LABORATORY
The D0 Detector
3.
6
8
The D0 trigger and data acquisition system
Level_1
Level_2
Level_3
10
10
12
13
The Silicon Track Trigger (STT)
14
The Silicon track cluster card (STC)
Strip Reader
Centroid Finder
Hit Filter
L3 buffer
Main control module
16
16
17
18
18
19
DETAILED DESCRIPTION OF THE MAIN DATA PATH
21
Design features
21
Design parameters
Monitor space
Miscellaneous memory
Gain offset memory
Test data LUT
Road data LUT
22
22
23
25
25
25
Strip Reader
SMT Data Filter module
SMT Test Select module
Strip Reader Control module
26
26
27
28
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4.
5.
6.
Centroid finder
Cluster Finder module
Centroid Calculator module
29
29
32
Hit Filter
Hit Filter Control module
Z- centroids module
Comparator module
Hit Register module
Hit Format module
Hit Read out module
33
34
35
35
36
36
37
SIMULATION RESULTS OF THE VHDL MODEL AND
COMPARISON WITH A MATLAB MODEL
38
The VHDL Model
SMT Data Filter
Strip Reader Control
Cluster Finder
Centroid Calculator
Hit Filter
38
39
39
41
42
43
The MATLAB Model
Main design
Read downloaded parameters
SMT Filter module
Strip Reader
Cluster Finder
Centroid Calculator
Hit Filter
45
45
45
46
46
46
46
47
DESIGN ISSUES FOR IMPLEMENTATION OF THE MAIN
DATA PATH
48
The Hit Filter design approaches
48
The different implementation schemes of the overall design
Approach 1
Approach 2
Approach 3
Approach 4
50
50
51
52
53
Implementation of the design using Quartus software
54
57
SUMMARY
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APPENDICES
A. Flowcharts of modules of Main data path
B. Top level schematics of main data path
C. VHDL code for main data path
D. MATLAB code for MATLAB model of main data path
59
70
89
171
BIBLIOGRAPHY
191
BIOGRAPHICAL SKETCH
193
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LIST OF TABLES
Table
Page
1.1 Comparison of ALTERA and XILINX architecture and products
3
2.1 The 23-bit data at the output of the Strip Reader
17
2.2 The 17-bit data word from Centroid Finder to the Hit Filter
17
3.1 Memory mapping for the single channel
22
3.2 Miscellaneous register downloaded at 0580(HEX)
25
3.3 Data stream from SMT Data Filter to the Strip Reader Control
27
3.4 The scheme for determining the pulse area of the cluster
33
3.5 The 32-bit word format of the Z-centroids
35
3.6 The data format of the hits in the output FIFO
36
3.7 The data format of the trailer for the hits
37
4.1 Test vector for an example simulation of the data path in hexadecimal
38
4.2 Output stream from the SMT Data Filter
40
4.3 Output stream from the Strip Reader Control module
41
4.4 The clusters found by the Cluster Finder module
42
4.5 The centroids found by the Centroid Calculator module
43
4.6 The road data values extracted from the road-data, with respect to the
17-bit road data value from FRC
43
4.7 The hits obtained written into output FIFO
44
5.1 The result of comparison for putting filters in parallel
49
5.2 Results of compilation: Approach 1
50
5.3 Results of compilation: Approach 2
51
5.4 Results of compilation: Approach 3
52
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5.5 Results of compilation: Approach 4
53
5.6 Implementation of the Strip Reader module in APPEX20KE
55
5.7 Specifications of EP20K1500E
56
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LIST OF FIGURES
Figure
Page
2.1 The flow of data in the D0 trigger and data acquisition system
11
2.2 The layout of the Silicon strips in the D0 detector
14
2.3 Block diagram of the STT
15
2.4 The data flow in the main data path with reference to the modules in the
electronics
18
3.1 The detailed block diagram of the Strip Reader module
26
3.2 Detailed block of the Centroid Finder module
29
3.3 An illustration example of a five-strip cluster
30
3.4 Realization of Centroid Calculation for five-strip cluster
32
3.5 Detailed block diagram of the Hit Filter module
34
4.1 The data values in the test data stream with the corresponding strip
42
addresses
5.1 Comparison of the memory bits utilized
54
5.2 Comparison of the logic cells utilized
54
5.3 Comparison of the EABs utilized
50
x
ABSTRACT
This thesis describes the electronics for the STC, a part of the "Silicon Track
Trigger", new trigger processor which is being designed for the D0 experiment at the
Fermi National Accelerator Laboratory in Batavia, Illinois, Fermilab The silicon track
trigger project is done in collaboration between the Electrical and Computer Engineering
Department at FAMU-FSU and the Physics Departments of Florida State University,
Boston University, Columbia University, and the University at Stony Brook.
The D0 detector is a general-purpose detector for the study of antiproton-proton
collisions at high energy. The construction and operation of the detector is done by the
D0 collaboration, which presently consists of about 450 physicists from about 50
universities and research laboratories. The particle created in the proton antiproton
collisions generates signals in a silicon micro-strip detector, which can be used to
reconstruct the tracks of the particles. The new trigger processor will use these signals
from the new Silicon Micro-strip Tracker (SMT) to tag collisions in which long-lived bquarks are produced. The study of events containing b-quarks can help in addressing
many fundamental questions in particle physics. The new trigger processor will add
significantly to the physics capabilities of the D0 detector in these areas. The silicon track
cluster card (STC) accepts the digitized data from the strips in the SMT, finds clusters of
strips with charge on them, determines the centroid for these clusters, and checks which
of those centroids are within roads corresponding to candidate tracks.
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Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
(VHDL) is used to describe the behaviour model of the design. The MAXPLUS –II
synthesis tool by ALTERA Corporation was used to implement the design in FPLDs. The
final design is implemented in three FPLDs of the FLEX10K family by ALTERA
Corporation.
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