Monitor memory space
Address (Hex) Description (Each 24 bits)
0
Serr,mismatch,smt_id,seq_id,hdi_id,data
(last data word read)
1
Serr error count – Serr bit high
2
mismatch in the seq-id or the HDI-id
3
zero error count – Zero byte not found
10
# of undefined data_type clusters
11
# of axial data_type clusters
12
# of stereo data_type clusters
13
# of Z-axis data_type clusters
20-28
Data activity on Chip(I)
Miscellaneous memory space
The miscellaneous memory space constitutes of 1. Bad channel: 32 X 64 – address : 0400 – 047F
2. Chip ranges : 24 X 1 – address : 0480
3. Pulse area thresholds:36 X 4
– address : 0500 – 0503
4. Miscellaneous parameters: 20 X 1 – SEQ_ID(8),
HDI_ID(3),Disable bit(1), and Delay count (8).
– address : 0580
5. Cluster threshold values: 17 X 4
– address : 0600 – 0603
Clustering algorithm
Start
Event start
Return state - Init
Read
Read the 23 bit word
from the FIFO
D
Check_for_eof
Check for end of cluster
1. Current type different
2. Data value < threshold1
3.Current addressnot in
sequence
Yes
Calculate
No
Send the available
data values for
calculation
Main
Next
Outpeak
A
B
C
E
Peak of the cluster
> threshold2
Write
No
Yes
Init
Return state
A
A
Init
Write the cluster into L3 buffer.
Write the centroid from the
Calculator block into the output
FIFO and L3 buffer.
Load first data value
and address in
data3 and add3.
Go to read.
Return state - main
D
B
Main
Yes
data 1 <---- data 2
data 2 <---- data 3
data3 <----- ndata
same for add.Return state main
If ndata > data 3
No
data4 <--- ndata,
same for add
Return state - next
D
D
Note: To write cluster data
into L3 buffer, takes 6
cycles. The machine is in
wait state for these cycles.
Clustering algorithm (continued..)
C
Next
If ndata > data 3
Yes
No
data5 <--- ndata
Shadow registersdata_shadow1 <-- data4
data_shadow2 <--- ndata, same for add
Return state - outpeak
data 1<--- data3
data 2 <---- data 4
data3 <----- ndata, same for add.
Go to read. Return state - main
D
D
E
Outpeak
No
data_shadow1<--- data_shadow2
data_shadow2 <---- ndata
, same for add.
If ndata > data 3
Yes
data1 <--- data_shadow1
data2 <--- data_shadow2
data3 <--- ndata,
data4 and data5 <--zero
same for add
Return state - main
D
D
Hit filter Control Logic
Init
Start
Event start
E
First_load
Wait for the road_write
signal, or the last_road
signal indicating no roads
Last_road
Road_write
Last_road
Next
Yes
Is
Fifo_empty
Wait for road_write to
go low
B
Road_write
Write the road datainto
comparator. Increment
count
Is Road write
and last road
No
Read the centroid.
Hits_busy = 1
Road_event count.
A
Yes
A
C
No
A
B
C
Decide
Data type = 10
What is the data
type
Data type = 11
This is z- axis centroid
This is axial centroid.
Centroid_write
Comp_read
Read the
comparators output
D
Write the centroid in a
the required format into
the z- axis FIFO.
A
Hit filter Control Logic (continued..)
D
Hitreg_read
Read the masked
output
Wait
Wait for the hit
counting formatting
and processing.
G
Yes
Yes
fifo_empty
and
end of event
fifo_empty
and not
end of event
E
F
Is done = 1
Yes
No
Wait in this state
fifo not empty
A
F
Data_wait
Yes
Is fifo_empty
No
A
G
Init
Hit format Logic
Hitreg_valid
Wait for
hitreg_valid
signal.
1.Latch the hitreg.
2. Latch the grouped
signals
Point_select
Select the starting
point to read the hit
register
Ready
Yes
Are
hits_present
Read the hits from
the starting point
D
No
Set the done bit
Read_hits
A
select the bit from
the register the
pointed out by the
counter
Read_bit
Yes
Is bit high
No
Next_hit
Write_hit
B
C
Hit format Logic (continued..)
B
Write_hit
Format the data into
32 bit word
Output_hit
Write the word to L3
buffer and output
FIFO
C
Next_hit
Is counter <
= total count
Yes
No
NOTE: Total count
here is the number of
roads / comparators
loaded. This the
upper limit for the hit
search
Centroid done.
Reset Counter
Increment the
counter.
D
Yes
Trailer
Write the trailer to
L3 buffer and the
output FIFO.
A
Is it end of
event
No
Go to Init and wait
for the hit register
for the next
centroid.
A
Approach 1
The synthesis tool was allowed to fit the design in
minimum number of FPLDs
Number of devices
5
Strip_reader_hitfilter_l3_schematic
EPF10K200EGC599-1
Strip_reader_hitfilter_l3_schematic-1
EPF10K200EGC599-1
Strip_reader_hitfilter_l3_schematic -2
EPF10K30ETC144-1
Strip_reader_hitfilter_l3_schematic-3
EPF10K30EQC208-1
Strip_reader_hitfilter_l3_schematic-4
EPF10K50EQC208-1
The synthesis tool mapped the design in five FPLDs such
that the Embedded Array Blocks (EABs) were uniformly
distributed but the major portion of the memory was set
in the larger FPLDs. The FPLDs holding the memory had
very small percentage of logic cells occupied.
Approach 2
The Hit Filter and L3 buffers are forced in one FPLD
each and the synthesis tool
is allowed to fit Strip Reader and Centroid Finder
Number of devices
3
Hitfilter_schematic
EPF10K100EBC356-1
L3_schematic
EPF10K200EGC599-1
Strip_reader_hitfilter_l3- 1
EPF10K200SFC484-1
The synthesis tool tries to accommodate some of the excess
logic, specially the memory of strip_reader_chip into the
FPLD assigned to L3 buffer and very small fraction of it into
FPLD assigned to Hit Filter and thus overall design fits into
three FPLDs.
Approach 3
The Hit Filter and L3 buffers are forced to fit in one
FPLD each and the Strip Reader with Centroid
Finder is forced to fit in two FPLDs
Number of devices
4
Strip_reader_chip – 1
EPF10K200EGC599-1
Strip_reader_chip -2
EPF10K130EFC484-1
Hitfilter_schematic
EPF10K100EBC356-1
L3_schematic
EPF10K130EFC484-1
The strip reader needed two FPLDs because of the need
of EABs for the memory blocks. Each memory block
regardless of the memory requirement has minimum of
two EABs,this is due to the word length more than 8 bits.
Approach 4 - The Hit Filter, L3 buffers and the Strip
Reader with Centroid Finder are forced to fit in one
FPLD each
Number of devices
3
Hitfilter_schematic
EPF10K200SBC356-1
L3_schematic
EPF10K200EGC599-1
Strip_reader_schematic
EPF10K200SFC484-1
The strip reader design now fits into one chip , because
downloaded parameters do not use EABs