ME 445 – H10
Name _________________________
Design a test circuit to check all four gates in a 7400 chip against a known good chip. One
portion of the test circuit should generate a sequence of all possible inputs, while the second
portion should combine the output of all NAND gates under test with the known good signal.
The output of the overall test circuit should illuminate one LED if any fault is detected. Assume
that a 1KHz TTL clock signal is available to drive the test circuit as shown below.
a) Provide a schematic using MultiSim, ExpressSCH or EagleCAD. Be certain to provide pin
numbers, supply voltage connections and GND connections for all components in your
schematic.
b) Attach PERTINENT pages of data sheets for any chips used. Do not use surface mount
chips.
TTL
CLK IN
7400 under test
in ZIF socket
1/4 known
good 7400