ECE 340 Lecture 33
MOS capacitor Threshold Voltage
• Inversion: at V > VT (for NMOS), many
electrons drawn to surface, which is now
“inverted” vs. the p-doped substrate.
Draw charge distribution:
• Draw energy bands at inversion:
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
1
Note:
 Mobile charge anywhere is given
by difference between EC or EV
and Fermi level as, e.g. n =
NCexp(EC – EF)
 If EF is close to EC then lots of
__________________
 If EF is close to EV then lots of
__________________
qVi
• At high gate V (> VT) which
band is closer to EF?
• The condition for this onset is
ϕS = 2ϕF (see plot)
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
S  2F  2
W  WT 
kT  N A 

ln 
q  ni 
2 Si (2 F )
qN A
2
• At inversion (on p-type sub.) the mobile surface charges are
______________, such that numerically nsurf. = NA,sub.
• Now we can calculate the threshold voltage, VT:
 For NMOS (electron inversion on p-type substrate):
2qN A siS
VG  VFB  S  Vi  VFB  S 
Ci
2qN A Si (2F )
VT  VFB  2F 
Ci
kT
F 
ln( N A / ni )  0
q
 For PMOS (hole inversion on n-type substrate):
VT  VFB  2 F 
2qN D Si 2 F
Ci
kT
 F   ln( N D / ni )  0
q
 Net surface charge in inversion layer?
© 2012 Eric Pop, UIUC
Qinv  Ci (VG  VT )
ECE 340: Semiconductor Electronics
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• This is a good place to recap MOS capacitor behavior:
V < VFB
V = VFB
VFB < V < VT
VT < V
• Since this is a capacitor, what
does the C-V measurement look like?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
4
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
5
ECE 340 Lecture 34
MOS Capacitance-Voltage (C-V) curve
• MOS capacitance measurement:
iac
GATE
vac
Si
C-V Meter
iac  C
C
MOS Capacitor
dvac
dt
dQGATE
dQs

dVG
dVG
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
6
• Why is there a difference in inversion capacitance at:
 Low-frequency (<10 kHz)
 High-frequency (~1 MHz)
• Answer:
gate
gate
Accumulation:
Depletion:
CCox
i
Cox
C
i
+ + + + + +
Cdep
p-type Si
p-type Si
Inversion:
Case 1
Case 2
gate
gate
C
Coxi
N+
W
- - - - - -
CC
oxi
DC
- - - - - Cdep,min
-
DC and AC WT
© 2012 Eric Pop, UIUC
p-type Si
ECE 340: Semiconductor Electronics
AC
WT
p-type Si
7
• Inversion case I: inversionlayer (minority carriers!) can
be supplied quickly to
respond to changes in VG
DQ
M
O
Time required to build inversion-layer
charge = 2NAto/ni , where
to = minority-carrier lifetime at surface
S
WT
DQ
dQinv
C
 CCoxi
dVG
• How do we supply them?
1) Optical generation (turn lights on)
2) Providing a nearby source of
minority carriers (like in a
MOSFET)
• Inversion case II: inversionlayer cannot be supplied
quickly enough to respond to
changes in VG
© 2012 Eric Pop, UIUC
C
Coxi
DQ
M
O
S
WT
DQ
1
1
1


C CCoxi Cdep

C
Coxi Cdep
ECE 340: Semiconductor Electronics
1 WT

CCoxi  Si
1
2(2F )
1



CCoxi
qN A Si C min
8
• Ex: plot and label the C-V curve of a PMOS capacitor with
P+ gate, substrate doping ND=5x1017 cm-3 and SiO2 d=2 nm
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
9
• MOS capacitor non-idealities… in reality, neither the SiO2
nor the Si/SiO2 interface are perfect:
 Mobile ions (Na+ used to be a major headache)
 Dangling bonds at Si/SiO2 interface
 Charge traps within SiO2
• We can group these non-idealities together as an equivalent
sheet of charge Qi (>0) at the Si/SiO2 interface
• + charge at the interface pulls down the E-bands there and
changes the field across the SiO2
• This shifts the flat-band voltage:
© 2012 Eric Pop, UIUC
VFB   MS 
ECE 340: Semiconductor Electronics
Qi
Ci
10
• Odd shifts in C-V characteristics were once a mystery:
• Source of problem: Mobile ionic charge (e.g. Na+, K+) moving
to/away from the interface, ΔVFB = Qi / Ci
• Solution: cleaner environment, water, chemical supply.
• With simple C-V measurements we can learn (and “debug”) a great
deal about the properties and quality of MOS capacitors:
 Obtain oxide thickness (d) from  C accumulation
 Obtain substrate doping (NA) from  Cmin at VT (high-freq)
 Interface charge (Qi) and VFB from  C-V across various dox thicknesses
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
11
• MOS capacitor wrap-up:
• Experimental
measurement of fast
interface states (traps):
Ci
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
12
• A little more on the real measured C-V curve:
C
C
Cox
Basic LF C-V
i
with gate-depletion
with gate-depletion and
charge-layer thickness
data
VG
• Effective oxide capacitance affected by:
 Poly-silicon gate depletion (no problem with metal gate)
W poly Winv
 Finite thickness of inversion layer
d ox,eff  d 

• Both of which are somewhat functions of voltage.
3
3
• Last but not least:
 Why HfO2 instead of SiO2?
 Why metal gate instead of highly-doped poly-Si gate?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
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