Issues Driving Wafer-Level Technologies
Dr. Thomas Di Stefano
Decision Track
April 5, 2001
Decision Track
Stanford Seminar Series
Wafer Level Packaging: A New Paradigm
VOLUME
Thru Hole
•DIP
•Pin Grid
1960
Surface Mount
•QFP
•TSOP
•SOJ
•BGA
1980
Chip Scale
•CSP
•Wafer Level
•Stacked Die
•SiP
2000
YEAR
Decision Track
Stanford Seminar Series
IC Packaging Progression:
Surface Mount
Through Hole
CSP / WLP
TSOP
CSP/WLP
 25 mil pitch
 Area array 0.8 mm to 0.5 mm
 Limited by perimeter leads
 Limited by substrate wiring
DIP
 100 mil pitch
 Limited by through hole spacing
Decision Track
Stanford Seminar Series
Initial Driver: Miniaturization
- Personal Electronics • Cell Phones
• PDAs
• Camcorders
• Mobile Computers
• Card PCs
• Memory Cards
• Personal Communicators
Decision Track
Stanford Seminar Series
Wafer Level Packaging and Interconnect...
Enabled by the Chip Size Package
• The Wafer Level Paradigm is driven by imperatives …
–
Packaging Cost
–
Simplified Logistics
–
IC Functionality
–
Performance
• Production is Emerging Rapidly
–
Beginning in Small Devices (< 3mm)
–
Adapts Wafer Processing Infrastructure
–
Extending to Larger Die Sizes
Decision Track
Stanford Seminar Series
•
Dallas Semiconductor Wafer Level Package
Decision Track
Stanford Seminar Series
National Semiconductor MicroSMD
Decision Track
Stanford Seminar Series
Wafer Level Packaging is Paced by Infrastructure
•
Package Reliability
–
Thermal Mismatch Causes Solder Fatigue Cracking
•
High Density PWB Substrates
•
Burn-in and Test
•
–
–
Wafer level burn-in
Functional test on the wafer
Standards
–
Proliferation of variations slows adoption
Decision Track
Stanford Seminar Series
10000
Flip-Chip
Underfill+
µProcessor
1000
ASICs
Pins (#)
DRAM
SRAM
Flash
100
Passives
Analog ICs
10
Power ICs
Discretes
1
1
Decision Track
10
100
Die Area (mm2)
1000
Stanford Seminar Series
Flip-Chip Wafer Level Package
•
•
•
Eutectic Solder Ball Flip-Chip
–
–
Small DNP allows adequate reliability
Adapts existing infrastructure for rapid growth
. . . But --- limited to small die sizes
Flexible Interconnect Extends to Larger Die Sizes
–
–
–
–
Metal columns
Solder columns
Stacked solder balls
Flexible solder balls
. . . All with minimum changes to existing wafer processing infrastructure
Wafer Level Package Provides:
–
–
–
–
Surface mountable package
Testability
Reliability
Standards
Decision Track
Stanford Seminar Series
Coffin-Manson Equation for Reliability
1.9
H
N = A F 1/3
DNP ( s - c ) T
exp(E/kT)
N = cycles to failure
F
= cycling frequency
DNP = distance from neutral point
s = CTE of the substrate
c = CTE of the chip
 T = temperature cycle
H = height of solder ball
 E = activation energy
Decision Track
Stanford Seminar Series
Fujitsu SuperCSP
Redistribution
Trace (Cu)
SiN
Al Pad
Polyimide Layer
Die
Encapsulant
Barrier Metal
Solder Ball
•
•
•
•
Metal Post (Cu)
Solder balls on copper posts
Redistribution wiring to posts
Encapsulant is molded onto wafer
Inflexible posts limit reliability
Decision Track
Stanford Seminar Series
APACK Solder Column Package
Improves Strain Relief on Solder Ball
Decision Track
Stanford Seminar Series
Flexible Contacts Will Extend Wafer Level (2002-2005)
10000
Flip-Chip
Underfill+
µProcessor
1000
ASICs
Pins (#)
DRAM
SRAM
Flash
100
Passives
Analog ICs
10
Power ICs
Discretes
1
1
Decision Track
10
100
Die Area (mm2)
1000
Stanford Seminar Series
Coffin-Manson Equation for Reliability
1.9
H
N = A F 1/3
DNP ( s - c ) T
exp(E/kT)
N = cycles to failure
F
= cycling frequency
DNP = distance from neutral point
s = CTE of the substrate
c = CTE of the chip
 T = temperature cycle
H = height of solder ball
 E = activation energy
Decision Track
Stanford Seminar Series
JIEP Projections for CTE
CTE (ppm/C)
20
Board
Board
Package
Package
15
10
5
0
1998
2005
2010
Year
Decision Track
Stanford Seminar Series
IBM HPCC Package
Silicon Die
90Pb/10Sn Alloy
C-4 Solder Ball
PTFE Dielectric
Direct Chip Attach
Solder Mask
D1
D2
D3
D4
D5
D6
Copper-Invar-Copper Core
Copper Circuit
Micro-vias
Eutectic Solder Ball
Decision Track
Stanford Seminar Series
Low CTE Substrates Further Extend Wafer Level (2005)
10000
Flip-Chip
µProcessor
1000
ASICs
Pins (#)
DRAM
SRAM
Flash
100
Passives
Analog ICs
10
Power ICs
Discretes
1
1
Decision Track
10
100
Die Area (mm2)
1000
Stanford Seminar Series
CSPWLP Paced by High Density Substrate
$30B
$25B
$20B
INFORMATON
APPLIANCES
$15B
$10B
SiP
µPROCESSOR
ASICs
WLP
WIRELESS
DRAM
DSP
FLASH, SRAM
Stacked Die
$ 5B
CSP
1995
Decision Track
Requires HDI
2000
2005
2010
Stanford Seminar Series
World Micro-via Hole PCB Production ($million)
Region
1996
1997
1998
1999
2000*
2001*
--------------------------------------------------------------------------------------------------------Japan
320
600
1,055
1,800
2,700
4,000
Europe
10
15
40
260
400
600
N. America
25
35
40
150
300
500
Asia Pacific
2
10
85
210
400
600
357
660
1,220
2,420
3,800
5,700
115
240
450
900
1,500
2,500
Total
Total Number
of Lasers
*forecast - Japan’s $4 Billion 2001 forecast consists of $2.5 Billion IC package
(BGA/LGA) substrates and $1.5 Billion in HDI circuit boards.
Data Source: N.T. Information Ltd. (Dr. Hayao Nakahara)
Decision Track
Stanford Seminar Series
I/O Explosion: Power & Ground Distribution
•
Distribute the Power and Ground on Chip
– Better electrical characteristics
– Shorter distance to the shielding planes
– Dramatically reduces I/O connections for power/ground
• 80+% of I/O on advanced processors is Power/Ground.
•
Power and Ground Layers on the Wafer
– Efficiency of production
• Avoid paying for large number of power/ground pins.
– Makes the chip easier to test -
Decision Track
fewer power/ground contacts
Stanford Seminar Series
Decision Track
Stanford Seminar Series
Interconnect: The I/O Explosion
Total Pin Count
3000
I/O 2000
Power/Ground
1000
Signal
500
1980
1990
2000
Time Line
Decision Track
Stanford Seminar Series
Power & Ground: Redistribution on the Chip
Power/Ground Distribution
•
•
Flip Chip
•
•
Pin count Explosion
70-80 % is Power & Ground
Decision Track
Fabricated on separate layers
Assembled to the wafer
Composite Chip
•
•
Power/ground distributed on
the chip to reduce I/O count
High performance Power
and ground distribution
Stanford Seminar Series
Intra-Chip Communication: RC Delays
•
RC Loading Limits Signal Propagation across Chip
•
Reduce RC Delays
– R scales inversely with [lithographic dimension]2
– C remains ~ constant
– Problem gets worse with scaling to smaller dimension
– Lower Dielectric Constant of Insulator
– Copper Conductors to Reduce Resistance
– Wafer Level Packaging for High Performance Interconnect
• Impedance Controlled Nets
• Low RC
Decision Track
Stanford Seminar Series
IC Performance: RC Delays are an Increasing Problem
RC Propagation Limit
RC Delays scale as the inverse square of the scaling law
• Max propagation length is 3 mm at 0.25 µm lithography
• Propagation length shrinks as geometries are scaled
Decision Track
Stanford Seminar Series
IC Performance: Interconnect Dominates Delays*
Package Delays
100 ps
10 ps
MOSFET Delays
1 ps
1.0 µm
Performance
•
•
•
Clock Speed
Wire Length
Pin Count
Decision Track
0.1 µm
1.0 µm
0.1 µm
33 MHz
100 m
150
2-3.5 MHz
5000 m
to 3000
*SOURCE SEMI/SEMATECH
Interconnect Focus Center
Stanford Seminar Series
Wafer Level Packaging: Added Interconnect Capability
• Wafer level production for processors allows
– Power/ground distribution on chip
– Routing critical nets in low resistance copper lines in the package
• Approaches
– Multi-layer flex interposer
–
Silicon interposer
• Pacing items
–
–
–
High density wiring capability on chip for (4-6 layers of wiring)
High density PWB substrates (0.5 mm via pitch or better)
Capability to burn-in and test chips in a wafer format
Decision Track
Stanford Seminar Series
Wafer Level
WAVE
Package
Source: Tessera
Decision Track
Stanford Seminar Series
Circuitized Polyimide
Copper Flex-Link
Silicon Wafer
X-ray image
of Flex-Link
Decision Track
Source: Tessera
Stanford Seminar Series
Multi-Chip Packages: TruSi Stacked Wafers
Passivation
Insulation
Thru Via
Decision Track
Stanford Seminar Series
Wafer Test & Burn-in: Driving Factors
•
•
•
•
Necessary for Wafer Level Packaging
–
–
Must burn-in Before Final Test on the Wafer.
Applies to flip chip as well as full wafer level packaging
Faster Time to Market
–
Diced Wafer is the final, fully tested product.
Faster Cycles of Learning
–
The wafer fab has full information on test before wafer leaves fab
Reduction of Test Costs
–
–
“Test Once”
Wafer test is both probe and final test
Decision Track
Stanford Seminar Series
Wafer
Probe
Wafer
Dicing
Package
Test
Burn-in
Final Test
Package
Test
Burn-in
Final Test
Package
Test
Burn-in
Final Test
Conventional Packaging
Wafer Run-in
Wafer
Packaging
Wafer
Burn-in
Final
Test
Wafer
Dicing
Wafer Level Packaging
•Product Cost Reduction
•Cycle Time Reduction
•Capital Cost Reduction
Decision Track
Stanford Seminar Series
Process Flow:
Wafer Level Packaging
vs.
Conventional Packaging
* From Motorola
Decision Track
Stanford Seminar Series
Wafer Test: Challenges Ahead
•
•
•
•
Probe Density
–
–
60 µm pad spacing
Area array pads
Functional Wafer Test
–
Test at Speed
Parallel Testing
–
–
BIST ?
Wafer run-in (test during burn-in)
Hot chuck testing
–
o
Wafer test at temperatures to 150 C
Decision Track
Stanford Seminar Series
Wafer Burn-in: Technical Challenges
•
Contact Alignment
•
Electrical Interconnect
•
•
–
Wire 10,000 - 20,000 contacts to device drivers
Large Number of Electrical Contacts
–
–
Force of 250 lb for 20,000 contacts
500,000 contacts for a flip chip micro-Processor
Extreme Environment
Decision Track
Stanford Seminar Series
Wafer Burn-in: Technical Challenges
10,000 - 500,000 contacts
From 25C to 150C
Decision Track
Cu
450 µm (18 mils)
Si
75 µm (3 mils)
Stanford Seminar Series
The Drive Toward Wafer Level Packaging
• Chip Scale Packages are Replacing Conventional Packages
Initial applications are rapidly growing personal electronics
CSPs move toward Wafer Level Production
• Growth of Chip Scale Electronics will be Rapid
CSP/WLP will grow to a $40B market in 10 years time
Rapidly growing approaches use existing infrastructure
• Wafer Level Packaging will Extend CSP for Decades into the Future
Packaging and wafer fabrication will merge
Additional function is integrated into the package
• Wafer Level Technologies will Provide Added Functionality
Intra-Chip Interconnect
Power/Ground Distribution
Stacked Wafers
Decision Track
Stanford Seminar Series