Problem 4
The small-signal equivalent circuit is shown in Figure 1. Note that the other capacitors
have been neglected as suggested by the problem. Also, gmb has been omitted because
the expressions should not be in terms of that parameter either.
V2 ( j )
Z 2 ( j )
Z1 ( j )
1
j    C GS1
1
j   CL
 g m1  V1 ( j )
ro1
V1 ( j )
Z i ( j )
Figure 1. Phasor domain circuit for Zi
1
. In
j    CGS1
order to determine Z 2 ( j ) , the circuit depicted in Figure 2 may be used.
As indicated in Figure 1, Z i ( j )  Z 1 ( j ) // Z 2 ( j ), where Z1 ( j ) 
Node 
Z 2 ( j )
V2 ( j )
1
j   CL
 g m1  Vt ( j )
ro1
Vt ( j )
V1 ( j )  Vt ( j )
I t ( j )
Figure 1. Phasor domain circuit for Z2
Performing KCL at node β yields,
V ( j )  V2 ( j )
I t ( j )  g m1Vt ( j )  t
ro1
(1)
But,
V 2 ( j )  I t ( j  ) 
1
j   CL
Substituting (2) into (1) then yields,
V ( j )
I ( j )
I t ( j )  g m1Vt ( j )  t
 t
ro1
j  ro1C L
(2)
(3)
Manipulating (3) finally results in the following for Z 2 ( j ) :
1  j  ro1C L 
V ( j )
Z 2 ( j )  t

(4)
I t ( j )


g m1 ro1C L
j  CGS1  1 
 j  ro1C L 
CGS1


Hence, the zero and pole magnitudes are as follows:
1
 zero 
ro1C L
(5)
 pole,1  0
(6)
1
 pole, 2 
g m1 ro1C L
C GS1
ro1C L
(7)
Note: Technically, the zeros and poles above are negative. In other words, they lie
in the left-half portion of the s-plane.