EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Physical Limitations of Logic Gates – Week 10a
In a computer we’ll have circuits of logic
gates to perform specific functions
• Computer Datapath: Boolean algebraic
functions using binary variables
• Symbolic representation of functions
using logic gates
• Example:
A
B
C
D
•Every node has capacitance and
interconnects have resistance. It takes
time to charge these capacitances.
•Thus, output of all circuits, including
logic gates is delayed from input.
•For example we will define the unit
gate delay
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
UNIT GATE DELAY D
Time delay D occurs between input and output: “computation” is not
instantaneous
Value of input at t = 0+ determines value of output at later time t = D
A
Logic State
C
B
Input (A and B tied together)
1
0
t
0
1
0
Output
0
D
t
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
UNIT GATE DELAY D in ASYNCHRONOUS LOGIC
Time delay D is measured from the last input change
A
Logic State
C
B
Input A
1
Input B
0
t
0
1
0
Output
0
D
t
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Synchronous and Asynchronous Logic
Time delay occurs between input and output in real logic circuits.
Therefore the time at which output appears is difficult to predict… it
depends for example on how many gates you go through.
CK
A
B
C
We will often not distinguish
asynchronous vs synchronous
logic.
To make logic operations as fast as possible, we need predictability of
signal availability. That is we want to know exactly when “C” is correctly
computed from A and B. This requirement argues for synchronous logic, in
which a clock signal CK actually initiates the computation of C.
Thus in the modified gate, C will be valid precisely one gate delay (D) after
the clock input CK, goes high (A and B are evaluated precisely when CK goes
high, what they do before or after this is irrelevant; CK must go low, then high
again before the NAND gate again looks at A and B).
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
EFFECT OF GATE DELAY
Cascade of Logic Gates
A
B
D
C
Inputs have different delays, but we
ascribe a single worst-case delay
D to every gate
How many “gate delays for shortest path?
ANSWER : 2
How many gate delays for longest path?
ANSWER : 3
Which path is the important one?
ANSWER : LONGEST
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
TIMING DIAGRAMS
Show transitions of variables vs time
A
B
Logic state
D
A, B, C
C
0 B
Note B becomes valid one gate
delay after B switches
t
D
t
D 2 D
t
D
t
D 2D3D
t
__
__
Note that ( B C )becomes valid two
gate delays after B&C switch, because
the invert function takes one delay and
the NAND function a second.
( B C )
( A  B)
D
No change at t = 3 D
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
W. G. Oldham
WHAT IS THE ORIGIN OF GATE DELAY?
Logic gates are electronic circuits that process electrical signals
Most common signal for logic variable: voltage
Specific voltage ranges correspond to “0” or “1”
Volts
3
2
Range  “1”
Thus delay in voltage rise or fall
(because of delay in charging
internal capacitances) will translate
to a delay in signal timing
“Gray area” . . . not allowed
1
Range  “0”
0
Note that the specific voltage range for 0 or 1 depends on “logic
family,” and in general decreases with logic generations
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
VOLTAGE WAVEFORMS (TIME FUNCTIONS)
Inverter input is vIN(t), output is vOUT(t)
inside a large system
v IN ( t )
v OUT ( t )
Vin(t)
t
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
GATE DELAY (PROPAGATION DELAY)
Define  as the delay required for the output voltage to reach 50% of its final
value. In this example we will use 3V logic, so halfway point is 1.5V.
Inverters are designed so that the gate delay is symmetrical (rise and fall)
Vin(t)
1.5
t
Vout(t)
Approximation
1.5
D
D
D
t
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED
Computer architects would like each system clock cycle to have
between 20 and 50 gate delays … use 35 for calculations
Implication: if clock frequency = 500 MHz
clock period = (5108 s1)1
Period = 2  10 9s = 2 ns (nanoseconds)
Gate delay must be D = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds)
How fast is this? Speed of light: c = 3  108 m/s
Distance traveled in 57 ps is:
C X D = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cm
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
WHAT DETERMINES GATE DELAY?
v IN ( t )
v OUT ( t )
The delay is mostly simply the charging of the capacitors at internal nodes.
We already know how to analyze this.
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Example
The gate delay is simply the charging of the capacitors at
internal nodes.
Oversimplified example using “ideal inverter, II” v OUT ( t )
and 5V logic swing
5
v OUT ( t )
v IN ( t )
v IN ( t )
RC =
0.1ns
R
Vx
MODEL
II
v OUT ( t )
2.5
v IN ( t )
C
5
vIN
2.5
RC = 0.1ns so 0.069ns after vIN
switches by 5V, Vx moves 2.5V
vOUT
Vx
D = 0.069ns
t
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Simple model for logic delays
Model actual logic gate as an ideal logic gate fed by an RC
network which represents the dominant R and C in the gate.
v IN ( t )
R
C
VX
Ideal
Logic
gate
v OUT ( t )
Actual Logic Gate
vIN (t)
Ideal
Logic
gate
etc.
v OUT ( t )
vIN
vOUT
VX
t
D = 0. 69 RC
t
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
W. G. Oldham
How can we build inverters, NAND gates, etc. ?
We need some sort of controlled switch: that is a device in
which a switch opens or closes in response to an input
voltage (a control voltage). If we have a controlled switch it is
an easy matter to build inverters, NAND gates, etc.
For example an electromagnetic relay has a coil producing a
magnetic field causing some contacts to “snap shut” when a
voltage is applied to the coil.
Lets imagine a simple controlled switch, but include in it some
resistance (all real devices have non-zero resistance).
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Controlled Switch Model
I
R
Output I vs. V
I
Input
high
+
Output
Input
+
-
Input
low
-
The basic idea: We need a switch which is controlled by an input
voltage. For example: Input V = 0 means the switch is open,
whereas an input voltage of 2V means that the switch is closed
(We will call this a “Type N controlled switch”)
V
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
Controlled Switch Model
G
Input
+
- -
RN +
Output
+-
Type N controlled switch”
means switch is closed if
input is high. (VG > VS)
RP +
Output
+-
Type P controlled switch”
means switch is closed if
input is low. (VG < VS)
S
G
Input
+
- -
S
Now lets combine these switches to make an inverter.
W. G. Oldham
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Controlled Switch Model of Inverter
VDD = 2V
RP
VIN
+
RN
Input
+
-
SP
SP is closed if
VIN < VDD
VOUT
+
+SN is closed if Output
VIN > VSS
SN
-
VSS = 0V
So if VIN is 2V then SN is closed and SP is open. Hence VOUT is zero.
But if VIN is 0V then SP is closed and SN is open. Hence VOUT is 2V.
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Controlled Switch Model of Inverter
VDD = 2V
VIN =2V
+
RN
- SS = 0V
V
VOUT
-
IF VIN is 2V then SN is
closed and SP is open.
Hence VOUT is zero (but
driven through resistance
RN).
VDD = 2V
VIN =0V
RP
+
VOUT
- SS = 0V
V
-
But if VIN is 0V then SP
is closed and SN is
open. Hence VOUT is
2V (but driven through
resistance RP).
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
Controlled Switch Model of Inverter
VDD = 2V
VIN =2V
+
RN
- SS = 0V
V
VOUT
-
IF there is a capacitance at
the output node (there
always is) then VOUT
responds to a change in VIN
with our usual exponential
form.
VOUT
VDD = 2V
VIN =0V
VIN jumps from
2V to 0V
RP
+
VOUT
- SS = 0V
V
-
VIN jumps from
0V to 2V
t
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
W. G. Oldham
Controlled Switch Model of Inverter
We will expand on this model in coming weeks.
The controlled switches will of course be MOS transistors.
The resistance will be the effective output resistance of the MOS
devices.
The capacitance will be the input capacitance of the MOS devices.
But now lets briefly review the energy used in charging and
discharging capacitances so we can start to estimate chip power.
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
ENERGY AND POWER IN CHARGING/DISCHARGING
CAPACITORS – A REVIEW
CASE 1R
t=0
Capacitor initially uncharged
Charging
i

(Q=CVDD at end)
V
C
DD

RD
Switch moves @ t=0
Power out of "battery"
P  i( t ) VDD
Power into C
PC  i( t )VC ( t )
Power into R
PR  i( t )2 R
Energy out of "battery"
Energy into C
Energy into R (heat)

E   iV DDdt  QVDD
0
 CVDD 2

EC   iVC dt
0
1
 CVDD 2
2
This must be difference
of E and EC, i.e. 1 CVDD2
2
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
ENERGY AND POWER IN CHARGING
R
t=0

VDD

C
RD
Capacitor initially uncharged
(Q=CVDD at end)
Switch moves @ t=0
Energy out of "battery"
 CVDD
2
Energy into C
1
 CVDD 2
2
Energy into R (heat)
1
CVDD2
2
In charging a capacitor from a fixed voltage source VDD half the
energy from the source is delivered to the capacitor, and half is
lost to the charging resistance, independent of the value of R.
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
ENERGY AND POWER IN CHARGING/DISCHARGING
CAPACITORS
CASE 2R
t=0
Capacitor initially charged
discharging

(Q=CVDD) and discharges.
V
C
DD

RD
i
Switch moves @ t=0
=0
Power out of C
PC  i( t )VC ( t )
Power into RD
PR  i( t )2 R
Energy out of battery
Energy out of C
Energy into RD (heat)
=0

EC   iVC dt
0
Power out of battery
Power in/out of R
=0
1
 CVDD 2
2
This must be energy
initially in C, i.e.
1
CVDD 2
2
EECS 42
Spring 2001 Lecture 19
W. G. Oldham
Copyright Regents of University of California
ENERGY IN DISCHARGING CAPACITORS
R
t=0

VDD

C
RD
Capacitor initially charged
(Q=CVDD) and discharges.
Switch moves @ t=0
Energy out of C
1
 CVDD 2
2
Energy into RD (heat)
1
CVDD 2
2
When a capacitor is discharged into a resistor the energy
originally stored in the capacitor (1/2 CVDD2) is dissipated as heat
in the resistor
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
W. G. Oldham
POWER DISSIPATION in DIGITAL CIRCUITS
Each node transition (i.e. charging or discharging) results in a loss of
(1/2)(C)(VDD)2 How many transitions occur per second? Well if the
node is pulsed up then down at a frequency f (like a clock frequency)
then we have 2f dissipation events.
A system of N nodes being pulsed at a frequency f to a signal voltage
VDD will dissipate energy equal to (N) (2f )(½CVDD)2 each second
Therefore the average power dissipation is (N) (f )(CVDD)2
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
LOGIC POWER DISSIPATION
Power = (Number of gates) x (Energy per cycle) x (frequency)
P = (N) (CVDD)2 (f )
N = 107; VDD = 2 V; node capacitance = 10 fF; f = 109 s-1 (1GHz)
P = 400 W! -- a toaster!
Pretty high but realistic
What to do? (N increases, f increases, hmm)
1) Lower VDD
2) Turn off the clock to the inactive nodes
Clever architecture and design!
Lets define a as the fraction of nodes that are clocked
(active). Then we have a new formula for power.
W. G. Oldham
EECS 42
Spring 2001 Lecture 19
Copyright Regents of University of California
W. G. Oldham
LOGIC POWER DISSIPATION with power mitigation
Power = (Energy per transition) x (Number of gates) x (frequency) x
fraction of gates that are active (a).
P = a N f CVDD2
In the last 5 years VDD has been lowered from 5V to about 1.5V. It
cannot go very much lower. But with clever design, we can
make a as low as 1 or 10%. That is we do not clock those parts
of the chip where there is no computation being made at the
moment.
Thus the 400W example becomes 4 to 40W, a manageable range
(4W with heat sink, 40W with heat sink plus fan on the chip).