EE 42 Homework and Reading No. 10

EE 42 Homework and Reading No. 10
Homework assigned Tuesday 26 April 2005; due at 5:30 pm Tuesday 3 May 2005 in the
box labeled EE 42 in Room 240 Cory Hall. Note: your graded homeworks will be
returned in your discussion section; if you don’t pick them up, they will be stored by
Chris Colbert in 253 Cory.
Reading: Skim Rabaey et al., Secs. 2.1 and 2.2 – The Manufacturing Process.
See also notes handed out in lecture Thursday 21 April and Tuesday 26
April (available either from your GSI or from Chris Colbert in 253 Cory).
1. (18 points) As noted before in class, the NAND gate is the favored basic logic
gate for digital circuits because of its speed. We also noted that it is desirable to
reduce the number of PMOS and NMOS transistors in order to minimize the size,
cost and delay of digital circuits. And you’ve seen what’s in a CMOS NAND
gate – just transistors, whose number depends on the number of inputs to the gate.
Suppose you made each of the following gates using NAND gates only (you’ll
need inverters, which you can also make with NAND gates). How many FETs in
all would it require to make each of the following gates? (Note: you may find
useful the handout on logic gates that shows the DeMorgan equivalent gates.)
Warmup: A two-input NAND gate.
An inverter made with single NAND gates two different ways.
A two-input AND gate made entirely with NAND gates.
A three-input AND gate made entirely with NAND gates.
A two-input OR gate made entirely with NAND gates.
A two-input NOR gate made entirely with NAND gates.
2. (20 points) Exclusive OR gate (XOR). This gate, which you probably used in
simulating the full adder circuit, can be made by hooking up other, more
fundamental gates. For example, you can make a two-input XOR gate with two
two-input NOR gates and one two-input AND gate.
a. Find a circuit that has the same truth table as the XOR gate. (Just
experiment a bit.) You may find it helpful to include in your truth table
the values at the outputs of all three gates.)
b. Calculate the number of transistors required in the gate made with AND
and NOR circuits (use the results of Problem 1).
c. Now try simplifying your equivalent XOR gate by (i) drawing the circuit
using NANDs only and (ii) simplifying where possible. Draw the
resulting circuit.
d. Calculate the number of transistors required in the circuit you obtained in
part (c).
3. (10 points) Answer the questions at the end of the four-page handout titled
“Finding the Propagation Delay”, which are reproduced here:
a. Given the propagation delay obtained on page 4 (26.5 ps) how high could
your clock frequency be if the clock periods in a computer should be no
shorter than about 35 times a gate delay?
b. If somehow an extra capacitance of 0.05 pF also loaded the input of the
driven inverter, what would the propagation delay become? (For reference,
note that the capacitance of a one-foot section of the black oscilloscope cables
used in the lab is about 30 pF.)
4. (15 points) Calculate the propagation delays for a high-to-low and a low-to-high
transition using the method given in the Week 12a lecture notes using the
effective load capacitance figures on p. 4 and the FET-channel resistance figures
on p. 118 of the Reader (p.106 of Rabaey’s book). Note that the figures shown in
Rabaey’s table are listed for various voltages VDD for an FET gate whose width
and length are equal. Use the correct figures for the voltage and gate dimensions
assumed in the handout.