Matakuliah
Tahun
Versi
: H0344/Organisasi dan Arsitektur Komputer
: 2005
: 1/1
Pertemuan 17
CPU Architecture
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menjelaskan konsep dasar CPU
architecture
2
Outline Materi
•
•
•
•
Processor Organization
Register Organization
Instruction Cycle
Instruction Pipelining
3
Processor Organization
CPU must do:
• Fetch instruction
• Interpret instruction
• Fetch data
• Process data
• Write data
4
Processor Organization
The CPU with the system bus
Registers
ALU
Control unit
Control
bus
Data
bus
Address
bus
System bus
5
Processor Organization
Internal structure of the CPU
Arithmetic and logic unit
Status flags
Shifter
Complementer
Arithmetic and
boolean logic
Internal CPU bus
Registers
Control
unit
Control path
6
Register Organization
The registers in the CPU perform two rules:
• User visible registers
• Control and status registers
User visible registers
We can characterize user visible registers in the following
categories:
• General purpose
• Data
• Address
• Condition codes
7
Register Organization
Control and status registers
Four registers are essential to instruction execution:
• Program counter
• Instruction register
• Memory address register
• Memory buffer register
8
Register Organization
Control and status registers
All CPU designs include a register or set registers, often know
as the program status word (PSW), that contain status
information.
These status include the following:
• Sign
• Zero
• Carry
• Equal
• Overflow
• Interrupt enable/disable
• Supervisor
9
Instruction Cycle
Instruction Cycle
Fetch
Interrupt
Indirect
Execute
10
Instruction Cycle
Instruction Cycle State Diagram
Instruction
fetch
Operand
fetch
Operand
store
Multiple
operands
Instruction
address
calculation
Instruction
operation
decoding
Instruction complete,
fetch next instruction
Operand
address
calculation
Multiple
result
Data
operation
Operand
address
calculation
Return for string
or vector data
11
Instruction Cycle
Data Flow in Fetch Cycle
PC
MAR
Memory
Control unit
IR
MBR
Address
bus
Data
bus
Control
bus
12
Instruction Cycle
Data Flow in Indirect Cycle
MAR
Memory
Control unit
MBR
Address
bus
Data
bus
Control
bus
13
Instruction Cycle
Data Flow in Interrupt Cycle
MAR
PC
Memory
Control unit
MBR
Address
bus
Data
bus
Control
bus
14
Instruction Pipelining
The following decomposition of the instruction processing
• Fetch instruction (FI)
• Decode instruction (DI)
• Calculate operands (CO)
• Fetch Operands (FO)
• Execute instruction (EI)
• Write operand (WO)
15
Instruction Pipelining
Fetch instruction
Six stage CPU
instruction pipeline
Decode instruction
Calculate operands
Unconditional
branch?
Fetch operands
Execute instruction
Write operands
Update PC
Empty pipe
Unconditional
or interrupt?
16
FI
DI
CO
FO
EI
1
I1
2
I2
I1
3
I3
I2
I1
4
I4
I3
I2
I1
5
I5
I4
I3
I2
I1
6
I6
I5
I4
I3
I2
7
I7
I6
I5
I4
8
I8
I7
I6
9
I9
I8
I9
10
11
12
WO
FI
DI
CO
FO
EI
WO
1
I1
2
I2
I1
3
I3
I2
I1
4
I4
I3
I2
I1
5
I5
I4
I3
I2
I1
I1
6
I6
I5
I4
I3
I2
I1
I3
I2
7
I7
I6
I5
I4
I3
I2
I5
I4
I3
8
I15
I7
I6
I5
I4
9
I16
I8
I7
I6
I5
10
I9
I8
I7
I6
11
I9
I8
I7
12
I9
I8
13
I9
14
13
14
I3
I15
I16
I15
I16
I15
I16
I15
I16
I15
I16
17
(a) No branches
(b) With conditional branch
Instruction Pipelining
A variety of approaches have been taken for dealing with
conditional branches:
• Multiple streams
• Prefetch branch target
• Loop buffer
• Branch prediction
• Delayed branch
18
Instruction Pipelining
Various techniques can be used to predict whether a branch
will be taken. Among the more common are the following:
• Predict never taken
• Predict always taken
• Predict by opcode
• Taken/not taken switch
• Branch history table
19
Instruction Pipelining
Branch prediction flowchart
Yes
Read next conditional
branch instruction
Read next conditional
branch instruction
Predict taken
Predict not taken
No
Branch taken?
Branch taken?
No
Yes
Read next conditional
branch instruction
Read next conditional
branch instruction
Predict taken
Predict not taken
Yes
No
Branch taken?
No
Branch taken?
Yes
20
Instruction Pipelining
Branch prediction state diagram
Not taken
Taken
Predict
taken
Predict
taken
Taken
Taken
Not taken
Not taken
Predict
not taken
Predict
not taken
Not taken
Taken
21
Instruction Pipelining
Dealing with Branches
Branch
instruction
address
E
Target
address
State
IPFAR
Next
sequential
address
Branch miss
handling
Add new
entry
E
Branch miss
handling
Select
Next
sequential
address
Update
state
Redirect
Select
Memory
Memory
(a) Predict never taken strategy
(a) Branch history table strategy
22