inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #20 – Controlling a Single-Cycle CPU
2007-7-30
Scott Beamer
Instructor
Black Hat Conference Kicks Off in Vegas
CS61C L20 Single-Cycle CPU Control (1)
Beamer, Summer 2007 © UCB
Putting it All Together:A Single Cycle Datapath
RegDst
32
Equal
0
5
5
5
Rw Ra Rb
RegFile
busA
busB
32
16
Extender
imm16
MemtoReg
MemWr
Rs Rt
clk
clk
ALUctr
32
=
ALU
busW
PC
PC Ext
Adder
Mux
00
RegWr
Adder
4
Rt Rd Imm16
Rd Rt
1
Instruction<31:0>
<0:15>
nPC_sel
Rs
<11:15>
Adr
<16:20>
<21:25>
Inst
Memory
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
imm16
ExtOp
CS61C L20 Single-Cycle CPU Control (2)
ALUSrc
Beamer, Summer 2007 © UCB
Review: A Single Cycle Datapath
Instruction<31:0>
Rs Rt Rd Imm16
ALUctr
MemtoReg
Rd Rt
1
RegWr
0
5
Rs Rt
5
busB
32
16
Extender
clk
imm16
busA
ExtOp
CS61C L20 Single-Cycle CPU Control (3)
32
MemWr
=
ALU
RegFile
32
zero
5
Rw Ra Rb
busW
<0:15>
RegDst
<11:15>
clk
<16:20>
instr
fetch
unit
nPC_sel
<21:25>
• We have
everything
except control
signals
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
ALUSrc
Beamer, Summer 2007 © UCB
An Abstract View of the Implementation
Ideal
Instruction
Memory
PC
clk
32
Instruction
Rd Rs Rt
5 5
5
Rw Ra Rb
Register
File
clk
Control Signals Conditions
A
32
ALU
Next Address
Instruction
Address
Control
B
32
32
Data
Addr
Ideal
Data
Memory
Data
Out
Data
In clk
Datapath
CS61C L20 Single-Cycle CPU Control (4)
Beamer, Summer 2007 © UCB
Recap: Meaning of the Control Signals
“+4” 0  PC <– PC + 4
“br” 1  PC <– PC + 4 +
“n”=next
{SignExt(Im16) , 00 }
• Later in lecture: higher-level connection
between mux and branch condition
• nPC_sel:
Inst Address
00
0
PC
Mux
Adder
PC Ext
imm16
CS61C L20 Single-Cycle CPU Control (5)
nPC_sel
Adder
4
1
clk
Beamer, Summer 2007 © UCB
Recap: Meaning of the Control Signals
° MemWr: 1  write memory
• ExtOp: “zero”, “sign”
° MemtoReg: 0  ALU; 1  Mem
• ALUsrc: 0  regB;
1  immed
° RegDst: 0  “rt”; 1  “rd”
• ALUctr: “ADD”, “SUB”, “OR”° RegWr: 1  write register
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp
CS61C L20 Single-Cycle CPU Control (6)
Extender
clk
32
0
ALU
busW
MemtoReg
MemWr
32
0
32 WrEn Adr
1
32
Data In
ALUSrc clk
Data
Memory
1
Beamer, Summer 2007 © UCB
RTL: The Add Instruction
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
11
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
add rd, rs, rt
• MEM[PC]
Fetch the instruction
from memory
• R[rd] = R[rs] + R[rt] The actual operation
• PC = PC + 4
Calculate the next
instruction’s address
CS61C L20 Single-Cycle CPU Control (7)
Beamer, Summer 2007 © UCB
Instruction Fetch Unit at the Beginning of Add
• Fetch the instruction from Instruction
memory: Instruction = MEM[PC]
• same for
all instructions
Inst
Memory
nPC_sel
Inst Address
00
Adder
4
Instruction<31:0>
PC
Mux
Adder
PC Ext
clk
imm16
CS61C L20 Single-Cycle CPU Control (8)
Beamer, Summer 2007 © UCB
Instruction Fetch Unit at the End of Add
• PC = PC + 4
• This is the same for all instructions except:
Branch and Jump
Inst
Memory
nPC_sel=+4 Inst Address
00
Adder
4
PC
Mux
Adder
PC Ext
clk
imm16
CS61C L20 Single-Cycle CPU Control (9)
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Add
31
26
op
21
16
rs
11
rt
rd
6
shamt
funct
R[rd] = R[rs] + R[rt]
5
5
5
busA
Rw Ra Rb
RegFile
32
busB
32
imm16
16
Extender
clk
ExtOp=x
CS61C L20 Single-Cycle CPU Control (10)
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=0
MemWr=0
32
=
ALU
busW
0
32
1
32
<0:15>
Rs Rt
<11:15>
RegWr=1
<16:20>
0
<21:25>
Rd Rt
1
Instruction<31:0>
instr
fetch
unit
nPC_sel=+4
RegDst=1
clk
0
Data In
ALUSrc=0
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
Single Cycle Datapath during Or Immediate?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = R[rs] OR ZeroExt[Imm16]
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
CS61C L20 Single-Cycle CPU Control (11)
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
Single Cycle Datapath during Or Immediate?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = R[rs] OR ZeroExt[Imm16]
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=zero
CS61C L20 Single-Cycle CPU Control (12)
Rs Rt Rd Imm16
zero ALUctr=OR
MemtoReg=0
MemWr=0
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=1
<11:15>
0
<16:20>
Rd Rt
<21:25>
nPC_sel=+4
RegDst=0
clk
1
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=1
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Load?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = Data Memory {R[rs] + SignExt[imm16]}
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
CS61C L20 Single-Cycle CPU Control (13)
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Load
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = Data Memory {R[rs] + SignExt[imm16]}
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=sign
CS61C L20 Single-Cycle CPU Control (14)
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=1
MemWr=0
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=1
<11:15>
0
<16:20>
Rd Rt
<21:25>
nPC_sel=+4
RegDst=0
clk
1
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=1
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Store?
31
26
21
op
16
rs
0
rt
immediate
• Data Memory {R[rs] + SignExt[imm16]} = R[rt]
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
CS61C L20 Single-Cycle CPU Control (15)
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Store
31
26
21
op
16
rs
0
rt
immediate
• Data Memory {R[rs] + SignExt[imm16]} = R[rt]
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=sign
CS61C L20 Single-Cycle CPU Control (16)
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=x
MemWr=1
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=0
<11:15>
0
<16:20>
Rd Rt
<21:25>
nPC_sel=+4
RegDst=x
clk
1
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=1
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
Administrivia
• Assignments
• HW7 due 8/2
• Proj3 due 8/5
• Assignment Grading
• Grades should be coming in now (HW1,
HW2 done, expect HW3, HW4, Proj1
soon)
• Reader info posted on webpage
• Midterm Regrades due Wed 8/1
CS61C L20 Single-Cycle CPU Control (17)
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Jump
31
J-type
26 25
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Instruction<31:0>
Jump=
<0:25>
Data In32
ALUSrc =
0
32
Clk
WrEn Adr
32
Mux
32
<0:15>
1
<11:15>
16
Extender
imm16
Rs Rd Imm16 TA26
MemtoReg =
Zero MemWr =
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
<16:20>
5
Rt
ALUctr =
Rs Rt
5
5
Mux
32
Clk
Clk
1 Mux 0
RegWr =
busW
Rt
<21:25>
RegDst =
Rd
Instruction
Fetch Unit
nPC_sel=
1
Data
Memory
ExtOp =
CS61C L20 Single-Cycle CPU Control (18)
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Jump
31
J-type
26 25
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Instruction<31:0>
Jump=1
<0:25>
Data In32
ALUSrc = x
0
32
Clk
WrEn Adr
32
Mux
32
<0:15>
1
<11:15>
16
Extender
imm16
Rs Rd Imm16 TA26
MemtoReg = x
Zero MemWr = 0
ALU
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
<16:20>
5
Rt
ALUctr =x
Rs Rt
5
5
Mux
32
Clk
Clk
1 Mux 0
RegWr = 0
busW
Rt
<21:25>
RegDst = x
Rd
Instruction
Fetch Unit
nPC_sel=?
1
Data
Memory
ExtOp = x
CS61C L20 Single-Cycle CPU Control (19)
Beamer, Summer 2007 © UCB
Instruction Fetch Unit at the End of Jump
31
26 25
J-type
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Jump
Inst
Memory
nPC_sel
Instruction<31:0>
Adr
Zero
nPC_MUX_sel
Adder
0
PC
Mux
Adder
imm16
00
4
How do we modify this
to account for jumps?
1
Clk
CS61C L20 Single-Cycle CPU Control (20)
Beamer, Summer 2007 © UCB
Instruction Fetch Unit at the End of Jump
31
26 25
J-type
0
op
target address
jump
• New PC = { PC[31..28], target address, 00 }
Jump
Inst
Memory
nPC_sel
Instruction<31:0>
Adr
Zero
imm16
Mux
Adder
1
CS61C L20 Single-Cycle CPU Control (21)
00
TA
4 (MSBs)
1
PC
Adder
0
26
Mux
4
00
nPC_MUX_sel
0
Clk
Query
• Can Zero still
get asserted?
• Does nPC_sel
need to be 0?
• If not, what?
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Branch?
31
26
21
op
16
rs
0
rt
immediate
• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
CS61C L20 Single-Cycle CPU Control (22)
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
The Single Cycle Datapath during Branch
31
26
21
op
16
rs
0
rt
immediate
• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
Rs Rt
5
5
5
busA
Rw Ra Rb
RegFile
32
busB
32
imm16
16
Extender
clk
ExtOp=x
CS61C L20 Single-Cycle CPU Control (23)
Rs Rt Rd Imm16
zero ALUctr=SUB
MemtoReg=x
MemWr=0
32
=
ALU
busW
0
32
1
32
<0:15>
RegWr=0
<11:15>
0
<16:20>
Rd Rt
<21:25>
nPC_sel=br
RegDst=x
clk
1
Instruction<31:0>
instr
fetch
unit
Data In
ALUSrc=0
clk
32
0
WrEn Adr
Data
Memory
1
Beamer, Summer 2007 © UCB
Instruction Fetch Unit at the End of Branch
31
26
op
21
rs
16
rt
0
immediate
• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;
else PC = PC + 4
Inst
Memory
nPC_sel
Adr
Zero
Instruction<31:0>
• What is encoding of
nPC_sel?
• Direct MUX select?
• Branch inst. / not branch
MUX
ctrl
nPC_sel
0
00
• Let’s pick 2nd option
Mux
PC
Adder
PC Ext
imm16
Adder
4
1
clk
CS61C L20 Single-Cycle CPU Control (24)
nPC_sel
0
1
1
zero?
x
0
1
MUX
0
0
1
Q: What
logic gate?
Beamer, Summer 2007 © UCB
Step 4: Given Datapath: RTL  Control
Instruction<31:0>
Rd
<0:15>
Rs
<11:15>
Rt
<16:20>
Op Fun
<21:25>
<0:5>
Adr
<26:31>
Inst
Memory
Imm16
Control
nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg
DATA PATH
CS61C L20 Single-Cycle CPU Control (25)
Beamer, Summer 2007 © UCB
A Summary of the Control Signals (1/2)
inst
Register Transfer
add
R[rd]  R[rs] + R[rt];
PC  PC + 4
ALUsrc = RegB, ALUctr = “ADD”, RegDst = rd, RegWr, nPC_sel = “+4”
sub
R[rd]  R[rs] – R[rt];
PC  PC + 4
ALUsrc = RegB, ALUctr = “SUB”, RegDst = rd, RegWr, nPC_sel = “+4”
ori
R[rt]  R[rs] + zero_ext(Imm16);
PC  PC + 4
ALUsrc = Im, Extop = “Z”,ALUctr = “OR”, RegDst = rt,RegWr, nPC_sel =“+4”
lw
R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4
ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”,
MemtoReg, RegDst = rt, RegWr,
nPC_sel = “+4”
sw
MEM[ R[rs] + sign_ext(Imm16)]  R[rs]; PC  PC + 4
ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”
beq
if ( R[rs] == R[rt] ) then PC  PC + sign_ext(Imm16)] || 00 else PC  PC + 4
nPC_sel = “br”, ALUctr = “SUB”
CS61C L20 Single-Cycle CPU Control (26)
Beamer, Summer 2007 © UCB
A Summary of the Control Signals (2/2)
See
Appendix A
func 10 0000 10 0010
We Don’t Care :-)
op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
add
sub
ori
lw
sw
beq
jump
RegDst
1
1
0
0
x
x
x
ALUSrc
0
0
1
1
1
0
x
MemtoReg
0
0
0
1
x
x
x
RegWrite
1
1
1
1
0
0
0
MemWrite
0
0
0
0
1
0
0
nPCsel
0
0
0
0
0
1
?
Jump
0
0
0
0
0
0
1
ExtOp
x
x
0
1
1
x
x
Add
Subtract
Or
Add
Add
Subtract
x
ALUctr<2:0>
31
26
21
16
R-type
op
rs
rt
I-type
op
rs
rt
J-type
op
CS61C L20 Single-Cycle CPU Control (27)
11
rd
6
shamt
immediate
target address
0
funct
add, sub
ori, lw, sw, beq
jump
Beamer, Summer 2007 © UCB
Boolean Expressions for Controller
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
nPCsel
Jump
ExtOp
ALUctr[0]
ALUctr[1]
= add + sub
= ori + lw + sw
= lw
= add + sub + ori + lw
= sw
= beq
= jump
= lw + sw
= sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR)
= or
where,
rtype = ~op5  ~op4  ~op3  ~op2 
ori = ~op5  ~op4  op3  op2 
lw = op5  ~op4  ~op3  ~op2 
sw = op5  ~op4  op3  ~op2 
beq = ~op5  ~op4  ~op3  op2 
jump = ~op5  ~op4  ~op3  ~op2 
~op1  ~op0,
~op1  op0
op1  op0
op1  op0
~op1  ~op0
op1  ~op0
How do we
implement this in
gates?
add = rtype  func5  ~func4  ~func3  ~func2  ~func1  ~func0
sub = rtype  func5  ~func4  ~func3  ~func2  func1  ~func0
CS61C L20 Single-Cycle CPU Control (28)
Beamer, Summer 2007 © UCB
Controller Implementation
opcode
func
“AND” logic
CS61C L20 Single-Cycle CPU Control (29)
add
sub
ori
lw
sw
beq
jump
“OR” logic
RegDst
ALUSrc
MemtoReg
RegWrite
MemWrite
nPCsel
Jump
ExtOp
ALUctr[0]
ALUctr[1]
Beamer, Summer 2007 © UCB
Other Programmable Logic Arrays
• There are other types of PLAs
which can be reprogrammed on the
fly
• The most common is called a Field
Programmable Gate Array (FPGA)
• made up of configurable logic blocks
(CLBs) and flip-flops which can be
programmed by software
• Berkeley has on-going research into
reconfigurable computing with
FPGAs
 Check out RAMP and BEE3 projects
CS61C L20 Single-Cycle CPU Control (30)
Beamer, Summer 2007 © UCB
An Abstract View of the Critical Path
Ideal
Instruction
Memory
PC
clk
32
Instruction
Rd Rs Rt
5 5
5
Rw Ra Rb
Register
File
clk
CS61C L20 Single-Cycle CPU Control (31)
(Assumes a fast controller)
A
32
ALU
Next Address
Instruction
Address
Critical Path (Load Instruction) =
Delay clock through PC (FFs) +
Instruction Memory’s Access Time +
Register File’s Access Time, +
ALU to Perform a 32-bit Add +
Data Memory Access Time +
Stable Time for Register File Write
B
32
32
Data
Addr
Ideal
Data
Memory
Data
In clk
Beamer, Summer 2007 © UCB
Peer Instruction
Instruction<31:0>
RegWr
Rs Rt
5
Extender
16
1
32
Clk
Imm16
MemWr
MemtoReg
0
32
Data In 32
ALUSrc
Rs Rd
WrEn Adr
32
Mux
busA
Rw Ra Rb
32
32 32-bit
Registers busB
0
32
imm16
Rt
Zero
ALUctr
Mux
32
Clk
5
ALU
busW
5
<0:15>
Clk
1 Mux 0
<11:15>
RegDst
Rt
<21:25>
Rd
Instruction
Fetch Unit
<16:20>
nPC_sel
1
Data
Memory
ExtOp
A.
MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?
B.
ALUctr=‘add’. Which 1 signal is different for all 3 of:
ADD, LW, & SW? RegDst or ExtOp?
C.
“Don’t Care” signals are useful because we can
simplify our PLA personality matrix. F / T?
CS61C L20 Single-Cycle CPU Control (32)
0:
1:
2:
3:
4:
5:
6:
7:
ABC
SRF
SRT
SEF
SET
BRF
BRT
BEF
BET
Beamer, Summer 2007 © UCB
Summary: Single-cycle Processor
°5 steps to design a processor
• 1. Analyze instruction set  datapath requirements
• 2. Select set of datapath components & establish clock
methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
• 5. Assemble the control logic
Processor
• Formulate Logic Equations
• Design Circuits
Control
Memory
Datapath
CS61C L20 Single-Cycle CPU Control (33)
Input
Output
Beamer, Summer 2007 © UCB