inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #19 – Designing a Single-Cycle CPU
2007-7-26
Scott Beamer
Instructor
AI Focuses
on Poker
CS61C L19 CPU Design : Designing a Single-Cycle CPU (1)
nytimes.com
Beamer, Summer 2007 © UCB
Review
• N-bit adder-subtractor done using N 1bit adders with XOR gates on input
• XOR serves as conditional inverter
• CPU design involves Datapath,Control
• Datapath in MIPS involves 5 CPU stages
1) Instruction Fetch
2) Instruction Decode & Register Read
3) ALU (Execute)
4) Memory
5) Register Write
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Datapath Summary
• The datapath based on data transfers
required to perform instructions
+4
ALU
Data
memory
rd
rs
rt
registers
PC
instruction
memory
• A controller causes the right transfers
to happen
imm
opcode, funct
Controller
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CPU clocking (1/2)
For each instruction, how do we control the
flow of information though the datapath?
• Single Cycle CPU: All stages of an
instruction are completed within one long
clock cycle.
• The clock cycle is made sufficient long to allow
each instruction to complete all stages without
interruption and within one cycle.
1. Instruction
Fetch
2. Decode/
Register
Read
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3. Execute 4. Memory
5. Reg.
Write
Beamer, Summer 2007 © UCB
CPU clocking (2/2)
For each instruction, how do we control the
flow of information though the datapath?
• Multiple-cycle CPU: Only one stage of
instruction per clock cycle.
• The clock is made as long as the slowest stage.
1. Instruction
Fetch
2. Decode/
3. Execute 4. Memory
Register
Read
5. Reg.
Write
Several significant advantages over single cycle
execution: Unused stages in a particular
instruction can be skipped OR instructions can
be pipelined (overlapped).
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How to Design a Processor: step-by-step
• 1. Analyze instruction set architecture (ISA)
 datapath requirements
• meaning of each instruction is given by the
register transfers
• datapath must include storage element for ISA
registers
• datapath must support each register transfer
• 2. Select set of datapath components and
establish clocking methodology
• 3. Assemble datapath meeting requirements
• 4. Analyze implementation of each
instruction to determine setting of control
points that effects the register transfer.
•
5. Assemble the control logic (hard part!)
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Beamer, Summer 2007 © UCB
Review: The MIPS Instruction Formats
• All MIPS instructions are 32 bits long. 3 formats:
31
26
op
• R-type
rs
6 bits
31
• I-type
26
op
31
16
rt
5 bits
5 bits
21
rs
6 bits
• J-type
21
5 bits
11
rd
shamt
funct
5 bits
5 bits
6 bits
16
6 bits
• The different fields are:
0
0
address/immediate
rt
5 bits
16 bits
26
op
6
0
target address
26 bits
• op: operation (“opcode”) of the instruction
• rs, rt, rd: the source and destination register specifiers
• shamt: shift amount
• funct: selects the variant of the operation in the “op” field
• address / immediate: address offset or immediate value
• target address: target address of jump instruction
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Step 1a: The MIPS-lite Subset for today
• ADDU and SUBU31
•addu rd,rs,rt
op
31
op
31
•lw rt,rs,imm16
•sw rt,rs,imm16
31
• BRANCH:
•beq rs,rt,imm16
26
op
6 bits
rs
5 bits
CS61C L19 CPU Design : Designing a Single-Cycle CPU (8)
shamt
funct
5 bits
5 bits
6 bits
0
16 bits
0
immediate
5 bits
21
0
rd
16
rt
5 bits
6
immediate
5 bits
21
rs
11
16
rt
5 bits
26
6 bits
5 bits
21
rs
op
16
rt
5 bits
26
•ori rt,rs,imm166 bits
• LOAD and
STORE Word
21
rs
6 bits
•subu rd,rs,rt
• OR Immediate:
26
16 bits
16
rt
5 bits
0
immediate
16 bits
Beamer, Summer 2007 © UCB
Register Transfer Language
• RTL gives the meaning of the instructions
{op , rs , rt , rd , shamt , funct}  MEM[ PC ]
{op , rs , rt , Imm16}  MEM[ PC ]
• All start by fetching the instruction
inst
Register Transfers
ADDU R[rd]  R[rs] + R[rt];
PC  PC + 4
SUBU
R[rd]  R[rs] – R[rt];
PC  PC + 4
ORI
R[rt]  R[rs] | zero_ext(Imm16);
PC  PC + 4
LOAD R[rt]  MEM[ R[rs] + sign_ext(Imm16)]; PC  PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ]  R[rt]; PC  PC + 4
BEQ if ( R[rs] == R[rt] ) then
PC  PC + 4 + (sign_ext(Imm16) || 00)
else PC  PC + 4
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Step 1: Requirements of the Instruction Set
• Memory (MEM)
• instructions & data (will use one for each)
• Registers (R: 32 x 32)
• read RS
• read RT
• Write RT or RD
• PC
• Extender (sign/zero extend)
• Add/Sub/OR unit for operation on
register(s) or extended immediate
• Add 4 or extended immediate to PC
• Compare registers?
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Step 2: Components of the Datapath
•Combinational Elements
•Storage Elements
• Clocking methodology
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Combinational Logic Elements (Building Blocks)
A
B
32
Adder
•Adder
CarryIn
32
Sum
CarryOut
32
Select
B
32
MUX
•MUX
A
32
Y
32
OP
A
B
ALU
•ALU
32
32
Result
32
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ALU Needs for MIPS-lite + Rest of MIPS
• Addition, subtraction, logical OR, ==:
ADDU R[rd] = R[rs] + R[rt]; ...
SUBU R[rd] = R[rs] – R[rt]; ...
ORI R[rt] = R[rs] | zero_ext(Imm16)...
BEQ
if ( R[rs] == R[rt] )...
• Test to see if output == 0 for any ALU
operation gives == test. How?
• P&H also adds AND,
Set Less Than (1 if A < B, 0 otherwise)
• ALU follows chap 5
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What Hardware Is Needed? (1/2)
• PC: a register which keeps track of
memory addr of the next instruction
• General Purpose Registers
• used in Stages 2 (Read) and 5 (Write)
• MIPS has 32 of these
• Memory
• used in Stages 1 (Fetch) and 4 (R/W)
• cache system makes these two stages as
fast as the others, on average
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What Hardware Is Needed? (2/2)
• ALU
• used in Stage 3
• something that performs all necessary
functions: arithmetic, logicals, etc.
• we’ll design details later
• Miscellaneous Registers
• In implementations with only one stage
per clock cycle, registers are inserted
between stages to hold intermediate data
and control signals as they travels from
stage to stage.
• Note: Register is a general purpose term
meaning something that stores bits. Not
all registers are in the “register file”.
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Storage Element: Idealized Memory
Write Enable
• Memory (idealized)
Data In
• One input bus: Data In
32
• One output bus: Data Out Clk
Address
DataOut
32
• Memory word is selected by:
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memory
word to be written via the Data In bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
operation
• During read operation, behaves as a
combinational logic block:
 Address valid  Data Out valid after “access time.”
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Storage Element: Register (Building Block)
• Similar to D Flip Flop except
 N-bit input and output
 Write Enable input
• Write Enable:
Write Enable
Data In
N
Data Out
 negated (or deasserted) (0):
Data Out will not change
clk
 asserted (1):
Data Out will become Data In on positive
edge of clock
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N
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Storage Element: Register File
• Register File consists of 32 registers:
• Two 32-bit output busses:
busA and busB
• One 32-bit input bus: busW
• Register is selected by:
RW RA RB
Write Enable 5 5 5
busW
32
Clk
busA
32
32 32-bit
Registers busB
32
• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be written
via busW (data) when Write Enable is 1
• Clock input (clk)
• The clk input is a factor ONLY during write operation
• During read operation, behaves as a combinational
logic block:
 RA or RB valid  busA or busB valid after “access time.”
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Administrivia
• Assignments
• HW5 due Tonight
• HW6 due 7/29
• Midterm
• Grading standards up
• If you wish to have a problem regraded
 Staple your reasons to the front of the exam
 Return your exam to your TA
• Scott is now holding regular OH on
Fridays 11-12 in 329 Soda
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Step 3: Assemble DataPath meeting requirements
• Register Transfer Requirements
 Datapath Assembly
• Instruction Fetch
• Read Operands and Execute Operation
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3a: Overview of the Instruction Fetch Unit
• The common RTL operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
 Sequential Code: PC  PC + 4
 Branch and Jump: PC  “something else”
clk
PC
Next Address
Logic
Address
Instruction
Memory
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Instruction Word
32
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3b: Add & Subtract
• R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt
• Ra, Rb, and Rw come from instruction’s Rs, Rt,
26
21
16
11
6
and Rd fields 31
op
6 bits
rs
5 bits
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
0
• ALUctr and RegWr: control logic after decoding
the instruction
Rd Rs Rt
RegWr 5 5 5
Rw Ra Rb
32 32-bit
Registers
busA
32
busB
clk
ALU
busW
32
ALUctr
Result
32
32
Already defined the register file & ALU
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Clocking Methodology
Clk
.
.
.
.
.
.
.
.
.
.
.
.
• Storage elements clocked by same edge
• Being physical devices, flip-flops (FF) and
combinational logic have some delays
• Gates: delay from input change to output change
• Signals at FF D input must be stable before active clock
edge to allow signal to travel within the FF (set-up time),
and we have the usual clock-to-Q delay
• “Critical path” (longest path through logic)
determines length of clock period
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Register-Register Timing: One complete cycle
Clk
New Value
PC Old Value
Rs, Rt, Rd,
Op, Func
Old Value
ALUctr
Old Value
RegWr
Old Value
busA, B
Old Value
busW
Old Value
Instruction Memory Access Time
New Value
Delay through Control Logic
New Value
New Value
Register File Access
Time New Value
ALU Delay
New Value
ALUctr
RegWr Rd Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
CS61C L19 CPU Design : Designing a Single-Cycle CPU (24)
Register Write
Occurs Here
32
ALU
busW
5
32
32
Beamer, Summer 2007 © UCB
3c: Logical Operations with Immediate
• R[rt] = R[rs] op ZeroExt[imm16] ]
31
26
op
31 6 bits
21
rs
16
rt
5 bits
0
immediate
5 bits 16 15
16 bits
0
immediate
0000000000000000
16 bits
16 bits
But we’re writing to Rt register??
ALUctr
RegWr Rd Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
CS61C L19 CPU Design : Designing a Single-Cycle CPU (25)
32
ALU
busW
5
32
32
Beamer, Summer 2007 © UCB
3c: Logical Operations with Immediate
• R[rt] = R[rs] op ZeroExt[imm16] ]
31
26
21
op
rs
31 6 bits
RegDst
RegWr
Rs Rt
5
16 bits
0
immediate
16 bits
ALUctr
5
Rw Ra Rb
busA
RegFile
busB
32
16
ZeroExt
clk
imm16
immediate
5 bits 16 15
32
ALU
32
0
What about Rt register read??
0
5
5 bits
rt
0000000000000000
16 bits
Rd Rt
1
16
0
32
1
32
ALUSrc
• Already defined 32-bit MUX; Zero Ext?
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3d: Load Operations
• R[rt] = Mem[R[rs] + SignExt[imm16]]
Example: lw rt,rs,imm16
31
26
21
op
16
rs
6 bits
0
rt
5 bits
immediate
5 bits
16 bits
RegDst Rd Rt
1
RegWr
5
Rs Rt
5
ALUctr
5
Rw Ra Rb
busA
RegFile
busB
32
imm16
16
ZeroExt
clk
CS61C L19 CPU Design : Designing a Single-Cycle CPU (27)
32
0
ALU
32
0
32
1
32
ALUSrc
Beamer, Summer 2007 © UCB
3d: Load Operations
• R[rt] = Mem[R[rs] + SignExt[imm16]]
Example: lw rt,rs,imm16
31
26
21
op
16
rs
6 bits
0
rt
5 bits
immediate
5 bits
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
Extender
clk
32
0
1
32
ExtOp
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ALU
busW
MemtoReg
MemWr
? 32
Data In
ALUSrc clk
32
0
WrEn Adr
Data
Memory
1
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3e: Store Operations
• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
31
26
21
op
6 bits
16
rs
5 bits
0
rt
5 bits
immediate
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
Extender
clk
32
0
ALU
busW
MemtoReg
MemWr
32
0
32 WrEn Adr
1
32
ExtOp
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Data In
ALUSrc clk
Data
Memory
1
Beamer, Summer 2007 © UCB
3e: Store Operations
• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
31
26
21
op
6 bits
16
rs
5 bits
0
rt
5 bits
immediate
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
Extender
clk
32
0
ALU
busW
MemtoReg
MemWr
32
0
32 WrEn Adr
1
32
ExtOp
CS61C L19 CPU Design : Designing a Single-Cycle CPU (30)
Data In
ALUSrc clk
Data
Memory
1
Beamer, Summer 2007 © UCB
3f: The Branch Instruction
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
beq rs, rt, imm16
• mem[PC] Fetch the instruction from memory
• Equal = R[rs] == R[rt] Calculate branch condition
• if (Equal) Calculate the next instruction’s
address
 PC = PC + 4 + ( SignExt(imm16) x 4 )
else
 PC = PC + 4
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Beamer, Summer 2007 © UCB
Datapath for Branch Operations
• beq rs, rt, imm16
Datapath generates condition (equal)
31
26
op
6 bits
21
rs
5 bits
16
0
rt
5 bits
immediate
16 bits
Inst Address
Equal
nPC_sel
Adder
4
00
clk
busW
5
ALUctr
Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
32
=
ALU
PC
Mux
Adder
PC Ext
imm16
RegWr
32
32
Already have mux, adder, need special sign
extender for PC, need equal compare (sub?)
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Putting it All Together:A Single Cycle Datapath
RegDst
32
Equal
0
5
5
5
busA
Rw Ra Rb
RegFile
busB
32
16
Extender
imm16
MemtoReg
MemWr
Rs Rt
clk
clk
ALUctr
32
=
ALU
busW
PC
PC Ext
Adder
Mux
00
RegWr
Adder
4
Rt Rd Imm16
Rd Rt
1
Instruction<31:0>
<0:15>
nPC_sel
Rs
<11:15>
Adr
<16:20>
<21:25>
Inst
Memory
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
imm16
ExtOp
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ALUSrc
Beamer, Summer 2007 © UCB
Peer Instruction
A. For the CPU designed so far, the
Controller only needs to look at
opcode/funct and Equal
B. Adding jal would only require
changing the Instruction Fetch
block
C. Making our single-cycle CPU
multi-cycle will be easy
CS61C L19 CPU Design : Designing a Single-Cycle CPU (34)
0:
1:
2:
3:
4:
5:
6:
7:
ABC
FFF
FFT
FTF
FTT
TFF
TFT
TTF
TTT
Beamer, Summer 2007 © UCB
How to Design a Processor: step-by-step
1. Analyze instruction set architecture (ISA)
=> datapath requirements
• meaning of each instruction is given by the
register transfers
• datapath must include storage element for ISA
registers
• datapath must support each register transfer
2. Select set of datapath components and
establish clocking methodology
3. Assemble datapath meeting requirements
4. Analyze implementation of each instruction
to determine setting of control points that
effects the register transfer.
5. Assemble the control logic
CS61C L19 CPU Design : Designing a Single-Cycle CPU (35)
Beamer, Summer 2007 © UCB