inst.eecs.berkeley.edu/~cs61c
Lecture 23 –
Representations of Combinatorial Logic
Circuits
2006-10-20
TA/Punner David Poll www.depoll.com
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CS61C L23 Representations of Combinatorial Logic Circuits (1) Garcia, Fall 2006 © UCB

Hello
• “Hello, world!”
CS61C L23 Representations of Combinatorial Logic Circuits (2) Garcia, Fall 2006 © UCB

Review
• State elements are used to:
• Build memories
• Control the flow of information between other state elements and combinational logic
• D-flip-flops used to build registers
• Clocks tell us when D-flip-flops change
• Setup and Hold times important
• We pipeline long-delay CL for faster clock
• Finite State Machines extremely useful
• Represent states and transitions
Garcia, Fall 2006 © UCB CS61C L23 Representations of Combinatorial Logic Circuits (3)

Combinational Logic
• FSMs had states and transitions
• How to we get from one state to the next?
• Answer: Combinational Logic
CS61C L23 Representations of Combinatorial Logic Circuits (4) Garcia, Fall 2006 © UCB

Truth Tables
0
CS61C L23 Representations of Combinatorial Logic Circuits (5) Garcia, Fall 2006 © UCB

TT Example #1: 1 iff one (not both) a,b=1 a b y
0 0 0
0 1 1
1 0 1
1 1 0
CS61C L23 Representations of Combinatorial Logic Circuits (6) Garcia, Fall 2006 © UCB

TT Example #2: 2-bit adder
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How
Many
Rows?
Garcia, Fall 2006 © UCB

TT Example #3: 32-bit unsigned adder
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How
Many
Rows?
Garcia, Fall 2006 © UCB

TT Example #3: 3-input majority circuit
CS61C L23 Representations of Combinatorial Logic Circuits (9) Garcia, Fall 2006 © UCB

Logic Gates (1/2)
CS61C L23 Representations of Combinatorial Logic Circuits (10) Garcia, Fall 2006 © UCB

And vs. Or review – Dan’s mnemonic
A
B
Symbol
AN
D
AND Gate
Definition
C A B C
0 0 0
0 1 0
1 0 0
1 1 1
Garcia, Fall 2006 © UCB CS61C L23 Representations of Combinatorial Logic Circuits (11)

Logic Gates (2/2)
CS61C L23 Representations of Combinatorial Logic Circuits (12) Garcia, Fall 2006 © UCB

2-input gates extend to n-inputs
• N-input XOR is the only one which isn’t so obvious
• It’s simple: XOR is a
1 iff the # of 1s at its input is odd

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Truth Table

Gates (e.g., majority circ.)
CS61C L23 Representations of Combinatorial Logic Circuits (14) Garcia, Fall 2006 © UCB

Truth Table

Gates (e.g., FSM circ.)
PS Input NS Output
00 0 00 0
00 1 01
01 0 00
0
0
01 1 10
10 0 00
10 1 00
0
0
1
CS61C L23 Representations of Combinatorial Logic Circuits (15) or equivalently…
Garcia, Fall 2006 © UCB

Boolean Algebra
• George Boole, 19 th Century mathematician
• Developed a mathematical system (algebra) involving logic
• later known as “Boolean Algebra”
• Primitive functions: AND, OR and NOT
• The power of BA is there’s a one-to-one correspondence between circuits made up of AND, OR and NOT gates and equations in BA
+ means OR,• means AND, x means NOT
Garcia, Fall 2006 © UCB CS61C L23 Representations of Combinatorial Logic Circuits (16)

Boolean Algebra (e.g., for majority fun.) y = a • b + a • c + b • c y = ab + ac + bc
CS61C L23 Representations of Combinatorial Logic Circuits (17) Garcia, Fall 2006 © UCB

Boolean Algebra (e.g., for FSM)
PS Input NS Output
00 0 00 0
00 1 01
01 0 00
01 1 10
10 0 00
10 1 00
0
0
0
0
1 or equivalently… y = PS
1
• PS
0
• INPUT
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BA: Circuit & Algebraic Simplification
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BA also great for circuit verification
Circ X = Circ Y?
use BA to prove!
Garcia, Fall 2006 © UCB

Laws of Boolean Algebra
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Boolean Algebraic Simplification Example
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Canonical forms (1/2)
Sum-of-products
(ORs of ANDs)
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Canonical forms (2/2)
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Peer Instruction
A.
(a+b)• (a+b) = b
B. N-input gates can be thought of cascaded 2-input gates. I.e.,
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND
C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT
CS61C L23 Representations of Combinatorial Logic Circuits (24)
ABC
1: FFF
2: FF T
3: F T F
4: F TT
5: T FF
6: T F T
7: TT F
8: TTT
Garcia, Fall 2006 © UCB

Peer Instruction Answer
A.
(a+b)•(a+b) = aa+ab+ba+bb = 0+b(a+a)+b = b+b = b TRUE
B. (next slide)
C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT.
° NOR(a,a)= a+a = aa = a
° Using this NOT, can we make a NOR an OR? An And?
° TRUE
A.
(a+b)• (a+b) = b
B. N-input gates can be thought of cascaded 2-input gates. I.e.,
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND
C. You can use NOR(s) with clever wiring to simulate AND, OR, & NOT
CS61C L23 Representations of Combinatorial Logic Circuits (25)
ABC
1: FFF
2: FF T
3: F T F
4: F TT
5: T FF
6: T F T
7: TT F
8: TTT
Garcia, Fall 2006 © UCB

A.
Peer Instruction Answer (B)
B.
N-input gates can be thought of cascaded 2-input gates. I.e.,
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e)) where ∆ is one of AND, OR, XOR, NAND… FALSE
Let’s confirm!
CORRECT 3-input
XYZ|AND|OR|XOR|NAND
000
00
0
0
1
1
1
0
11
0
00
0
|
1|
|
11|
|
1|
|
0
0
0
0 0 0 1
0 1 1 1
0 1 1 1
0
0
0
0
| 0 |
|1 | 1 | 1
|1 | 1 | 1
|1 |
0 1
0 1
|1 | 0
0
1
0
111| 1 |1 | 1 | 0
1
|1 | 1 | 1
|1 |
0 1
1 1
0
0
0
| 1
| 1
| 1
0 0
1 1
CORRECT 2-input
YZ|AND|OR|XOR|NAND
00 | 0 | 0 | 0 | 1
0 1| 0 |1 | 1 | 1
1 0 | 0 |1 | 1 | 1
11| 1 |1 | 0 | 0
Garcia, Fall 2006 © UCB CS61C L23 Representations of Combinatorial Logic Circuits (26)

“And In conclusion…”
• Pipeline big-delay CL for faster clock
• Finite State Machines extremely useful
• You’ll see them again in 150, 152 & 164
• Use this table and techniques we learned to transform from 1 to another
CS61C L23 Representations of Combinatorial Logic Circuits (27) Garcia, Fall 2006 © UCB