Week 12/ Lecture 22 Nov. 17, 2005
1. Overview of Digital Systems
2. CMOS Inverter
3. CMOS Gates
4. Digital Logic
5. Combinational Blocks
6. Latches and Flip Flops
7. Registers and Counters
Reading: Hambley 12.7, 7
EE42/100 Fall 2005
Prof. Fearing
1
Decoder
•n inputs, 2n outputs
– one output is 1 for each possible input pattern,
all other outputs are 0
1
A
B
2
3
4
EE42/100 Fall 2005
Prof. Fearing
2
Multiplexer (MUX)
•n-bit selector and 2n inputs, one output
– output equals one of the inputs, depending on
selector
I1
I2
I3
I4
A
B
O
2 input decoder
EE42/100 Fall 2005
Prof. Fearing
3
Flip-Flops
• One of the basic building blocks for sequential circuits is
the flip-flop:
– 2 stable operating states  stores 1 bit of info.
– A simple flip-flop can be constructed using two inverters:
Q
Q
EE42/100 Fall 2005
Prof. Fearing
4
Realization of the S-R Flip-Flop
S
Q
Q
R
S-R Flip-Flop Symbol:
S Q
R Q
EE42/100 Fall 2005
Prof. Fearing
R
S
Qn
0
0
1
1
0
1
0
1
Qn-1
1
0
(not allowed)
5
Clocked S-R Flip-Flop
S
Q
CK
Q
R
• When CK = 0, the value of Q does not change
• When CK = 1, the circuit acts like an ordinary S-R flip-flop
vC(t)
positive-going edge
(leading edge)
negative-going edge
(trailing edge)
VOH
0
EE42/100 Fall 2005
time
TC
2TC
Prof. Fearing
6
The D (“Delay”) Flip-Flop
D
D Flip-Flop Symbol:
Q
CK Q
• The output terminals Q and Q behave just as in the S-R
flip-flop.
• Q changes only when the clock signal CK makes a
positive transition.
EE42/100 Fall 2005
Prof. Fearing
CK
D
Qn
0
1




0
1
Qn-1
Qn-1
0
1
7
D Flip-Flop Example (Timing Diagram)
CK
t
D
t
Q
t
EE42/100 Fall 2005
Prof. Fearing
8
Registers
• A register is an array of flip-flops that is used to store or manipulate
the bits of a digital word.
Example: 4 bit data register
OUT1
OUT2
OUT3
OUT4
"0"
R S
D Q
R S
D Q
R S
D Q
R S
D Q
CLK
IN1
EE42/100 Fall 2005
IN2
IN3
Prof. Fearing
IN4
9
Registers
Example: Serial-In, Parallel-Out Shift Register
Parallel outputs
Data input
Q0
Q1
Q2
D0 Q0
D1 Q1
D2 Q2
CK
CK
CK
Clock input
Parallel to serial converter
Reset
“0”
R S
D Q
R S
D Q
R S
D Q
R S
D Q
Output
Clock
“0” literal
IN1
IN2
IN3
IN4
mux
Load/Shift
EE42/100 Fall 2005
Prof. Fearing
10
Shift Register Application
• Parallel-to-serial conversion for serial
transmission
parallel outputs
parallel inputs
serial transmission
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Prof. Fearing
11
Finite State Machine Block diagram/Counter example
Inputs (N)
Combinatorial
Logic
Qn+1
Register
(N+M edge
triggered
flip-flops)
outputs
next
state
present
state
Q2
Q1
Q0
Q2
Q1
Q0
Clock
Current state of the system: Qn (M states)
Clock
Q2 Q1 Q0
Counter
NS=PS+1
Clock
(good for freq division, position, velocity sensing)
EE42/100 Fall 2005
Prof. Fearing
12