Compound Semiconductor IC Symposium 2010
Chart 1
A 204.8GHz Static Divide-by-8 Frequency Divider
in 250nm InP HBT
Zach Griffith, Miguel Urteaga, Richard Pierson, Petra Rowell,
Mark Rodwell*, and Bobby Brar
Teledyne Scientific Company, Thousand Oaks, CA 91360, USA
*Department of Electrical and Computer Eng., UC Santa Barbara
e-mail: zgriffith@teledyne.com, phone: 805-373-4104
Why Static Frequency Dividers ?
Chart 2
MS flip-flops are very widely-used high speed digital circuits:
• Dividers are master-slave flip-flop with inverting feedback
• Connection as 2:1 frequency divider provides simple test method
Standard benchmark of logic speed:
• Performance comparisons across technologies
Dynamic, super-dynamic, frequency dividers:
• Higher maximum frequency than true static dividers
• Narrow-band operation  applications are limited
High speed technology performance for static dividers:
• 250nm InP HBT: NGAS 200.6GHz (2009), TSC/UCSB 204.8GHz (2010)
• Advanced SiGe HBT: Infinion 110+GHz
Fast divider design – identifying dominant gate delays
Chart 3
Gate Delay Determined by :
Depletion capacitanc e charging
through the logic swing
 VLOGIC 

Ccb  Cbe,depletion 
 IC 
Depletion capacitanc e charging
through the base resistance
Rbb Ccb  Cbe,depletion 
Supplying base  collector
stored charge
through the base resistance
 IC 

Rbb  b   c 
 VLOGIC 
The logic swing must be at least
 kT

VLOGIC  6
 Rex I c 
 q

out
out
in
in
clock
clock
clock
clock
Delay not well correlated with HBT delay 1/(2f ).
VLOGIC
I C Ccb  Cbe,depl  is 60% - 80% of total.
Low Ccb / I c  is a key HBT design objective.
 Acollector  TC 





 Aemitter  2veffective 
Rex must be very low for low Vlogic at high J e
Ccb VLOGIC VLOGIC

IC
2VCE ,min
...Need to design for clock speed, not fτ & fmax
200GHz dividers – collector design for 250nm HBTs
Chart 4
Collector Field Collapse (Kirk Effect)
base
Vcb    ( J / vsat  qN d )(Tc2 / 2 )
emitter
sub
collector
collector
Collector Depletion Layer Collapse
Vcb,min    (qN d )(Tc2 / 2 )
base
emitter
sub
collector
 J max  2vsat (Vce  Vce,min ) / Tc2
(1-D collector current flow)
collector
0.25um HBT, 200GHz divider – vertical, lateral scaling for Je = 10mA/um2
0.5um HBT, 150GHz divider, Je = 5mA/um2
Ccb,1
ΔVlogic
IC

ε o ε r A c,1 ΔVlogic
TC,1 Je,1A e,1
Ccb,2
Ccb,2
ΔVlogic
IC
ΔVlogic
IC


ε oεr
1
A c,1
2
2
TC,1
3
ΔVlogic
ΔVlogic
3
 Ccb,1
1
IC
2Je,1  A e,1 4
2
1
A c,1 ΔV
ΔVlogic
1
logic
2
 Ccb,1
1
TC,1
IC
2Je,1  A e,1 2
2
ε oεr
Lateral scaling, current spreading for Je = 10mA/um2
33% reduction
Key HBT Scaling Limit  Emitter Resistance
Chart 5
ECL delay not well correlated with f or fmax
RL
Largest delay is charging Ccb
Ccb
ΔVlogic
IC

Rex
ε o ε r A collector ΔVlogic
; where Je,max  1/Tc2 .
TC
Je A emitter
Io
Noise margin
 Je  10 mA/m2 needed for 200 GHz clock rate
Voltage drop of emitter resistance becomes excessive
RexIc = exJe = (15 m2)  (10 mA/m2) = 150 mV
 considerable fraction of Vlogic  300 mV
Degrades logic noise margin
 ex  7 m2 needed for 200 GHz clock rate
This slide presented at BCTM 2004 for phase-I 150GHz divider.
HBT metrics here invoked to demonstrate the phase-III 200GHz divider.
Vout
Vin
Vlogic
2kT/q+IoRex
Vlogic=IoRL
Ccb/Ic Charging Rate: ECL delays lower than CML
Chart 6
10
V
Zo
8
cb
25
= -0.3 V
20
-0.2 V
15
e
0.0 V
0.2 V
10
cb
4
V
2
cb
cb
6
C (fF)
C /A (fF/m2)
CML
= 0.6 V
5
0
0
2.5
5
7.5
10
2
0
12.5
J (mA/m )
e
10
V
logic
V
= 300mV
8
cb
25
= -0.3 V
20
-0.2 V
15
e
0.0 V
0.2 V
4
10
Vcb = 0.6 V
2
5
0
0
2.5
5
7.5
2
J (mA/m )
e
10
0
12.5
Ccb (fF)
6
cb
Zo
C /A (fF/m2)
ECL
Design approach for 200GHz logic
Chart 7
Approach: (new design elements presented in bold)
• Emitter coupled logic (ECL) topology
• Faster HBTs with lower Ccb and lower Rex (-um2)
• Scaled device from 0.5um to 0.25um
• 150nm collector, 30nm base (400GHz ft, 650GHz fmax)
• Reduce signal bus and loading delays
• Decreased device-to-device spacing
• Thin-film microstrip with low loss r = 2.7
• Resistive pulldown voltage biasing
• Small peaking inductance Lpeak
• Emitter-follower HBTs having reduced Ccb (Q1, Q2)
• Collector-base DC voltage Vcb increased
Q1, Q2 Ccb reduction
Schematic of a flip-flop configured as a static divider
Block diagram of Divide-by-8
IC micrographs of the TSC 200GHz Static Frequency Dividers
Chart 8
Final fabrication, top-metal ground plane omitted
Divide-by-2 circuit, 36 HBTs (0.420.41-mm2)
Divide-by-8 circuit, 108 HBTs (0.680.45-mm2)
TSC/UCSB/GSC 150GHz divider (September 2004)
Output Power (dBm)
-20
Chart 9
Technology cross-section, phase-I
-40
-50
dBm
-10
-60
-30
-40
-70
-80
75.9975
76.0000
GHz
76.0025
-50
-60
-70
y = 470um
-80
-90
0.00
19.50
39.00
58.50
frequency (GHz)
78.00
Phase-I divider @ 152GHz
DC power ~ 600mW
190um
x = 500um
Summary of divider physical size:
• 5um device-to-device spacing
112um
• Two-sided collector HBT
• Latch width = 112um
• Latch-to-buffer signal distance = 190um
CMET = Blue
MET-1 = Red
Close-up view of flip-flop interconnect, configured for divide-by-2
TSC/UCSB 200GHz divider – scaling summary
Chart 10
y = 410um
TSC mixed-signal technology cross-section
DC power ~ 592mW
x = 420um
64um
Summary of divider physical size:
• 2um device-to-device spacing
• One-sided narrower collector HBT
• Latch width = 50um (55% reduction)
50um
• Latch-to-buffer signal distance = 64um
• 66% reduction
Simulated CLK rate, 213GHz
Close-up view of flip-flop interconnect, configured for divide-by-2
Probe-station for 200GHz divider testing
Chart 11
Mechanical attenuator
200GHz source
WR-05 output power sweep
Output
Close-up showing wafer probes
Output at 204.8GHz operation
200GHz 8x VDI source from UCSB
Probe station for 200GHz testing
Divide-by-8 static divider operating to 204.8GHz
Chart 12
0
5MHz span
Low-frequency verification
-40
-60
-80
-100
-40
25.5975
25.6000
GHz
25.6025
-60
-80
-100
0
0
10
20
30
40
Frequency (GHz)
50
Divider output – fclk = 204.8GHz, fout = 25.60GHz
Output Power (dBm)
-20
dBm
Output Power (dBm)
0
-20
-20
-40
-60
-80
-100
0
5
10
15
20
Frequency (GHz)
Divider output – fclk = 4.0GHz, fout = 500MHz
• Peak divider toggle rate is 204.8GHz
• Expected output at 25.60GHz, no spectral content at lower frequencies
• Input divider operational down to 4.0GHz to confirm static operation at all frequencies
• 3rd-stage divider is operating at 1.0GHz clock (differential 350mVp-p), 500MHz final output
• PDC of divide-by-8 circuit = 1.82W
• Input divider operating at 204.8GHz, PDC = 592mW
25
Sensitivity plot of the 204.8GHz static divider
Chart 13
0
10
-40
-60
-80
-100
-40
25.5975
25.6000
GHz
25.6025
-60
-80
-100
0
182-209GHz 8x FEM
5MHz span
10
20
30
40
Frequency (GHz)
50
Divider output – fclk = 204.8GHz, fout = 25.60GHz
Input Power (dBm)
-20
dBm
Output Power (dBm)
0
-20
0.1-50GHz source
0
61-113GHz tripler
-10
-20
-30
Source-free self-oscillation @ 143GHz
0
50
100
150
Frequency (GHz)
200
Sensitivity plot, 204.8GHz static divider
• Sensitivity plot of the divider: 0.1-50GHz, 61.5-113.25GHz, 182.4-204.8GHz
• Expected trends of input power sensitivity versus frequency observed
• Source-free self oscillation (no input signal) reference to the input is 143GHz
Summary
Chart 14
• A record static divide-by-8 frequency divider has been demonstrated
–
–
–
–
108 HBTs, all having 250nm features
TSC 4-metal layer, mixed-signal interconnect
Operational from 4.0GHz to 204.8GHz
Total PDC = 1.82W, input divider only (no buffers) = 592mW
• Continued increases to static divider toggle rate require balanced
reductions to HBT base Rbb and emitter resistance Rex, and junction
capacitances Cje, Ccb.
– Presentation (Tues-F1) by M. Urteaga discusses recent HBT developments
Acknowledgement
Chart 15
• This work was supported under the DARPA TFAST program,
Sanjay Raman program manager.
Thank you!!