Laser Controller One (LC1)
A.R. Hertneky
J.W. O’Brien
J.T. Shin
C.S. Wessels
www.teamvice.net
Outline
•
•
•
•
•
February 28, 2006
Background
Architecture and parts
Interfaces
Circuit/logic design
Updated schedule &
responsibilities
Critical Design Review (CDR)
2
Laser Controller One (LC1)
• Interacts with laser
analog control system
• Consists of rackmountable enclosure
with connections to
external devices
• Will manage laser
system to establish
and maintain
frequency lock
February 28, 2006
Critical Design Review (CDR)
3
Analog signals
f0
1
0
724.8
nm
'
f1
0.5
0
0.5
724.8
nm
''
f2
0.5
0
2
724.8
February 28, 2006
nm
• Saturated absorption
spectroscopy (sat spec)
raw signal is subject to
high-pass filtering
• Derivatives can still be
generated using a mixer
• Use sat spec (f0) to
update LCD
• Use first derivative (f1)
to locate peaks
• Use second derivative
(f2) to monitor lock
Critical Design Review (CDR)
4
System Environment Block Diagram
Raw SATSPEC Output
[Existing Control Circuitry]
Error Offset Monitor
1 st Derivative
[Existing Control Circuitry]
2 nd Derivative
[Vice Differential Circuitry]
Legend
Input
Laser Control 1 (LC-1)
Output
Digital Interconnect
Analog Interconnect
Offset Control
Sweep
Switch
[Existing Control Circuitry]
[Existing Control Circuitry]
[Existing Control Circuitry]
February 28, 2006
Critical Design Review (CDR)
5
Microprocessor
Freescale M68EC020 Microprocessor
• Clock speed for…
– wire wrapped prototype: 12MHz
– PCB integration: 25MHz
•
•
•
•
February 28, 2006
32-bit data/24-bit address
Dynamic bus sizing
Instruction cache
100-QFP package
Critical Design Review (CDR)
6
Data Flow Block Diagram
Data Bus
32
Graphical LCD Display
Crystalfontz
CFAG12864B-TMI-V
8
3
CPU
32
3
Shaft Encoder/Push Button
Grayhill
62A11-02-050S
3
Freescale
MC68EC020
CPLD
Xilinx
XC95108
Digital I/O
LEDs
DAC
Analog Devices
AD7249
FPGA
ADC
Digilent Spartan 3
XC3S1000 Core
Development Board
32
32
Analog Devices
AD7890
256k x 16
SRAM
16
Cypress
CY7C1041B
1MB
16
Counter Timer
Intersil
82C54
256k x 16
8
8
RS-232 Driver
UART
Maxim
MAX233
National Semiconductor
PC16552D
Keypad Decoder
Keypad
Fairchild
MM74C922
Grayhill
96BB2-006-F
8
8
32
8
8
256k x 8
256k x 8
256k x 8
Flash Memory
Atmel
AT49F002A
1MB
8 256k x 8
February 28, 2006
Critical Design Review (CDR)
7
Memory Map
February 28, 2006
Start
0x000000
End
0x0FFFFF
Peripheral
0x100000
0x1FFFFF
SRAM
0x300000
0x3FFFFF
FPGA
0x400000
0x40FFFF
UARTs
0x410000
0x41FFFF
Counter/timers
0x420000
0x42FFFF
Key pad
0x430000
0x43FFFF
Shaft encoder
0x440000
0x44FFFF
LCD
0x450000
0x45FFFF
Digital I/O
Flash
Critical Design Review (CDR)
8
Control Flow Block Diagram
Graphical LCD Display
Crystalfontz
CFAG12864B-TMI-V
Shaft Encoder/Push Button
Grayhill
62A11-02-050S
CPU
Digital I/O
Freescale
MC68EC020
LEDs
CPLD
Xilinx
XC95108
FPGA
Digilent Spartan 3
XC3S1000 Core
Development Board
Counter Timer
256k x 16
SRAM
Cypress
CY7C1041B
1MB
256k x 16
Chip Enable Bus
Read Enable Bus
Write Enable Bus
Interrupt Bus
Interrupt Control
Byte Enables
Intersil
82C54
Keypad Decoder
Fairchild
MM74C922
UART
National Semiconductor
PC16552D
256k x 8
256k x 8
Flash Memory
256k x 8
Atmel
AT49F002A
1MB
256k x 8
February 28, 2006
Critical Design Review (CDR)
9
Interrupt Priorities
Level Peripheral
February 28, 2006
7
UART 1
6
Counter/timer 1
5
FPGA
4
Key pad
3
Counter/timer 2
2
UART 2
1
Shaft encoder
Critical Design Review (CDR)
10
CPLD Block Diagram
Inputs
GCK
ADDR[2:0]
IRL'[5:0]
Outputs
Priority Interrupt Controller (PIC)
FC[2:0]
AVEC'
ADDR[23:16]
SIZ[1:0]
IPL'[2:0]
CS[6:0]
DSACK'[1:0]
Address Decoder
R/W'
Bus Controller
GOE'
AS'
GWE'
DS'
BE'[3:0]
SHAFT'
DIO'[2:0]
Shaft Encoder Interface
DATA[3:0]
February 28, 2006
DIO Interface
Input/Output
Critical Design Review (CDR)
11
Wire Wrap Prototype Preview
clock/reset
CPLD
CPU
SRAM
Flash (x1)
UARTs/
drivers
Headers
for FPGA
February 28, 2006
Critical Design Review (CDR)
12
Schematic: CPU
February 28, 2006
Critical Design Review (CDR)
13
Schematic: FPGA
February 28, 2006
Critical Design Review (CDR)
14
Schematic: Memory
February 28, 2006
Critical Design Review (CDR)
15
Schematic: UARTs
February 28, 2006
Critical Design Review (CDR)
16
Schematic: Keypad
February 28, 2006
Critical Design Review (CDR)
17
Schematic: RS-232 Drivers
February 28, 2006
Critical Design Review (CDR)
18
Schematic: LEDs
February 28, 2006
Critical Design Review (CDR)
19
Schematic:
Shaft
Encoder
February 28, 2006
Critical Design Review (CDR)
20
Schematic: Reset Circuit
February 28, 2006
Critical Design Review (CDR)
21
8 Channel/12 Bit Serial ADC - AD7890
Pin
Mnemonic
1
2
3
4
5
6
7
8
9
AGND
SMODE
DGND
CEXT
CONVST'
CLK IN
SCLK
TFS'
RFS'
10
DATA OUT
11
12
DATA IN
VDD
13
MUX OUT
14
SHA IN
15
16-23
AGND
VIN1-8
24
REF OUT/ REF IN
February 28, 2006
Description
Analog Ground
Determines weather the part operates in External or Self Clocking
Digital Ground
External Capacitor. Determines the length of the internal Pulse
Conversation Start. Edge-triggered logic input
Clock Input for external clock mode
Serial Clock Input
Transmit Frame Synchronization Pulse
Receive Frame Synchronization Pulse
Serial Data Output. Sixteen bits of serial data are provided with one
leading zero.
Serial Data Input. Serial data to be loaded into the control register
Positive supply voltage (5V)
Multiplexer Output. If no external antialiasing filter is required, tied to
SHA IN
Track/Hold Input. The input to the on-chip track/hold is applied to this
pin
Analog Ground
Analog Input Channels
Voltage Reference Output/Input. (2.5V)
Critical Design Review (CDR)
22
AD7890 A/D: Interfaces
February 28, 2006
Critical Design Review (CDR)
23
AD7890 A/D: Control Register
A2
A2
A1
A1
A0
CONV STBY
Address Input. This input is the most significatn address input for the multiplexer
channel selection
Address Input. This is the 2nd most significant address input for multiplexer channel
selection.
Address Input. Least significant address input for multiplexer channel selection.
A0 When the address is written to the control register, an internal pulse is initiated, the
pulsewidth of which is determined by the value of capacitance on the CEXT pin.
When this pulse is active, it ensures the conversion process cannot be activated.
Conversion Start. Writing a 1 to this bit initiates a conversion in a similar manner to
CONV
the CONVST input.
February 28, 2006
Critical Design Review (CDR)
24
AD7890 A/D: Timing Diagram
February 28, 2006
Critical Design Review (CDR)
25
Dual 12-Bit Serial DACPORT-AD7249
Pin
Mnemonic
1
2
3
4
5
6
7
8
REFOUT
REFIN
ROFSB
VOUTB
AGND
CLR'
BIN' /COMP
DGND
9
SDIN
10
LDAC'
11
SCLK
12
SYNC'
13
14
VDD
VOUTA
15
VSS
16
ROFSA
February 28, 2006
Description
Voltage Refrence Output.
Voltage Refrence Input
Output Offset Resistor for DAC B
Analog Output Voltage of DAC B
Analog Ground
Clear, Logic Input. Active low clears both DAC's
Logic Input selects the data format to be binary or twos complement
Digital Ground
Serial Data IN, Logic Input. The 16-bit serial data word is applied to this
input
Load DAC, Logic Input. Updates both DAC outputs on falling edge of
this signal.
Serial Clock, Logic Input
Data Synchronization Pulse. Input low initalizes the internal logic in
rediness for new data word
Postive Power Supply
Analog Output Voltage of DAC A
Negative Power Wupply (used by output amplifier only). Connected to
0V for single supply operation
Output Offset Resistor for the amplifier of DAC A.
Critical Design Review (CDR)
26
AD7249 D/A Interfaces
February 28, 2006
Critical Design Review (CDR)
27
AD7890 D/A: Timing Diagram
February 28, 2006
Critical Design Review (CDR)
28
Software Architecture
• Message passing & synchronization will take
place through circular buffers (CBs)
• Interrupt service routines (ISRs) will insert
data in CBs
• Main program will setup hardware, and then
begin checking for/acting on messages in CBs
February 28, 2006
Critical Design Review (CDR)
29
Software Flow Diagram
Event
ISRs
LCD
Driver
CBs
UI
Manager
Main Program Loop
Laser
Manager
February 28, 2006
Critical Design Review (CDR)
FPGA 30
UI Mock-up
February 28, 2006
Critical Design Review (CDR)
31
Updated Schedule
February 28, 2006
Critical Design Review (CDR)
32
Milestone I Deliverables (3/21)
• FPGA
– sample/store and drive all analog signals
• Wire wrap prototype
– running boot loader & minimal system
– talk to all peripherals
• PCB
– rev 1 populated and testing
• Enclosure
– fully specified and drafted
February 28, 2006
Critical Design Review (CDR)
33
Milestone II Deliverables (4/18)
• FPGA
– can establish laser lock
– lock monitor/recovery in alpha stage
– full communication with PCB/CPU
• PCB
– rev 2 debugged and running
– ready for rev 3 if necessary
• Draft of user and technical manuals
February 28, 2006
Critical Design Review (CDR)
34
Expo Deliverables (5/4)
• System
– user can lock laser manually or by computer
– will detect and recover from broken lock
• Form factor
– enclosure is ready to be installed in client lab
• Documentation
– completed user manual and technical manual
February 28, 2006
Critical Design Review (CDR)
35
Project Responsibilities
• A.R. Hertneky
– PCB layout, FPGA development, laser system
modifications, user manual
• J.W. O’Brien
– System-level architecture/software, chassis/UI design, test
procedure design, CPLD development, technical manual
• J.T. Shin
– Analog interfaces, FPGA on-chip peripherals, peripheral
simulation, technical manual
• C.S. Wessels
– Graphical LCD driver, FPGA development, boot loader and
CPU firmware, user manual
February 28, 2006
Critical Design Review (CDR)
36
Thank you. Questions?
“I don’t know; and when I know
nothing, I usually hold my tongue.”
– Creon in Oedipus the King
February 28, 2006
Critical Design Review (CDR)
37