Laser Controller One (LC1)
A.R. Hertneky
J.W. O’Brien
J.T. Shin
C.S. Wessels
www.teamvice.net
Outline
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January 31, 2006
Background
Functionality
Block diagrams/sub-systems
Parts list/budget
Schedule/division of labor
Risk analysis
Preliminary Design Review (PDR)
2
Background
• Physics experiments often
require laser cooling
– Bose-Einstein Condensate
(BEC)
– atomic fountain clock
• Laser wavelength locked to
hyperfine transition
– analog control system
– Doppler-free saturated
absorption spectroscopy
(sat spec)
January 31, 2006
Preliminary Design Review (PDR)
3
Background
• Establishing/maintaining
lock is operator intensive
– non-intuitive
– manual system
monitoring required
• Incompatible with
automated lab equipment
January 31, 2006
Preliminary Design Review (PDR)
4
Functionality
• Auto-magically scans
atomic spectrum
• Identifies absorption
peaks
• Operator selects a
reference peak
• Configures analog
control equipment
• Lock is engaged
January 31, 2006
Preliminary Design Review (PDR)
5
Functionality
If the lock is lost
A manual operator would…
• observe erroneous
behavior in experiment
• discover broken lock
through troubleshooting
• repeat procedure to
establish lock from
scratch
January 31, 2006
Our device will…
• sense problem
• recalibrate and
reestablish the lock
• return to normal
operation within
seconds
Preliminary Design Review (PDR)
6
User Interface
• Front panel status
– LCD
• available absorption peaks
• currently selected reference peak
• time since last lock status change
– Two-color LED
• quick visual: locked/unlocked
– Keypad or dial
• choose peak and initiate automatic behavior
January 31, 2006
Preliminary Design Review (PDR)
7
Hardware Environment
Loop Filter
Laser /
Saturated Absorption
Spectroscopy
Peak Lock
Switch
Laser Controller One (LC1)
January 31, 2006
Preliminary Design Review (PDR)
8
External Connections
Spectrum Output
(Saturated Absorption
Spectroscopy)
Error Offset Monitor
(Loop Filter)
Error Monitor
(Peak Lock)
Legend
Input
Output
Laser Controller One (LC1)
Digital Interconnect
Analog Interconnect
Offset Control
(Loop Filter)
January 31, 2006
Sweep
(Loop Filter)
Switch
(Peak Lock/Loop Filter)
Preliminary Design Review (PDR)
9
Hardware Subsystems
Laser Control One (LC1)
Bus
LCD
Display
Flash
Memory
CPU
Input
Device
(Dial/
Keypad)
A/D
D/A
FPGA
Digilent Spartan 3 Development
Board
UART
January 31, 2006
Other
IP
1MB
SRAM
Preliminary Design Review (PDR)
10
Microcontroller
Freescale M683XX Microcontroller
• Clock speeds for wire wrapped prototype (8-12MHz)
and PCB integration (15-20MHz)
• Integrated Memory Controller
• LQFP 144, PQFP 132, QFP 144 Packages
January 31, 2006
Preliminary Design Review (PDR)
11
FPGA Module
Digilent Spartan-3 Starter Board
• XC3S1000 Core
• 1000k gate version
• 1 Megabyte of SRAM
• 2 Megabits of platform flash
• 50 MHz oscillator
• 3 x 40-pin I/O headers
January 31, 2006
Preliminary Design Review (PDR)
12
Optional FPGA Sub-modules
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Memory (Flash/SRAM)
Test Point Header
Serial I/O
R2R Module (8-bit DAC up to 25MHz)
Two A/D 12-bit converter chips
Two D/A 8-bit converter chips
RS232 converter
Four high bright LEDs
6-pin header to two BNC connectors
January 31, 2006
Preliminary Design Review (PDR)
13
Software/Hardware Division
CPU
•User Interface
– LCD Display
– Keypad
•Remote control
•System management
January 31, 2006
FPGA
•Laser control interaction
•Signal processing
•Application specific
functions
•System monitoring
Preliminary Design Review (PDR)
14
Estimated Cost
Component
2 Spartan3 FPGA Boards
PCB etching (2 revisions)
LCD
Power Supply
Keypad/Dial
Chassis
Flash Memory
Misc/Unforeseen Expenses
Total
January 31, 2006
Preliminary Design Review (PDR)
Price
$150.00 ea
$200.00
$300.00
$100.00
$25.00
$100.00
$50.00
$225.00
$1,300.00
15
Risks and Contingency Plan
• Risks
– unfamiliarity with DSP and control systems
– system and algorithmic complexity
– integration with automated environment a
large task
• Contingencies
– utilize classmates and instructors
– modularize and reduce interdependencies
– limit project scope
January 31, 2006
Preliminary Design Review (PDR)
16
Schedule
January 31, 2006
Preliminary Design Review (PDR)
17
Project Responsibilities
• A.R. Hertneky
– PCB layout, FPGA development, laser system
modifications
• J.W. O’Brien
– System-level software, chassis/UI design, test procedure
design
• J.T. Shin
– Analog interfaces, FPGA on-chip peripherals, peripheral
simulation
• C.S. Wessels
– Graphical LCD driver, FPGA development, boot loader and
CPU firmware
January 31, 2006
Preliminary Design Review (PDR)
18
Thank you. Questions?
“I don’t know; and when I know
nothing, I usually hold my tongue.”
– Creon in Oedipus the King
January 31, 2006
Preliminary Design Review (PDR)
19