Capstone CDR
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Group: AquaLung
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Mir Minhaz Ali
Wilfredo Oteromatos
Greg Newcomb
Robin Elliott
Presentation Overview
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Minhaz
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Hardware Overview
Bill of Materials
Fiber and Camera Assembly
CCD and Connection
Freddy
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Greg
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USB Interface
Easy USB Chip
Connection
Device Driver to
handle USB
Driver to GUI
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CCD Parallel Interface
CCD Serial Interface
Functional Block Diagram
Analog to Digital
FPGA Connection
Robin
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Software Functionality
Software Flowchart
AquaImage
Program Launch and Menu
Time Chart
Milestone Tasks
Complete Hardware Overview
12.5 MHz
CLOCK
1M long Optical Fiber
Camera
GUI
(Graphics User
Interface)
2 pin Analog
output
CCD Image
Sensor TC237B
680 x 500 Pixel
Device
Driver
Clock Driver &
CCD Logic
2 bits Easy USB CHIP
FT245BM
6 MHz Crystal
Resonator
ADC
8 bit
AD7825
Spartan 3
FPGA
Bill of Materials (BOM)
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1 meter long optical fiber with built in camera
Ti CCD Sensor (TC237B)
Hi speed clock driver for CCD (EL7202C)
Octal buffer for CCD serial driver ( 74ACT240NS)
Spartan 3 FPGA with 1M-byte of Fast Asynchronous
USB Chip (FT245BM)
USB Cable and connector
8bits ADC(AD7825)
EPROM (93LC46B-I/P)
Clock (12.5 MHz) (CSTLS6M00G53Z-B0)
Crystal Resonator (6MHz)
Variable output voltage regulator (PTN7800)
Other hardware, Capacitor and resistor.
Optical Fiber and Camera
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7000 pieces of fiber inside
creating full color image.
0.5mm diameter glass fiber
imaging bundle enables
scope to bend around .
Very inexpensive(120$) for
1M long fiber with camera
2 Xeon light bulbs to
illuminate the image.
1M long Optical Fiber
Camera Tip
Eye Piece
Charge Couple Device (CCD)
 0.34M Pixels Per Field
 658(H) x 469(v) Active Elements
 Multimode readout capability
 Progressive Scan
 Duel Line readout
 Image Area line Summing
 Low Dark Current
 7.4µm x 7.4µm pixel size
12.5 MHz Clock
Module 1: CCD
+15V
2.7K
R
R19
2K
Q1
1R1001
R16
5.2K
CCD_ODB
R12
10
1.5K
U29A
R10
1
2
Q2
1R1001
3.3K
R18
3.3K
74HC14
ODB DRIVER
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Four Functional Blocks:
 Image sensing area
 image storage area
 serial register gate
 low noise signal processing amplifier block
The storage area and serial gate are used to
transfer charge line by line from storage area
into serial register
After transfer the pixel are clocked out and
sensed by charged detection node.
TC237
CCD_IA G1
12
CCD_SAG
11
IAG1
ODB
SA G11
IAG2
10
9
8
7
SA G10
SUB9
SUB3
A DB
SRG
OUT1
RST
OUT2
1
2
CCD_IA G2
3
+12V
4
5
CCD_OUT1
6
CCD_OUT2
Module 2: CCD Parallel interface
+5V
Drivers:
2
4
E2
1
E1
R24
3.9k
6
C1
IAG1_CLK
5
B2
C2
B1
R25
1.2k
3

HN1A 01F
R23
1.8k
R26
1.8K
4
B2
HN1A 01F
U35
CCD_IA G1
8
7
6
CCD_IA G2
5
NC
NC
OUT A IN A
V+
GND
OUT B IN B
IAG2_CLK
5
C2
B1
C1
2
E2
E1
1
CCD Driver
3
1
2
3
R22
1.8K
4
B1
B2
6
C1
2
U36
CCD_SAG
8
7
6
5
NC
NC
OUT A IN A
V+
GND
OUT B IN B
EL7202C
1
2
3
R20
C2
1.8k
E2
-10V
E1
EL7202C
4
1
R21
+2v
3
EL7202C (non-inverting)
 Image Area Gate (IAG)
 Storage Area Gate (SAG)
- Input: CLK(12.5MHz)
 Output: Logic signals to
control Image and
Storage Areas.
 Purpose: Activates the
Image Area and Opens
the Storage Area.
R11
1.8K
6
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HN1A 01F
4
1.8k
PARALLEL DRIVER
5
SA G_CLK
Module 3 : CCD Serial Driver
C14 +2v
0
C
+5V
C14
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Progressive Scan Mode
Two register available for
high speed data transfer
Drives the Serial Register
Gate (SRG)
12.5Mhz clk. Signal.
74ACT240 Octal buffer
Allows data to be pulled
from the serial registers.
Input: CLK (12.5MHz)
Output: Driving signal.
560
10k
0
C
74A CT240
1
2
3
4
5
6
7
8
9
10
SRG_CLK
SRT_CLK
1OE
1A 1
2Y 4
1A 2
2Y 3
1A 3
2Y 2
1A 4
2Y 1
GND
V CC
2OE
1Y 1
2A 4
1Y 2
2A 3
1Y 3
2A 2
1Y 4
2A 1
20
19
18
17
16
15
14
13
12
11
2.2k
0.1u
R52
4.7
CCD_SRG
4.7
0.1u
10R
C
0
560
10K
-10 v
+2v
560
0
2.2k
10k
0.1u
R53
4.7
4.7
CCD_RST
0.1u
10
R
C
Octal Buffer
560
-10 v
C14
C
0
10K
Functional Block Diagram
Parallel Driver
Serial Driver
Analog to Digital Converter
U30
CCD_OUT1
15
14 VIN1
13 VIN2
12 VIN3
VIN4
ADC_PD
5V
18
10uF
C8
0.1uF
VDD
AGND
2.5v
19
CCD_OUT2
D GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
17
VREFIN/OUT EOC
RD
CONVST
11
PD
CS
A1
16
VMID
A0
7
 AD 7825
 2Msps
 420nS conversion time
 PWR Dissipation 36mW
 Input: 2 AC signals from
CCD out1 and 2.
 Output: 8 Bits Parallel to
FPGA.
 Purpose: Conversion
from CCD analog output to
FPGA A-2 header.
0
3
2
1
24
23
22
21
20
8
6
4
5
9
10
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC[0:7]
ADC_EOC
ADC_RD
ADC_CONVST
ADC_CS
ADC_A1
ADC_A0
Module 4 : Spartan III FPGA
A DC_EOC
A DC_RD
A DC_CONV ST
A DC_CS
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Function: Data timing issues
resolutions and sampling.
USB_RXF#
USB[0..7]
USB_TXE#
USB[0:7]
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7
USB_WR
USB_RD#
A DC_A0
A DC_A1
A DC0
A DC1
A DC2
A DC3
A DC4
A DC5
A DC6
A DC7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
V U(+5V )
V cco(+3.3V )
A DR0
DB0
A DR1
DB1
A DR2
DB2
A DR3
DB3
A DR4
DB4
A DR5
DB5
WE
DB6
OE
DB7
CSA
LSBCLK
MA1 -DB0
MA1 -DB1
MA1 -DB2
MA1 -DB3
MA1 -DB4
MA1 -DB5
MA1 -DB6
MA1 -DB7
MA1 -A STB
MA1 -DSTB
MA1 -WRITE
MA1 -WA IT
MA1 -RESET
MA1 -INT
JTA G Isolation
TMS
TCK
TDO-ROM
TDO-A
Spartan 3 Boar d
A2 EXPANSION
A1 EXPANSION
A DC[0:7]
USB_PWREN#
SPARTAN III
B1 EXPANSION
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A DC_PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
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FPGA: Spartan III
Inputs:
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Data from ADC
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End of Conversion
(EOC) signal from ADC.
Outputs:
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8 bits data to USB
interface
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Control signals to:
 ADC
 USB (interface)
 CCD
GND
VU(+5V)
Vcco(+3.3V)
PA-IO1
PA-IO2
PA-IO3
PA-IO4
PA-IO5
PA-IO6
PA-IO7
PA-IO8
PA-IO9
PA-IO10
PA-IO11
PA-IO12
PA-IO13
PA-IO14
PA-IO15
PA-IO16
PA-IO17
PA-IO18
MA2-DB0
MA2-DB1
MA2-DB2
MA2-DB3
MA2-DB4
MA2-DB5
MA2-DB6
MA2-DB7
MA2-ASTB
MA2-DSTB
MA2-WRITE
MA2-WAIT
MA2-RESET
MA2-INT/GCK4
PROG-B
DONE
INIT
CCLK
DIN

GND
V U(+5V )
V cco(+3.3V )
PB-A DR0
PB-DB0
PB-A DR1
PB-DB1
PB-A DR2
PB-DB2
PB-A DR3
PB-DB3
PB-A DR4
PB-DB4
PB-A DR5
PB-DB5
PB-WE
PB-DB6
PB-OE
PB-DB7
PB-CS
PB-CLK
MB1-DB0
MB1-DB1
MB1-DB2
MB1-DB3
MB1-DB4
MB1-DB5
MB1-DB6
MB1-DB7
MB1-A STB
MB1-DSTB
MB1-WRITE
MB1-WAIT
MB1-RESET
MB1-INT
PROG- B
DONE
INIT
CCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Module 5 : USB Interface
27R
RESET
R7
1.5K
5
4
R9
1M
27
28
6 MHz Resonator
32
1
2
RSTOUT#
RESET#
D0
D1
D2
D3
D4
D5
D6
D7
USB0
USB1
USB2
USB3
USB4
USB5
USB6
USB7
25
24
23
22
21
20
19
18
USB_D0-D7
XTIN
XTOUT
FT245BM
EECS
EESK
SI/WU
EEDA TA
TEST
RD#
WR
TXE#
RXF#
PWREN#
16
15
14
12
USB_RD#
USB_WR
11
10
USB_TXE#
C6
V CC_3V??
USB_RXF#
29
9
17
31
3V 3OUT
USBDM
USBDP
USB[0..7]
R6
10K
1
6
8
7
U26
13
R5
4.7K
30
3
26
C1
C
R3
AGND
GND
GND
27R
USB B CONNECTOR
V CC_5V
C5
C V CC_3V
R8
470
VCCIO
C2
C
AVCC
VCC1
VCC
R4
1A
2A
3A
4A
C7
C
USB_PWREN#
U17
3
2
1
8
V CC_BAR
C3
C
DI
DO
4
CLK
CS
V CC
R1
R2
93C56B
V CC_BAR
2.2K
C4
C 10K
Easy USB chip
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FIFO Interface between FPGA and USB cable
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Entire USB protocol handled on-chip
Simple to interface with FPGA
USB 2.0 Compatible
Cheap $$$
EEPROM optional (93LC46B)
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Bidirectional
Transfer data rate 1M byte/sec
Default setting or program with EEPROM
6 MHz Timing Chip required (CSTLS6M00GS32-B0)

With 8x clock multiplier, works at 48 MHz
Easy USB - FT245BM
Single Chip USB <=> parallel FIFO bi-directional data transfer
EEPROM
Interface
Clock
Check
TXE# Low
Control
Easy USB - FT245BM
Single Chip USB <=> parallel FIFO bi-directional data transfer
EEPROM
Interface
Clock
Input
8 pin digital
signal from
FPGA (D0-D7)
Write when
TXE# Low
Control
Easy USB - FT245BM
Single Chip USB <=> parallel FIFO bi-directional data transfer
EEPROM
Interface
Clock
Input
8 pin digital
signal from
FPGA (D0-D7)
Sending over
USB cable
Output
2 pin signal to
USB Cable
TXE# is
Raised
(USBDP & USBDM)
Control
Easy USB - FT245BM
Single Chip USB <=> parallel FIFO bi-directional data transfer
Physical Connection to USB pins
To PC
From FPGA
Pin
FPGA
Signal Name
1
+5 V
VBUS
2
USBDM
Data Minus
3
USBDP
Data Plus
4
GND
GND
USB Cable
•USB 2.0 (“Full Speed”)
•Uses NRZI (Non Return to Zero Invert) encoding
•Not our problem!
Device Driver to Handle USB
 Provided by FTDI free
 Version for Windows XP
 Will allow for plug & play
Driver to GUI Handoff
Notice
Interrupt
Open
File 1
Driver to GUI Handoff
Save 1st
picture
Driver to GUI Handoff
Notice File 1
is Full
Picture 1
saved
Close
File 1
Open File 1
Driver to GUI Handoff
Read Data
from File 1
Save next
picture
Driver to GUI Handoff
Finish Getting
Data
Save next
picture
Close File 1
Send image
to monitor
Driver to GUI Handoff
Open File 2
Save next
picture
Get Data
Software Functionality
Launch
Program
Display
“Moving” Image
Pick Up
Event
Y
Option
Buttons
•Zoom
•Color Contrast
•Pause/Unpause
•Auto Save
•OpenSaved Image
Data?
N
Exit Program
Display Still Image
Or None at all
Pick Up
Event
Software Flow Chart
Display “Moving” Image
Launch Program
•initialize software
•look for device driver
?
Device
Driver
Found
?
N
Display
Driver
Error
•Patient name & ID
•Zoom/Contrast toggle
•Zoom Level (if zoomed)
Y
Y
?
Data
From
Driver
?
N
Y
?
Moving
Image
?
N
Display
No Signal
?
Open
Y
Saved
Image
?
N
Exit Program
•Close all files
?
Y
?
Valid
Mouse
Event
?
N
Image
Update
Ready
?
N
Y
?
Determine
Event
?
Auto Save Image
•Name, ID, date, time
Zoom Toggle
•Turn off Color Contrast
Color Contrast Toggle
•Turn off Zoom
Unpause the Image
Pause Current Image
Open Saved Image
Display Still Image
•Patient name & ID
•Zoom/Contrast toggle
•Zoom Level (if zoomed)
?
Valid
Mouse
Event
?
Y
N
?
Determine
Event
?
Exit
•Confirm
About AquaImage
This is the “About” box seen in all Windows applications.
Program Launch

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Screen seen at start-up.
Circled items are customized features.
Menu Bar

Menu features included in AquaImage.
Time Chart
Milestone Tasks

Milestone 1
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GUI Complete
Device Driver Implemented/Not Tested
Prototyping and Modular Testing
Milestone 2
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Static Interface Working
Prototyping and Testing Complete
PCB In House
Questions ??