Drag and Atmospheric
Neutral Density Explorer
(DANDE)
Command and Data Handling
(CDH)
Preliminary Design Review
September 13th, 2007
Brandon Gilles (EE)
James Gorman (ECE)
Eric McIntyre (ECE)
Gabe Thatcher (EE)
Program Schedule
Spring
07
SCR
Detailed Schedule
Summer
07
♦
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PDR
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EDU & Vibe Test
CDR
Electrically equivalent
satellite on a lab bench
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Proto-Qualification Unit at 80%, Verification at 90%
Proto Qualification Testing
♦
♦
Proto-Qualification Unit at 100%, Verification at 100%, as-built documentation
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Fall
08
♦
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Proto Qualification Build
FCR
Summer
08
Design Documentation, Analysis,
Breadboard Verification
EDU, Analysis, Flat Sat, Verification at 50%
PQR
Spring
08
Concept Design, Requirements Definition
Prelim. Design &
Breadboard
Flat-sat Build
Fall
07
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Responsibilities of CDH
• Monitor and manage health of satellite.
• Record and pre-process data from science
subsystems.
• Provide command and control functionality.
• Manage the operating modes of satellite.
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Science
Safe
Separation
Spin-up
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Scope of Implementation
• Developing the Flat Satellite version of the CDH system
– Full Hardware and software functionality
– Boards do not have size constraints
– Standard practice for satellite development
• Size constrained boards come after Flat-Sat completion
• The CDH portion of the
DANDE Flat-Sat is the
scope of this capstone
project
Here is the Flat-Sat of the
Naval Academy’s ‘Pcsat’
http://web.usna.navy.mil/~bruninga/pcsat.html
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Outline of Approach
• Distributed architecture
– Main “Flight Computer”
• 32-bit Atmel AVR
• Linux 2.6 Kernel
– Subsystem microcontrollers
• 8-bit Atmel AVRs
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CDH Block Diagram
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Subsystem and Instrument Interfaces
• Interfaces to the satellite are all through the subsystem
microcontrollers
– Subsystem microcontrollers are responsible for collecting and buffering
salient science and health data from the subsystem instruments.
– The Flight Computer polls the subsystem microcontrollers periodically
for data
• Extent of Subsystem Development
– The CDH team shall provide an AVR reference design to the subsystem
designer
• AVR hardware reference design
• AVR driver package (in C)
– Beyond this reference design, no further subsystem development is in
the scope of this project
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Division of Labor
• Brandon Gilles
• Eric McIntyre
– Project Manager
– REA - 32-bit Hardware
– REA - Linux Kernel
– REA - 32-bit Software
– Architecture
– Analysis and Design
– Implementation
• James Gorman
– REA - 8-bit Hardware and Software
Reference Design
– REA - Watch Dog and Long Dog
Circuitry
– 32-bit Hardware
• Gabriel Thatcher
– REA - Memory Voting Logic
– REA - Subsystem Hardware
Interfacing
• Across the board
– 32-bit Software Analysis, Design and Implementation
REA - Responsible Engineering Authority
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Implementation, Schedules, and Risk Assessment
• High-Level Systems Software
• Flight Computer Hardware and Drivers
• Subsystem Computer Hardware and Drivers
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High-Level Systems Software
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Implementation
The following methods will ensure successful
implementation:
• Adherence to the rational process
• Detailed documentation during all workflows including
requirements, analysis, and design
• Object-oriented design for applicable systems
• Coding during the implementation workflow will be
performed in development environments provided by
the chip manufacturer.
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Schedule
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Schedule
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Risk Assessment
• Risk: Failure to define requirements.
– Consequences: Interfaces may not be clear or specified to
users. Software may require rework, patches, or be unusable.
– Mitigation: Following the rational process, meeting regularly
with users, documenting, and holding regular reviews with
the other subsystem leads
• Risk: Failure to build compatible software with specified
hardware.
– Consequences: Software will be unusable.
– Mitigation: When defining implementation iterations each
build will be tested on target hardware, which is available, to
be considered usable.
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Flight Computer Hardware
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Flight Computer: Implementation
• The flight computer needs to be able to process large
amounts of data
• It also needs to have support for high level code.
– This is so the other systems can write algorithms in an easy to use
object-oriented language
– This is also so that there is protected memory so a bug in one
piece of code does not wipe out everything else
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Flight Computer: Implementation
• The AVR32 processor will be used
– This is a 32 bit RISC processor
– High performance
• Pipelined with superscalar out-of-order execution
• Instruction and data cache
– Internal DRAM controller
– Fully supported in the Linux 2.6 kernel
– Extensive integrated peripherals
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Flight Computer: Implementation
• The Linux operating system needs to be loaded out of a non-volatile
memory which can be rewritten during flight
– This can either be a parallel access NAND Flash chip or a SPI NAND Flash device
• 64 MB of non-volatile memory is required for science mission data
– This will be in the form of an SD card
• This system requires RAM for the same reasons a PC requires RAM
– Needs a place to execute code out of
– Needs a place to store variables
• Either SRAM or DRAM will be used
– Decision will be made based on amount of RAM required and ease of
implementation
– Other factors such as radiation tolerance may affect decision
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Flight Computer: Risk Assessment
• Make or Buy Decision for flight computer:
– Make:
• Getting a processor with external memory running is a very
difficult task
• In addition the processor is only available in a 256 pin BGA
package
• Processor speed requires board design with signal integrity in
mind (150MHz max)
– Buy:
• Prevents Radiation Mitigation Techniques
– Memory Voting Circuit
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Subsystems Hardware and Drivers
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Implementation
• Most of the subsystems need a way to interface their
hardware to the central processor/ data bus
• An Atmel AVR 8-bit microcontroller will be used
• The microcontroller requires little hardware support for
external circuitry
• Many I/O pins and peripheral hardware available for
interfacing to subsystems
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Implementation
• Each subsystem will need to be able to write their own
software to interface to their hardware
• This requires that low level drive be written to handle the
following operations:
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Manipulate digital I/O pins
Communicate using the UART or SPI module
Sample analog signals using the internal converter
Use the timers to sample data at the proper rate
React to commands from the central processor
Transmit data back to the main computer
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Flight Computer: Risk Assessment
• The hardware system involves very few risks
• The software risks involves writing the software in an
extensible and easy to use way
– Ther e is no protected memory so all other code can cause faults in the system
– The proper libraries may not be provided.
• Libraries Currently Planned
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Real Time Clock
Timer
UART
SPI
Analog Input
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Schedule
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Backup Slides
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DANDE Background Information
• Drag and Atmospheric Neutral Density Explorer
– A Low-Cost Small-Satellite Program for Neutral Density, Wind, and Composition
Research with Applications Space Weather Models
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DANDE measures atmospheric density variations
DANDE will also provide coefficient of drag data
DANDE weighs 110 lb (50 kg), and is 18” (0.46 m) in diameter.
DANDE spins at 10 RPM to provide gyroscopic stability for instrument pointing, and ease of
attitude determination and control.
– DANDE uses the aluminum shell halves of its structure as a receive antenna, and a piano
wire embedded in Delrin as a transmit antenna.
– DANDE will use a novel aerobraking mechanism to quickly descend from a common 310370 miles (500-600 km) orbit to its science orbit at 220 miles (350 km)
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Exploded View
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Communications Analysis
•
Data volume:
bits/sample
NMS (Neutral Mass Spectrometer)
ACC (Accelerometer)
PRS (Pressure Sensor)
Health and Status (Engineering) data
•
sample rate
samples / day
bits / day
0.01667 Hz
1,440
6,036,480 bits
0.2 Hz
17,280
552,960 bits
0.2 Hz
17,280
552,960 bits
0.00028 Hz
24
98,304 bits
Communications passes:
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4,192 bits
32 bits
32 bits
4,096 bits
TOTAL DATA / DAY
Average pass length: 247 seconds ( @ start of mission)
~2 passes per day at Boulder CO (40°N)
At 9600bps, we can downlink ~1,968,000 bits per pass
Takes ~4 passes to downlink one day’s data
Communications trade studies (in-progress):
– Adding ground stations
• Space Grant Colleges in Hawaii, Puerto Rico
• Can downlink all data using 3 ground stations
– Microwave (2.4GHz) communications equipment
• Currently increasing TRL at home institution
– Potential use of local high-gain antenna facility
• 2 x 60’ steerable dishes (http://www.deep-space.org/)
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7,240,704 bits
Functional Block Diagram
Wiring Harness
FOV
360°
EPS
Photovoltaics 30W
Inhibit
x4
Regulation
Control
Lightband assy.
SEP
RAM TBD
Control
CPU
AVR32
Satellite Sep Plane (SSP)
Instrument
Instrument
FOV
32° x 1°
Control
TNC
Sensors
Control
Mag (3axis)
Torque
rod A
Instrument
FOV
32° x 1°
Horizon
Crossing
Sensor
Rx
2m
9.6kbps
NMS
Torque
rod A
ADC
Tx
70cm
38.4kbps
ADCS
Coatings, Insulation
Horizon
Crossing
Sensor
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Rx Ant
FOV
90°
Tx Ant
FOV
90°
Control
Comm
SSD
TBD
Control
COM
OS
Science
THM
Mech2
ACC
Scheduling
RTC
Mech1
SFT
Serial I/O
ABS
Inhibit
Battery A
14.4V
4AH
Battery
B
14.4V
4AH
I2C I/O
LV electrical
interface
x4
CDH
FOV 2° Laboratory
FOV 2°
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