GFX-One Guitar
Processor
Team Carpal Tunnel
October 6th 2005
Capstone Fall 2005
Team Members




Mason Stone
Henock Negassa
Tony Sawyer
Nael Cassier
Capstone Fall 2005
Refresher: What is GFX-One?


GFX-One is a digital audio effects
processor.
It is designed specifically for use with
guitar, but can process any monaural
analog audio input.
Capstone Fall 2005
Functional Block Diagram
Input
Box/User Interface
Output
GFX-One
Push Buttons
LCD
Mono to Amp.
EMIF
A/D
16-bit,
44.1KHz
Guitar or
any other
analog
input
EPROM
I 2C
McBSP0
FPGA
Spartan 3
CLOCK
20MHz
Audio
Amplifier
DSP
Starter Kit
Stereo
Headphone
McBSP1
2
I C
Stereo D/A
16-bit,
44.1KHz
Stereo
MP3
player
Capstone Fall 2005
2 analog
Mixer
Mono Speaker
DSP Implementation


Will implement DSP using a Texas
Instruments TMS3206713 Development
Board
The board allows for easy configuration
and testing of the processor functionality
and effects routines
Capstone Fall 2005
Development Board Interface

The development board will be accessible to the
rest of the system through an 80 pin memory
expansion port

The processor will be accessible to the
programmer through a JTAG USB port

The on-board codec (ADCs, DACs, mixer) will be
bypassed in favor of components that we will lay
out and implement
Capstone Fall 2005
DSP Core Software

Code Composer Studio will
be the software package
used to program the
processor

The effects algorithms as
well as all other code will
be written in C++

Using the development
board will allow for more
effective debugging of our
design code
Capstone Fall 2005
DSP Development Board
Capstone Fall 2005
DSP Development Board
Capstone Fall 2005
Communication with FPGA

Memory Expansion Connector
– External Memory Interface (EMIF)
 16 bits data
 6 bits address
 Chip enable

Peripheral Expansion Connector
– 2 Multi-channel Binary Ports (McBSP)
 Accessed by reassigning multiplexer on-board
 7 pins per port—don’t need all of them

3.3V Input/Output buffers
Capstone Fall 2005
FPGA: Xilinx XC3S400

20 MHz oscillator input
– Digital Clock Manager (DCM) provides phase-locked
clock inputs to A/D and D/A

Communication with DSP board
– EMIF
– McBSP

Data converters (A/D, D/A)
– Data format can be converted from I2C to McBSP
User interface to LCD and Buttons
 JTAG Interface

Capstone Fall 2005
FPGA: Xilinx XC3S400
Capstone Fall 2005
Schematic version of
our FPGA
Capstone Fall 2005
Serial Interface
Capstone Fall 2005
Mixed Signal Interface
Signal from Analog
amplifier is fed to A/D
Converter.
 Converts input
voltage from analog
signal in to Digital bit
 Synchronized with
44.1KHz Clock
 16 Bit digital signal

MAX 195
Capstone Fall 2005
A/D schematic
Capstone Fall 2005
Mixed Signal Interface

Digital to Analog (D/A)
conversion methods
– Data is fed from DSP to
D/A Converter.
– Standard D/A converters
translate an array of digital
bits into a bias voltage
– Synchronized with 44.1KHz
Clock
– 16 Bit digital signal
– I2c interface
AD 1866
Capstone Fall 2005
D/A Schematic
Capstone Fall 2005
Analog Signal Mixer



We are going to use
voltage adder (summer)
Op Amp circuit as analog
signal mixer
A good recording mixer
lets you route a variety of
input signals and combine
them into one signal.
For a potential Add-on
output signal from MP3
player will mix with signal
from D/A converter
Capstone Fall 2005
Audio Amplifier




Analog signal from Mixer is
going to be amplified and
routed to speaker
Amplifier is transistor based
stereo audio power amplifier
–0.3 V to 6 V supply
Capstone Fall 2005
Power


Regulated 3.3 and 2.5 V power buses from 9V DC
adapter.
5V
– LCD
– D/A converter
– A/D converter +5 & -5

3.3 V
–
–
–
–

Compact Flash
Audio Amplifier
Data lines to and from FPGA
FPGA VCC
2.5 V
– FPGA JTAG
Capstone Fall 2005
User Interface
Power
In
Out
Mix
EQ
I/O
1
2
3
4
5
6
Bypass
Capstone Fall 2005
LCD Code
Capstone Fall 2005
LCD Code
Capstone Fall 2005
User Interface Schematic
Capstone Fall 2005
Project Schedule
Capstone Fall 2005
Division of Labor
Name
Nael Cassier
Task
Mason Stone
User Interface/FPGA
Configuration
DSP Integration
Tony Sawyer
DSP Core Implementation
Henock Negassa A/D Component Integration
Capstone Fall 2005
Hardware List
Component
Part Number
Manufacturer
Quantity
Ordered?
FPGA
XC3S400-TQ144
Xilinx
2
Yes
DSP Starter Kit
TMS320C6713DSK
T.I.
1
Yes
EPROM
XCF02V020C
Xilinx
2
Yes
CLOCK
EC1100HSTS-20.000M
ECLIPTEK
2
Yes
A/D
MAX195BEPE
MAXIM
2
Yes
D/A
AD1866N
Analog Devices
2
Yes
Audio Amplifier
TPA6021A4
T.I.
2
Yes
3.3V Regulator
LT1764AET-3.3
Linear Technologies
2
Yes
-5.0V Regulator
Radio Shack
Radio Shack
2
Yes
2.5V Regulator
Radio Shack
Radio Shack
2
Yes
5.0V Regulator
LM7805
FairChild
2
Yes
Level Shifter
SN74LVC4245ADWRE4
T.I.
8
Yes
LCD
CFAH1602A
CrystalFontz
2
Yes
Push Buttons
ZF-2U-OA-C
ITT
16
Yes
On/Off Button
ZF-2U-EE-C
ITT
3
Yes
Audio Jacks
JB Saunders
JB Saunders
6
Yes
Power Supply
Adapter
JB Saunders
JB Saunders
1
Yes
Passive Components
JB Saunders
JB Saunders
N/A
No
Capstone Fall 2005
Milestone Deliverables
Milestone 1
Milestone 2
Design Schematics
Solder PCB
Completed
Board Layout Completed PCB Debug Completed
PCB Ordered and
Delivered
LCD Code Completed
DSP Code Completed
(Alpha)
FPGA Code Completed
(Alpha)
Capstone Fall 2005
Questions?
Capstone Fall 2005