Lecture 22 OUTLINE The MOSFET (cont’d) • Velocity saturation • Short channel effect • MOSFET scaling approaches Reading: Pierret 19.1; Hu 7.1, 7.3 MOSFET Scaling • MOSFETs have been steadily miniaturized over time – 1970s: ~ 10 mm – Today: ~30 nm • Reasons: – Improved circuit operating speed – Increased device density --> lower cost per function EE130/230M Spring 2013 Lecture 22, Slide 2 Benefit of Transistor Scaling As MOSFET lateral dimensions (e.g. channel length L) are reduced: • IDsat increases decreased effective “R” • gate and junction areas decrease decreased load “C” faster charging/discharging (i.e. td is decreased) EE130/230M Spring 2013 Lecture 22, Slide 3 Velocity Saturation Velocity saturation limits IDsat in sub-micron MOSFETS Simple model: v m 1 sat v vsat for < for sat Esat is the electric field at velocity saturation: vsat EE130/230M Spring 2013 sat 8 106 cm/s for electr ons in Si 6 6 10 cm/s for holes in Si Lecture 22, Slide 4 sat 2vsat m MOSFET I-V with Velocity Saturation In the linear region: W m Coxe meff VGS VT VDS VDS L 2 ID VDS 1 sat L long channel I D ID VDS 1 sat L EE130/230M Spring 2013 Lecture 22, Slide 5 Drain Saturation Voltage, VDsat • If satL >> VGS-VT then the MOSFET is considered “long-channel”. This condition can be satisfied when – L is large, or – VGS is close to VT 1 VDsat EE130/230M Spring 2013 m 1 VGS VT sat L Lecture 22, Slide 6 sat 2vsat m Example: Drain Saturation Voltage Question: For VGS = 1.8 V, find VDsat for an NMOSFET with Toxe = 3 nm, VT = 0.25 V, and WT = 45 nm, if L = (a) 10 mm, (b) 1 mm, (c) 0.1 mm (d) 0.05 mm Solution: From VGS , VT and Toxe, meff is 200 cm2V-1s-1. Esat= 2vsat / meff = 8 104 V/cm m = 1 + 3Toxe/WT = 1.2 VDsat EE130/230M Spring 2013 m 1 VGS VT sat L Lecture 22, Slide 7 1 (a) L = 10 mm: VDsat= (1/1.3V + 1/80V)-1 = 1.3 V (b) L = 1 mm: VDsat= (1/1.3V + 1/8V)-1 = 1.1 V (c) L = 0.1 mm: VDsat= (1/1.3V + 1/.8V)-1 = 0.5 V (d) L = 0.05 mm: VDsat= (1/1.3V + 1/.4V)-1 = 0.3 V EE130/230M Spring 2013 Lecture 22, Slide 8 IDsat with Velocity Saturation Substituting VDsat for VDS in the linear-region ID equation gives I Dsat W 2 Coxe meff VGS VT long channel I Dsat 2 mL VGS VT VGS VT 1 1 m sat L m sat L For very short L: I Dsat sat L VGS VT / m W satCoxe m eff VGS VT WvsatCoxe VGS VT 2 • IDsat is proportional to VGS–VT rather than (VGS – VT)2 • IDsat is not dependent on L EE130/230M Spring 2013 Lecture 22, Slide 9 V gs = 1.0V 0.0 Short- vs. Long-Channel NMOSFET V (V) 0 1 2 2.5 ds 0.4 L = 0.15 mm Vt = 0.4 V I ds (mA/mm) L = 2.0 mm V gs = 2.5V Vgs = 2.5V Vt = 0.7 V 0.3 0.02 Ids (mA/mm) (a) 0.03 (b) V gs = 2.0V 0.2 V gs = 1.5V 0.1 Vgs = 2.0V 0.01 Vgs = 1.5V V gs = 1.0V Vgs = 1.0V 0.0 0.0 0 1 2 2.5 V ds (V) Short-channel NMOSFET: 0.03 Vto 2.5V-V rather than (V -V )2 L =is 2.0proportional mm gs =V • IDsat GS Tn GS Tn Vt = 0.7 V • VDsat is lower than for long-channel MOSFET 0.02 • Channel-length modulation is apparent /mm) (b) Vds (V) EE130/230M Spring 2013 Vgs = 2.0V Lecture 22, Slide 10 Velocity Overshoot • When L is comparable to or less than the mean free path, some of the electrons travel through the channel without experiencing a single scattering event projectile-like motion (“ballistic transport”) The average velocity of carriers exceeds vsat e.g. 35% for L = 0.12 mm NMOSFET Effectively, vsat and sat increase when L is very small EE130/230M Spring 2013 Lecture 22, Slide 11 The Short Channel Effect (SCE) “VT roll-off” • |VT| decreases with L – Effect is exacerbated by high values of |VDS| • This effect is undesirable (i.e. we want to minimize it!) because circuit designers would like VT to be invariant with transistor dimensions and bias condition EE130/230M Spring 2013 Lecture 22, Slide 12 Qualitative Explanation of SCE • Before an inversion layer forms beneath the gate, the surface of the Si underneath the gate must be depleted (to a depth WT) • The source & drain pn junctions assist in depleting the Si underneath the gate – Portions of the depletion charge in the channel region are balanced by charge in S/D regions, rather than by charge on the gate Less gate charge is required to invert the semiconductor surface (i.e. |VT| decreases) EE130/230M Spring 2013 Lecture 22, Slide 13 The smaller L is, the greater the percentage of depletion charge balanced by the S/D pn junctions: depletion charge supported by gate (simplified analysis) VG n+ n+ p D S D Depletion charge supported by S/D Depletion charge supported by S/D EE130/230M Spring 2013 depletion region Small L: Large L: S rj Lecture 22, Slide 14 First-Order Analysis of SCE • The gate supports the depletion charge in the trapezoidal region. This is smaller than the rectangular depletion region underneath the gate, by the factor L L 1 2L WT • This is the factor by which the depletion charge Qdep is reduced from the ideal • One can deduce from simple geometric analysis that EE130/230M Spring 2013 Lecture 22, Slide 15 2WT L L 2 r j 1 1 rj VT Roll-Off: First-Order Model VT VT (longchannel) qN AWT rj 2WT VT 1 1 Coxe L rj Minimize VT by • reducing Toxe • reducing rj • increasing NA (trade-offs: degraded meff, m) MOSFET vertical dimensions should be scaled along with horizontal dimensions! EE130/230M Spring 2013 Lecture 22, Slide 16 MOSFET Scaling: Constant-Field Approach • MOSFET dimensions and the operating voltage (VDD) each are scaled by the same factor k>1, so that the electric field remains unchanged. EE130/230M Spring 2013 Lecture 22, Slide 17 Constant-Field Scaling Benefits • Circuit speed improves by k • Power dissipation per function is reduced by k2 EE130/230M Spring 2013 Lecture 22, Slide 18 • Since VT cannot be scaled down aggressively, the operating voltage (VDD) has not been scaled down in proportion to the MOSFET channel length: EE130/230M Spring 2013 Lecture 22, Slide 19 MOSFET Scaling: Generalized Approach • Electric field intensity increases by a factor a>1 • Nbody must be scaled up by a to suppress short-channel effects • Reliability and power density are issues EE130/230M Spring 2013 Lecture 22, Slide 20