Lecture #23 Synthesis
Next week: Converting gates into
circuits
10/25/2004
EE 42 fall 2004 lecture 23
1
Topics
Today:
• Minimization versus other goals
(Performance, cost, ….)
• Important properties of logic expressions
• DeMorgan’s Theorem
• Sum-of-Products Implementation
10/25/2004
EE 42 fall 2004 lecture 23
2
Some Important Logical Functions
• “AND”
A B
• “OR”
AB
• “INVERT” or “NOT”
not A (or A )
• “not AND” = NAND
AB
• “not OR” = NOR
A B
• exclusive OR = XOR
A  B (only1 when A, B differ)
i.e., A  B except A  B
AB (only0 whenAB1)
10/25/2004
(or A  B C)
(or A  B  C  D)
(only 0 when A and B 1)
EE 42 fall 2004 lecture 23
(only 1 when A  B  0)
3
Logic Gates
These are circuits that accomplish a given logic function such as “OR”. We will
shortly see how such circuits are constructed. Each of the basic logic gates has a
unique symbol, and there are several additional logic gates that are regarded as
important enough to have their own symbol. The set is: AND, OR, NOT, NAND,
NOR, and EXCLUSIVE OR.
A
A
AND
C=A·B
B
B
A
B
A
C=A+B B
OR
A
A
NOT
10/25/2004
A
B
NAND
C = A B
NOR
C = A B
C  AB
EXCLUSIVE OR
EE 42 fall 2004 lecture 23
4
Multiple input gates
• And, Or, NAND, and NOR can be
extended to multiple inputs easily
• AND O=(A•B) O=(A•B•C•D…)
• OR O=(A+B) O=(A+B+C+D…)
• Multiple inputs are indicated by just adding
input lines to the symbols
A
B
C
10/25/2004
AND
O=A·B·C
A
B
C
EE 42 fall 2004 lecture 23
NOR
A B  C
5
Generalized Logic Gates
We have the standard logic gates:
AND
NOR
NOT
OR
X OR
We can generalize/simplify by using the small circle in any
line for a NOT function (instead of showing a NOT gate.)
EXAMPLES:
a) A  B
b) C  B
A
B
C
B
a)
B
D
b)
c)
c) B D
10/25/2004
EE 42 fall 2004 lecture 23
6
Logic Circuits
With a combination of logic gates we can construct any logic function. In
these two examples we will find the truth table for the circuit.
A
X
C
B
It is helpful to list the intermediate
logic values (at the input to the OR
gate). Let’s call them X and Y.
Y
Now we complete the truth tables for X and Y, and from that for C. (Note
that X  A  B and Y  B A
and finally C = X + Y)
A
B
X
Y
C
0
0
0
0
0
0
1
0
1
1
1
0
1
0
1
1
1
0
0
0
10/25/2004
EE 42 fall 2004 lecture 23
Interestingly, this is the
same truth table as the
EXCLUSIVE OR
7
Some Useful Theorems
1) A  B  B  A
Defined from form
of truth tables
Communicative
2) A  B  B  A
3) A  B  C  C  B  A
Associative
4) A  B  C  C  B  A
5) A  A  0
6) A  A  1
7) A  B  A  C  A  (B  C)
Distributive
8) A  B  A  B
9) A  B  A  B
10/25/2004
Each of these can be
proved by writing out
truth tables
} de Morgan’s Laws
EE 42 fall 2004 lecture 23
8
Truth table to show
de Morgan’s theorem
10/25/2004
A
B
A+B
A•B
A B
A B
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
EE 42 fall 2004 lecture 23
9
de Morgan’s Theorems
• de Morgan’s Theorems can be used
repeatedly on complex logical expressions
to put them into one of two standard
forms, a sum of products, or a product of
sums
AB  AB
AB  AB
10/25/2004
EE 42 fall 2004 lecture 23
10
Sum of Products
• In a sum of products standard form, each
input appears no more than once in each
term:
A B  C  A B  C
10/25/2004
EE 42 fall 2004 lecture 23
11
Using these properties we can often simplify expressions
Note that
A
B
F
F  AB  AB
But factoring:
F  B(A  A)  B
So a simpler realization is:
B
F
Just a wire !
10/25/2004
EE 42 fall 2004 lecture 23
12
Synthesis
Designing the combinatorial logic circuit
Method1: Certainly we may directly substitute gates for expressions
Example: F  AB  C(A  B)
There are two OR operations and two AND operations plus a NOT
operation: Thus using 4 Gates plus a NOT:
F
B
A
C
10/25/2004
This method uses three different gate
types and unless the expression is
minimized does not lead to any kind of
optimum circuit (its not the fastest, or
cheapest, or lowest power way to
construct the logic function).
EE 42 fall 2004 lecture 23
13
Synthesis
Method 2: Similarly we may directly construct an expression and thus the circuit
from the truth table.
We can construct a sum of products form by taking each row, and then ANDing
the variable from each column (or its inverse).
Each of these become a term in an OR expression.
A
0
B
0
0
1
1
1
0
1
F
0
1
0
1
Clearly F  AB  AB
10/25/2004
A
F
B
Obviously this expression and it’s
realization are not optimal (F=B), but it
shows that a solution can be obtained
from simple rules, which can then be
optimized for speed, area, or power, etc.
EE 42 fall 2004 lecture 23
14
Synthesis
• If we look at a sum or products, we see
that it can be converted into multiple AND
gates each with multiple inputs (some
inverting), and a final multiple input OR
gate.
• A product of sums can be converted into
multiple OR gates each with multiple
inputs (some inverting), and a final
multiple input AND gate.
10/25/2004
EE 42 fall 2004 lecture 23
15
NOR synthesis
• If we look at each of the terms in a sum of
products representation, we can see that
we can express them as a sum as well, so
the whole expression can be done with
only NOR gates
10/25/2004
EE 42 fall 2004 lecture 23
16
NAND Synthesis
Designing the combinatorial logic circuit, cont.
Method 3: NAND GATE SYNTHESIS. We can use De Morgan’s theorem to turn
the sum-of-products expression into a form directly implementable entirely
with NAND gates. (The NOT function is accomplished by a one-input
NAND gate).
Starting with any SUM-OF-PRODUCTS expression:
Y = ABC+DEF we can rewrite it by “inverting” with De Morgan:
Y  (ABC)  (DEF) Clearly this expression is realized with three NAND
gates: one three-input NAND for (ABC) , one for
(DEF) , and one two-input gate to combine them:
A
B
C
The NAND realization, while based on
Y
DeMorgan’s theorem, is in fact much
D
E
simpler: just look at the sum of products
F
expression and use one NAND for each term
and one to combine the terms.
10/25/2004
EE 42 fall 2004 lecture 23
17
Synthesis
Designing the combinatorial logic circuit, cont.
Method 3: NAND GATE SYNTHESIS (CONTINUED).
Two Examples of SUM-OF-PRODUCTS expressions:
X  AB  AB (X-OR function)
Y  ABC  AB C
A
B C
A
X
Y
B
(No connection)
10/25/2004
We could make the drawings simpler
by just using a circle for the NOT
function rather than showing a oneinput NAND gate
EE 42 fall 2004 lecture 23
18
CMOS and complementary logic
• When we look at how to implement logic
into transistors next week, we will see that
we can use the complementary PMOS
and NMOS switches in parallel or in series
with complementary logic to form high
speed, low power logic
10/25/2004
EE 42 fall 2004 lecture 23
19
CMOS NOR
VDD
A
B
A+B
10/25/2004
EE 42 fall 2004 lecture 23
20
CMOS NAND
VDD
A
AB
B
10/25/2004
EE 42 fall 2004 lecture 23
21