CS152 – Computer Architecture and
Engineering
Lecture 6 – Single Cycle + Design Notebook
2004-09-16
John Lazzaro
(www.cs.berkeley.edu/~lazzaro)
Dave Patterson
(www.cs.berkeley.edu/~patterson)
www-inst.eecs.berkeley.edu/~cs152/
CS 152 L06 Single Cycle 1 (1)
UC Regents Fall 2004 © UCB
Review
Timing key concept: critical path
Xilinx: Physical, yet configurable
CS 152 L06 Single Cycle 1 (2)
UC Regents Fall 2004 © UCB
Outline
°Single clock cycle per instruction
=> Data path resource used at most once
per instruction
=> Need to replicate some data path
resources if need more than once:
memory, ALU/adders, …
°Timing, Testing of Single Cycle
°Single Cycle Datapath
• 5 generic steps (on next slide)
• See how far we get this lecture; finish next time
°Design Notebook
CS 152 L06 Single Cycle 1 (3)
UC Regents Fall 2004 © UCB
How to Design a Processor: step-by-step
° 1. Analyze instruction set => datapath requirements
• the meaning of each instruction is given by the register transfers
• datapath must include storage element for ISA registers
-
possibly more
• datapath must support each register transfer
° 2. Select set of datapath components and establish
clocking methodology
° 3. Assemble datapath meeting the requirements
° 4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
° 5. Assemble the control logic
CS 152 L06 Single Cycle 1 (4)
UC Regents Fall 2004 © UCB
The MIPS Instruction Formats
° All MIPS instructions are 32 bits long. The three instruction
formats:
31
26
21
16
11
6
op
• R-type
rs
6 bits
31
5 bits
26
op
• I-type
• J-type
5 bits
21
rs
6 bits
31
rt
5 bits
rd
shamt
funct
5 bits
5 bits
6 bits
16
0
immediate
rt
5 bits
16 bits
26
op
6 bits
0
0
target address
26 bits
° The different fields are:
• op: operation of the instruction
•
•
•
•
•
rs, rt, rd: the source and destination register specifiers
shamt: shift amount
funct: selects the variant of the operation in the “op” field
address / immediate: address offset or immediate value
target address: target address of the jump instruction
CS 152 L06 Single Cycle 1 (5)
UC Regents Fall 2004 © UCB
Step 1a: The MIPS-lite Subset for today
31
° ADD and SUB
• addU rd, rs, rt
• subU rd, rs, rt
op
31
• lw rt, rs, imm16
• sw rt, rs, imm16
° BRANCH:
• beq rs, rt, imm16
CS 152 L06 Single Cycle 1 (6)
op
31
5 bits
21
26
op
6 bits
5 bits
16
5 bits
0
rd
shamt
funct
5 bits
5 bits
6 bits
0
16 bits
0
immediate
5 bits
21
rs
6
immediate
rt
5 bits
11
16
rt
rs
6 bits
5 bits
21
rs
6 bits
31
26
16
rt
5 bits
26
op
° LOAD and STORE Word
21
rs
6 bits
° OR Immediate:
• ori rt, rs, imm16
26
16 bits
16
rt
5 bits
0
immediate
16 bits
UC Regents Fall 2004 © UCB
Lectures vs. Chapter 5 COD 3/e
° Difficult complaint for textbook author:
Lecturing directly from the textbook!
° Good news: These lectures differ from book
Book
Lectures
° MIPS-lite subset:
• Addu, Subu, LW, SW
• BEQ, ORi
CS 152 L06 Single Cycle 1 (7)
° MIPS-lite subset:
• Add, Sub, LW, SW
• BEQ, OR
• AND, SLT, J
UC Regents Fall 2004 © UCB
Using Hardware Description Lang.
° All start by fetching the instruction
op | rs | rt | rd | shamt | funct <= MEM[ PC ]
op | rs | rt | Imm16
<= MEM[ PC ]
inst
HDL description
ADDU
R[rd] <= R[rs] + R[rt];
PC <= PC + 4
SUBU
R[rd] <= R[rs] – R[rt];
PC <= PC + 4
ORi
R[rt] <= R[rs] | zero_ext(Imm16);
PC <= PC + 4
LOAD
R[rt] <= MEM[ R[rs] + sign_ext(Imm16)]; PC <= PC + 4
STORE
MEM[ R[rs] + sign_ext(Imm16) ] <= R[rt]; PC <= PC + 4
BEQ
CS 152 L06 Single Cycle 1 (8)
if ( R[rs] == R[rt] ) PC <= PC + 4 +
{sign_ext(Imm16), 2’b00 }
else PC <= PC + 4
UC Regents Fall 2004 © UCB
Step 1: Requirements of the Instruction Set
° Memory
• One for instructions, one for data
° Registers (32 x 32bit)
• Read RS
• Read RT
• Write RT or RD
° PC
° Sign Extender (for immediate field)
° Add and Sub register or Extended Immediate
° Add 4 or Extended Immediate to PC
CS 152 L06 Single Cycle 1 (9)
UC Regents Fall 2004 © UCB
Step 2: Components of the Datapath
°Combinational Logic Elements
°Storage Elements (“State”)
• Clocking methodology
CS 152 L06 Single Cycle 1 (10)
UC Regents Fall 2004 © UCB
Combinational Logic Elements (Basic Building Blocks)
CarryIn
°Adder A
B
Adder
32
32
Sum
(to add
values)
Carry
32
Select
32
°MUX
(multi- B
plexor)
B
32
Y
(to chose
between
values)
Result
(to do add,
subtract, or)
32
OP
32
32
CS 152 L06 Single Cycle 1 (11)
ALU
°ALU
A
MUX
A
32
UC Regents Fall 2004 © UCB
Storage Element: Register (Basic Building Block)
°Register
• Similar to the D Flip Flop
except
Write Enable
Data In
N
Data Out
N
- N-bit input and output
- Write Enable input
Clk
• Write Enable:
- negated (0): Data Out will not change
- asserted (1): Data Out will become Data In
CS 152 L06 Single Cycle 1 (12)
UC Regents Fall 2004 © UCB
Storage Element: Register File
RW RA RB
Write Enable 5 5 5
° Register File consists of 32 registers:
• Two 32-bit output busses:
busA and busB
• One 32-bit input bus: busW
busA
32
busW
32
Clk
32 32-bit
Registers busB
° Register is selected by:
32
• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be written
via busW (data) when Write Enable is 1
° Clock input (CLK)
• The CLK input is a factor ONLY during write operation
• During read operation, Register File behaves as a
combinational logic block:
-
RA or RB valid => busA or busB valid after “access time.”
CS 152 L06 Single Cycle 1 (13)
UC Regents Fall 2004 © UCB
Storage Element: Idealized Memory
° Memory (idealized)
• One input bus: Data In
• One output bus: Data Out
° Memory word is selected by:
Write Enable
Address
Data In
32
Clk
DataOut
32
• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memory
word to be written via the Data In bus
° Clock input (CLK)
• The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic
block:
-
Address valid => Data Out valid after “access time.”
CS 152 L06 Single Cycle 1 (14)
UC Regents Fall 2004 © UCB
Administrivia
°Last mini-lab Friday
°Lab #2 Design Document due Friday
• Should already have groups
°Reading: Sections 5.1 to 5.4, 5.8,
Appendix B of COD 3e
CS 152 L06 Single Cycle 1 (15)
UC Regents Fall 2004 © UCB
Computers In The News
°“Intel shifts focus to multicore chip
performance” 9/7/04 S.F. Chronicle
°Intel Corp., which has led the charge in the
gigahertz race, is expected to change its
tune… Excess heat in PC microprocessors
has become an increasingly difficult problem to
solve as chipmakers crank up the frequency of
the tiny transistors to boost performance. Dual
core will be part of Intel's big theme ... which
shows Intel is changing direction from focusing
on faster and faster gigahertz to other
features," he said. Chips with multiple cores
are not new. Both IBM and Sun have such
processors for larger server computers and
AMD last week introduced its dual-core CPU.
CS 152 L06 Single Cycle 1 (16)
UC Regents Fall 2004 © UCB
Review: Clocking Methodology
Clk
Setup
Hold
Setup
Hold
.
.
.
.
.
.
Don’t Care
.
.
.
.
.
.
° All storage elements are clocked by the same clock edge
° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock
Skew
° (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time
CS 152 L06 Single Cycle 1 (17)
UC Regents Fall 2004 © UCB
Step 3: Assemble Datapath meeting our requirements
°HDL (Verilog) Requirements
 Datapath Assembly
°Instruction Fetch
°Read Operands and Execute Operation
CS 152 L06 Single Cycle 1 (18)
UC Regents Fall 2004 © UCB
3a: Overview of the Instruction Fetch Unit
° The common operations
• Fetch the Instruction: mem[PC]
• Update the program counter:
-
Sequential Code: PC <= PC + 4
Branch and Jump: PC <= “something else”
Clk
PC
Next Address
Logic
Address
Instruction
Memory
CS 152 L06 Single Cycle 1 (19)
Instruction Word
32
UC Regents Fall 2004 © UCB
3b: Add & Subtract
° R[rd] <= R[rs] op R[rt]
Example: addU rd, rs, rt
• Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the
instruction
31
26
21
op
rs
6 bits
RegWr
16
rt
5 bits
5 bits
Rd Rs
5
5
Rt
0
rd
shamt
funct
5 bits
5 bits
6 bits
busA
32
busB
ALU
32
Clk
32 32-bit
Registers
6
ALUctr
5
Rw Ra Rb
busW
11
Result
32
32
CS 152 L06 Single Cycle 1 (20)
UC Regents Fall 2004 © UCB
Register-Register Timing: One complete cycle
Clk
PC
Old Value
Clk-to-Q
New Value
Rs, Rt, Rd,
Op, Func
Old Value
ALUctr
Old Value
busA, B
busW
RegWr
Instruction Memory Access Time
New Value
Delay through Control Logic
New Value
Register File Access Time
New Value
Old Value
ALU Delay
New Value
Old Value
Old Value
New Value
Rd Rs Rt
RegWr 5 5
5
CS 152 L06 Single Cycle 1 (21)
32 32-bit
Registers
ALUctr
busA
32
busB
32
ALU
busW
32
Clk
Rw Ra Rb
Register Write
Occurs Here
Result
32
UC Regents Fall 2004 © UCB
3c: Logical Operations with Immediate
° R[rt] <= R[rs] op ZeroExt[imm16] ]
31
26
op
21
rs
6 bits
rt
5 bits
Mux
RegWr 5
Rs Rt?
5
5
32 32-bit
Registers
32
Clk
32
busB
Mux
ZeroExt
CS 152 L06 Single Cycle 1 (22)
16
16 bits
busA
32
imm16
immediate
ALUctr
Rw Ra Rb
busW
0
and I-type different
field for destination
ALU
Additions
to prior
Datapath
16 15
16 bits
rd?
0000000000000000
16 bits
Rt
Why? R-type
Rd
0
immediate
5 bits
31
RegDst
11
16
32
Result
32
Why? Reg file busB or
Immediate
ALUSrc
Why? 0-extend immed.UC Regents Fall 2004 © UCB
3d: Load Operations
° R[rt] <= Mem[R[rs] + SignExt[imm16]]
Example: lw rt, rs, imm16
31
26
op
rs
6 bits
Rd
RegDst
Mux
RegWr 5
32
Clk
rt
5 bits
5 bits
16 bits
Rs Rt?
5
5
W_Src
32
busB
32
32
ExtOp
32
MemWr
??
ALUSrc
Data In
32
Clk
Mux
CS 152 L06 Single Cycle 1 (23)
busA
Mux
0 or sign
extend Why?
Chose ALU output
or Data Memory output
Why?
ALUctr
Extender
16
0
immediate
Rt
Rw Ra Rb
32 32-bit
Registers
imm16
16
ALU
busW
21
WrEn Adr
Data
Memory
32
Separate memory for data
Why?
UC Regents Fall 2004 © UCB
3e: Store Operations
° Mem[ R[rs] + SignExt[imm16] ] <= R[rt]
Example: sw rt, rs, imm16
31
26
21
op
rs
6 bits
Rd
Rt
RegDst
16
rt
5 bits
0
immediate
5 bits
16 bits
ALUctr
MemWr
W_Src
Mux
RegWr 5
32
Clk
5
Rt
Rw Ra Rb
32 32-bit
Registers
32
ExtOp ALUSrc
CS 152 L06 Single Cycle 1 (24)
32
Data In 32
Why?
Clk
WrEn Adr
Data
Memory
Mux
busB
32
Mux
16
32
Extender
imm16
busA
ALU
busW
5
Rs
32
Reg file bus B as
Data Memory input
UC Regents Fall 2004 © UCB
3f: The Branch Instruction
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
° beq rs, rt, imm16
• mem[PC]
Fetch the instruction from memory
• Equal <= (R[rs] == R[rt])
Calculate the branch condition
• if (Equal)
-
•
Calculate the next instruction’s address
PC <= PC + 4 + { SignExt(imm16) , 2b00 }
else
-
PC <= PC + 4
CS 152 L06 Single Cycle 1 (25)
UC Regents Fall 2004 © UCB
Datapath for Branch Operations
° beq rs, rt, imm16
Datapath generates condition (equal)
26
op
21
rs
6 bits
16
rt
5 bits
0
immediate
5 bits
16 bits
Inst Address
PCSrc
4
Adder
RegWr 5
busW
PC
Mux
00
32
Adder
PC Ext
imm16
Cond
Clk
5
Rs
5
Rt
Rw Ra Rb
32 32-bit
Registers
busA
32
busB
32
Equal?
31
Why?
Clk
Test if Reg file busA
equals Reg file busB
Chose PC+4 or
Why?
PC+4+{SignExtImm, 00}
CS 152 L06 Single Cycle 1 (26)
UC Regents Fall 2004 © UCB
Putting it All Together: A Single Cycle Datapath
RegDst
PCSrc
00
busA
Rw Ra Rb
32 32-bit
Registers
busB
32
imm16
16
=
32
0
1
32
Data In
32
Clk
0
32
Mux
imm16
5
ExtOp
CS 152 L06 Single Cycle 1 (27)
MemtoReg
Rt
Extender
Clk
5
Rs
Mux
PC
Mux
PC Ext
Adder
Clk
ALUctr MemWr
Equal
ALU
Adder
32
Imm16
0
RegWr 5
busW
Rd
Rd Rt
1
4
Rt
Instruction<31:0>
<0:15>
Rs
<11:15>
Adr
<16:20>
<21:25>
Inst
Memory
WrEn Adr
Data
Memory
1
ALUSrc
UC Regents Fall 2004 © UCB
Lectures vs. Chapter 5 3/e
Lectures
Book
° MIPS-lite subset:
° MIPS-lite subset:
• Add, Sub, LW, SW
• BEQ, OR
• AND, SLT, J
• AddU, SubU, LW, SW
• BEQ, ORI
° Control lines names
° Control lines names
• MemtoReg, PCSrc,
ALUSrc, RegDst
• MemWr, RegWr
• ExtOp (zero extend or
sign extend)
• ALUctr 3 bits (no NOR)
• MemWr==0 => MemRead
CS 152 L06 Single Cycle 1 (28)
• MemtoReg, PCSrc,
ALUSrc, RegDst
• MemWrite, RegWrite
• No ExtOp since subset
address just sign extend
• ALUoperation 4 bits
• MemRead & MemWrite
UC Regents Fall 2004 © UCB
Step 5: Implement the control
Next Time!
CS 152 L06 Single Cycle 1 (29)
UC Regents Fall 2004 © UCB
Types of Bugs in Single Cycle Lab 2?
°Which Epoch most likely to uncover
bugs for Single Cycle Design?
°Which Epoch would you expect for
Pipelined Design?
°Which tests from Single Cycle Design
can be reused for Pipelined Design?
°Suggestions for a good your plan?
CS 152 L06 Single Cycle 1 (30)
UC Regents Fall 2004 © UCB
Recap Test Plan: The testing timeline
Top-down
testing
complete
processor
testing
processor
testing
with
self-checks
Which testing types are good for each epoch?
Epoch 1
unit
testing
early
multi-unit
testing
multi
unit
testing
later
Epoch 2
processor
testing
with
self-checks
Epoch 3
processor
testing
with
self-checks
multi-unit
testing
multi-unit
testing
unit testing
unit testing
CS 152 L06 Single Cycle 1 (31)
complete
processor
testing
verification
processor
testing
with
self-checks
diagnostics diagnostics diagnostics
Time
unit testing
Bottom-up
testing
Epoch 4
processor
assembly
complete
correctly
executes
single
instructions
correctly
executes
short
programs
UC Regents Fall 2004 © UCB
Peer Evaluation Question Assumptions
°
For the next few slides in this
lecture assume that
1. Delay to Access Register File
@ Delay to do 32-bit add
@ Delay to do 32-bit ALU operation
2. Multiplexor delays 0 (ignore for now)
CS 152 L06 Single Cycle 1 (32)
UC Regents Fall 2004 © UCB
Peer Instruction: What is critical path for BEQ?
A. PC’s Clk-to-Q
B. Instruction Memory’s Access Time
C. Register File’s Access Time
D. ALU to Perform a 32-bit Operation
E. PC Adder1 adds 4 to PC
F. PC Ext sign extends immediate
G. PC Adder2 adds imm to Adder1 sum
Rd Rt
H. Data Memory Access Time
0
1
I. Setup Time for PC
Rs Rt
J. Setup Time for Register File Write
5
5
5
Equal
busA K. Clock Skew
1. A, B, C, D, I, K
2. A, B, C, D, G, I, K
3. A, B, C, D, E, F, G, I, J, K
4. A, B, C, D, E, F, G, H, I, J, K
Inst
Memor
y
imm16
16
0
1
32
Data In
32
Clk
0
32
Mux
CS 152 L06 Single Cycle 1 (33)
imm16
Extender
Clk
=
32
Mux
PC
Mux
PC Ext
Adder2
busW Wr Rw Ra Rb
32 32-bit
32
Registers
busB
32
Clk
ALU
00
Adder1
4
WrEn Adr
1
Data
Memory
UC Regents Fall 2004 © UCB
Peer Instruction: What is critical path for LW?
A. PC’s Clk-to-Q
B. Instruction Memory’s Access Time
C. Register File’s Access Time
D. ALU to Perform a 32-bit Operation
E. PC Adder1 adds 4 to PC
F. PC Ext sign extends immediate
G. PC Adder2 adds imm to Adder1 sum
Rd Rt
H. Data Memory Access Time
0
1
I. Setup Time for PC
Rs Rt
J. Setup Time for Register File Write
5
5
5
Equal
busA K. Clock Skew
1. A, B, C, D, H, J, K
2. A, B, C, D, H, I, J, K
3. A, B, C, D, E, H, I, J, K
4. A, B, C, D, E, F, G, H, I, J, K
Inst
Memor
y
imm16
16
0
1
32
Data In
32
Clk
0
32
Mux
CS 152 L06 Single Cycle 1 (35)
imm16
Extender
Clk
=
32
Mux
PC
Mux
PC Ext
Adder2
busW Wr Rw Ra Rb
32 32-bit
32
Registers
busB
32
Clk
ALU
00
Adder1
4
WrEn Adr
1
Data
Memory
UC Regents Fall 2004 © UCB
Peer Instruction: Which has longest critical path?
1. ADDU
2. BEQ
3. LW
4. ORI
5. SUBU
6. SW
imm16
16
0
1
32
Data In
32
Clk
0
32
Mux
CS 152 L06 Single Cycle 1 (37)
imm16
Extender
Clk
=
32
Mux
PC
Mux
PC Ext
Adder2
busW Wr Rw Ra Rb
32 32-bit
32
Registers
busB
32
Clk
ALU
00
Adder1
4
Inst
Memor
y
A. PC’s Clk-to-Q
B. Instruction Memory’s Access Time
C. Register File’s Access Time
D. ALU to Perform a 32-bit Operation
E. PC Adder1 adds 4 to PC
F. PC Ext sign extends immediate
G. PC Adder2 adds imm to Adder1 sum
Rd Rt
H. Data Memory Access Time
0
1
I. Setup Time for PC
Rs Rt
J. Setup Time for Register File Write
5
5
5
Equal
busA K. Clock Skew
WrEn Adr
1
Data
Memory
UC Regents Fall 2004 © UCB
An Abstract View of the Implementation
Control
Ideal
Instruction
Memory
Rd Rs
5
5
Instruction
Address
Rw Ra Rb
PC
32 32-bit
Registers
Clk
Conditions
Rt
5
A
32
Clk
Control Signals
32
32
ALU
Next Address
Instruction
B
32
Data
Address
Data
In
Ideal
Data
Memory
Data
Out
Clk
Datapath
CS 152 L06 Single Cycle 1 (40)
UC Regents Fall 2004 © UCB
Why should you keep a design notebook?
° Keep track of the design decisions and the reasons
behind them
• Otherwise, it will be hard to debug and/or refine the design
• Write it down so that can remember in long project:
2 weeks ->2 yrs
• Others can review notebook to see what happened
° Record insights you have on certain aspect of the
design as they come up
° Record of the different design & debug experiments
• Memory can fail when very tired
° Industry practice: learn from others mistakes
CS 152 L06 Single Cycle 1 (41)
UC Regents Fall 2004 © UCB
Why do we keep it on-line?
° You need to force yourself to take notes!
• Open a window and leave an editor running while you work
1) Acts as reminder to take notes
2) Makes it easy to take notes
• 1) + 2) => will actually do it
° Take advantage of the window system’s
“cut and paste” features
° It is much easier to read your typing than your writing
° Also, paper log books have problems
• Limited capacity => end up with many books
• May not have right book with you at time vs. networked
screens
• Can use computer to search files/index files to find what
looking for
CS 152 L06 Single Cycle 1 (42)
UC Regents Fall 2004 © UCB
How should you do it?
° Keep it simple
• DON’T make it so elaborate that you won’t use (fonts, layout, ...)
° Separate the entries by dates
• type “date” command in another window and cut&paste
° Start day with problems going to work on today
° Record output of simulation into log with cut&paste; add
date
• May help sort out which version of simulation did what
° Record key email with cut&paste
° Record of what works & doesn’t helps team decide what
went wrong after you left
° Index: write a one-line summary of what you did at end of
each day
CS 152 L06 Single Cycle 1 (43)
UC Regents Fall 2004 © UCB
On-line Notebook Example
°Refer to the handout
“Example of On-Line Log Book” on
CS 152 home page:
~cs152/handouts/online_notebook_example.html
CS 152 L06 Single Cycle 1 (44)
UC Regents Fall 2004 © UCB
1st page of On-line notebook (Index + Wed. 9/6/95)
* Index ==============================================================
Wed Sep 6 00:47:28 PDT 1995 - Created the 32-bit comparator component
Thu Sep 7 14:02:21 PDT 1995 - Tested the comparator
Mon Sep 11 12:01:45 PDT 1995 - Investigated bug found by Bart in
comp32 and fixed it
+ ====================================================================
Wed Sep 6 00:47:28 PDT 1995
Goal: Layout the schematic for a 32-bit comparator
I've layed out the schemtatics and made a symbol for the comparator.
I named it comp32. The files are
~/wv/proj1/sch/comp32.sch
~/wv/proj1/sch/comp32.sym
Wed Sep 6 02:29:22 PDT 1995
- ====================================================================
• Add 1 line index at front of log file at end of each session: date+summary
• Start with date, time of day + goal
• Make comments during day, summary of work
• End with date, time of day (and add 1 line summary at front of file)
CS 152 L06 Single Cycle 1 (45)
UC Regents Fall 2004 © UCB
2nd page of On-line notebook (Thursday 9/7/95)
+ ====================================================================
Thu Sep 7 14:02:21 PDT 1995
Goal: Test the comparator component
I've written a command file to test comp32.
in ~/wv/proj1/diagnostics/comp32.cmd.
I've placed it
I ran the command file in viewsim and it looks like the comparator
is working fine. I saved the output into a log file called
~/wv/proj1/diagnostics/comp32.log
Notified the rest of the group that the comparator
is done.
Thu Sep 7 16:15:32 PDT 1995
- ====================================================================
CS 152 L06 Single Cycle 1 (46)
UC Regents Fall 2004 © UCB
3rd page of On-line notebook (Monday 9/11/95)
+ ===================================================================
=
Mon Sep 11 12:01:45 PDT 1995
Goal: Investigate bug discovered in comp32 and hopefully fix it
Bart found a bug in my comparator component. He left the following
e-mail.
------------------From bart@simpsons.residence Sun Sep 10 01:47:02 1995
Received: by wayne.manor (NX5.67e/NX3.0S)
id AA00334; Sun, 10 Sep 95 01:47:01 -0800
Date: Wed, 10 Sep 95 01:47:01 -0800
From: Bart Simpson <bart@simpsons.residence>
To: bruce@wanye.manor, old_man@gokuraku, hojo@sanctuary
Subject: [cs152] bug in comp32
Status: R
Hey Bruce,
I think there's a bug in your comparator.
The comparator seems to think that ffffffff and fffffff7 are equal.
Can you take a look at this?
Bart
----------------
CS 152 L06 Single Cycle 1 (47)
UC Regents Fall 2004 © UCB
4th page of On-line notebook (9/11/95 contd)
I verified the bug. here's a viewsim of the bug as it appeared..
(equal should be 0 instead of 1)
-----------------SIM>stepsize 10ns
SIM>v a_in A[31:0]
SIM>v b_in B[31:0]
SIM>w a_in b_in equal
SIM>a a_in ffffffff\h
SIM>a b_in fffffff7\h
SIM>sim
time =
10.0ns A_IN=FFFFFFFF\H B_IN=FFFFFFF7\H EQUAL=1
Simulation stopped at 10.0ns.
------------------Ah. I've discovered the bug. I mislabeled the 4th net in
the comp32 schematic.
I corrected the mistake and re-checked all the other
labels, just in case.
I re-ran the old diagnostic test file and tested it against
the bug Bart found. It seems to be working fine. hopefully
there aren’t any more bugs:)
CS 152 L06 Single Cycle 1 (48)
UC Regents Fall 2004 © UCB
5th page of On-line notebook (9/11/95 contd)
On second inspectation of the whole layout, I think I can
remove one level of gates in the design and make it go faster.
But who cares! the comparator is not in the critical path
right now. the delay through the ALU is dominating the critical
path. so unless the ALU gets a lot faster, we can live with
a less than optimal comparator.
I e-mailed the group that the bug has been fixed
Mon Sep 11 14:03:41 PDT 1995
- ================================================================
====
• Perhaps later critical path changes;
• What was idea to make comparator faster?
• Check on-line notebook!
CS 152 L06 Single Cycle 1 (49)
UC Regents Fall 2004 © UCB
Added benefit: cool post-design statistics
Sample graph from the Alewife project:
• For the Communications and
Memory Management Unit (CMMU)
• These statistics came from
on-line record of bugs
CS 152 L06 Single Cycle 1 (50)
UC Regents Fall 2004 © UCB
Lecture Summary
° 5 steps to design a processor
1. Analyze instruction set => datapath requirements
2. Select set of datapath components & establish clock methodology
3. Assemble datapath meeting the requirements
4. Analyze implementation of each instruction to determine setting of control
points that effects the register transfer.
5. Assemble the control logic (Next Lecture)
° MIPS makes it easier
• Instructions same size; Source registers, immediates always in same place
• Operations always on registers/immediates
° Single cycle datapath => CPI=1, CCT => long
° On-line Design Notebook
• Open a window and keep an editor running while you work;cut&paste
• Former CS 152 students (and TAs) say they use on-line notebook
for
programming as well as hardware design; one of most valuable
skills
•
Refer to the handout as an example
CS 152 L06 Single Cycle 1 (51)
UC Regents Fall 2004 © UCB