CS61CL Machine Structures
Lec 8 – State and Register Transfers
David Culler
Electrical Engineering and Computer Sciences
University of California, Berkeley
CS61CL Road Map
HLL Program
Asm Lang. Pgm
Machine Lang. pgm
foo.s
foo.c
foo.exe
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Semiconductor Materials
10/14/09
CS61CL F09
2
Review: Combinational Logic
• Any boolean function can be expressed as an
acyclic connection of gates
• Often specified by a truth table
k
inputs
outputs
inputs
Logic
outputs
Combinational
2k
• Outputs are purely a function of the inputs
– no history, no state
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Examples: Logical Operations
A B
A31 B31 A30 B30
C=A&B
A0 B0
°°°
C
C31
A31:0 B31:0
C31:0
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A31:0 B31:0
C31:0
CS61CL F09
C30
C0
A31:0 B31:0
C31:0
A31:0
C31:0
4
Example: Multiplexor
B
A
C=S?A:B
S
C = (S & A) | (~S & B)
C
A31:0 B31:0
S
C31:0
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Example: Adder
A B Ci
A B Ci
A B Ci
A B Ci
A B Ci
Co S
Co S
Co S
Co S
Co S
A31:0 B31:0
C31:0
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Example: Arithmetic Logic Unit
A31:0 B31:0
S1:0
C31:0
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ALU
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Element of Time
+3
Propagation delay
Vout
0
T
• Logical change is not instantaneous
• Broader digital design methodology has to make it appears
as such
– Clocking, delay estimation, glitch avoidance
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What makes Digital Systems tick?
Combinational
Logic
clk
time
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Administrative Issues
• HW 6 due tonight
• Project 2 dues Monday 10/26
– bimodal check-off
– testing tools available tomorrow
– they are really picky
• Project 1 grading almost done
– Friday
• HW 7 – discuss
• Midterm 2 on 11/9 as in original schedule
– 11/11 is holiday
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A Bit of state: D-type edge-triggered
flip-flop
0
1
0
1
0
1
0
• The edge of the clock is used
to sample the "D" input &
send it to "Q” (positive edge
triggering).
– At all other times the output Q is
independent of the input D (just
stores previously sampled value).
– The input must be stable for a
short time before the clock edge.
8/30/2007
12
Registers
• Collections of flip-flops with similar controls and
logic
– Stored values somehow related (e.g., form binary value)
– Share clock, reset, and set lines
– Similar logic at each stage
OUT1
OUT2
OUT3
OUT4
"0"
R S
D Q
R S
D Q
R S
D Q
R S
D Q
CLK
IN1
IN2
IN3
IN4
13
9/18/07
What “registers” do we need?
r0
r1
°
°
°
r31
PC
lo
hi
0
Programmable storage
2^32 x bytes
31 x 32-bit GPRs (R0=0)
32 x 32-bit FP regs (paired DP)
HI, LO, PC
• “read” vs use the output
• “write” on the clock edge => Load
• Load Control
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Register with Load Control
1
load
clock
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0
R0
R31
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Register File
Asel
Din
Bsel
R0
Dsel
1
decoder
R1
R2
Bout
Aout
°°°
R31
ld
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Towards a Data Path
Asel
Bsel
Dsel
ld
°°°
aluOP
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Exercise a Data Path
Asel
Bsel
Dsel
ld
2
4
2
7 10 13
3
1
°°°
7 13
10
3 3
aluOP
10
13 16
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What about RAM - Randomly Accessed
Memory?
RAM
address
data
• Like a HUGE register file
–
–
–
–
dense, slower, low-cost storage cell (6T)
fewer ports
wider address lines
accessed over a “bus”
• Bus: means of composition in hardware system
– logically related collection of wires
– interfacing one or more sources to one or more destinations
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Recall: Instruction Cycle
000..0:
n:
main: 0B20:
°°°
FFF..F:
32 2 3 1
Instruction Fetch
“add $1,$2,$3”
Decode
40
Operand
Execute
61
101
+
Result
Next
9/16/09
PC
UCB CS61CL F09 Lec 4
0B20
0B24
20
Register Transfers
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Synchronous Circuit Design
clock
input
input
CL
CL
reg
reg
output
option feedback
output
• Combinational Logic Blocks (CL)
– Acyclic
• clock
– no internal state (no feedback)
– output only a function of inputs
• Registers (reg)
– distributed to all flip-flops
• ALL CYCLES GO THROUGH
A REG!
– collections of flip-flops
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