CS 61C: Great Ideas in Computer
Architecture (Machine Structures)
Caches
Instructor:
Michael Greenbaum
6/27/2016
Spring 2011 -- Lecture #11
1
Review: Performance
• Latency vs. Throughput.
• Time (seconds/program) is performance measure
Instructions × Clock cycles × Seconds
=
Program
Instruction Clock Cycle
• Time measurement via clock cycles, machine
specific
• Power of increasing concern, and being added to
benchmarks
• Profiling tools (eg, gprof) as way to see where
spending time in your program.
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Spring 2011 -- Lecture #11
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New-School Machine Structures
(It’s a bit more complicated!)
Software
• Parallel Requests
Assigned to computer
e.g., Search “Katz”
Hardware
Harness
Smart
Phone
Warehouse
Scale
Computer
• Parallel Threads Parallelism &
Assigned to core
e.g., Lookup, Ads
Achieve High
Performance
Computer
• Parallel Instructions
>1 instruction @ one time
e.g., 5 pipelined instructions
• Parallel Data
>1 data item @ one time
e.g., Add up 4 pairs of words
• Hardware descriptions
All gates @ one time
6/27/2016
…
Core
Memory
Today and
Core Tomorrow
(Cache)
Input/Output
Instruction Unit(s)
Core
Functional
Unit(s)
A0+B0 A1+B1 A2+B2 A3+B3
Main Memory
Logic Gates
Spring 2011 -- Lecture #11
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Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
6/27/2016
Spring 2011 -- Lecture #11
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Storage in a Computer
• Processor
– holds data in register file (~100 Bytes)
– Registers accessed on sub-nanosecond
timescale
• Memory (we’ll call “main memory”)
– More capacity than registers (~Gbytes)
– Access time ~50-100 ns
– Hundreds of clock cycles per memory access?!
Historical Perspective
• 1989 first Intel CPU with cache on chip
• 1998 Pentium III has two cache levels on chip
CPU
µProc
60%/yr.
Processor-Memory
Performance Gap:
(grows 50% / year)
DRAM
DRAM
7%/yr.
100
10
2000
1999
1998
1997
1996
1995
1994
1993
1992
1991
1990
1989
1988
1987
1986
1985
1984
1983
1982
1981
1
1980
Performance
1000
Great Idea #3: Principle of Locality/
Memory Hierarchy
6/27/2016
Spring 2011 -- Lecture #1
7
Library Analogy
• Writing a report on a specific topic.
– E.g., works of J.D. Salinger
• While at library, check out books and keep them
on desk.
• If need more, check them out and bring to desk.
– But don’t return earlier books since might need them
– Limited space on desk; Which books to keep?
• You hope this collection of ~10 books on desk
enough to write report, despite 10 being only
0.00001% of books in UC Berkeley libraries
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Spring 2011 -- Lecture #11
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Locality
• Temporal Locality (locality in time)
– Go back to same book on desktop multiple times
– If a memory location is referenced then it will tend to
be referenced again soon
• Spatial Locality (locality in space)
– When go to book shelf, pick up multiple books on J.D.
Salinger since library stores related books together
– If a memory location is referenced, the locations with
nearby addresses will tend to be referenced soon
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Principle of Locality
• Principle of Locality: Programs access small
portion of address space at any instant of time
• What program structures lead to temporal
and spatial locality in code?
• In data?
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How does hardware exploit principle
of locality?
• Offer a hierarchy of memories where
– closest to processor is fastest
(and most expensive per bit so smallest)
– furthest from processor is largest
(and least expensive per bit so slowest)
• Goal is to create illusion of memory almost as
fast as fastest memory and almost as large as
biggest memory of the hierarchy
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Spring 2011 -- Lecture #11
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Memory Hierarchy
Processor
Higher
Levels in
memory
hierarchy
Lower
Level 1
Level 2
Increasing
distance from
processor,
decreasing
speed
Level 3
...
Level n
Size of memory at each level
As we move to deeper levels the latency goes up
and price per bit goes down. Why?
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Spring 2011 -- Lecture #11
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Caches
• Processor and memory speed mismatch leads us to
add a new level: a memory cache
• Implemented with same integrated circuit processing
technology as processor, integrated on-chip: faster but
more expensive than DRAM memory
• Cache is a copy of a subset of main memory
• Modern processors have separate caches for
instructions and data, as well as several levels of caches
implemented in different sizes
• As a pun, often use $ (“cash”) to abbreviate cache,
e.g. D$ = Data Cache, I$ = Instruction Cache
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Spring 2011 -- Lecture #11
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Memory Hierarchy Technologies
• Caches use SRAM (Static RAM) for speed and
technology compatibility
– Fast (typical access times of 0.5 to 2.5 ns)
– Low density (6 transistor cells), higher power, expensive
($2000 to $4000 per GB in 2011)
– Static: content will last as long as power is on
• Main memory uses DRAM (Dynamic RAM) for size
(density)
– Slower (typical access times of 50 to 70 ns)
– High density (1 transistor cells), lower power, cheaper
($20 to $40 per GB in 2011)
– Dynamic: needs to be “refreshed” regularly (~ every 8 ms)
6/27/2016
• Consumes 1% to 2% of the active cycles of the DRAM
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Characteristics of the Memory Hierarchy
Increasing
distance
from the
processor in
access time
Block – Unit
of transfer
between
memory and
cache
Processor
4-8 bytes (word)
L1$
8-32 bytes (block)
L2$
16-128 bytes (block)
Main Memory
Inclusive–
what is in L1$
is a subset of
what is in L2$
is a subset of
what is in MM
that is a subset
of is in SM
4,096+ bytes (page)
Secondary Memory
(Relative) size of the memory at each level
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Spring 2011 -- Lecture #11
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How is the Hierarchy Managed?
• registers  memory
– By compiler (or assembly level programmer)
• cache  main memory
– By the cache controller hardware
• main memory  disks (secondary storage)
– By the operating system (virtual memory)
– (Talk about later in the semester)
– Virtual to physical address mapping assisted by the
hardware (TLB)
– By the programmer (files)
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Typical Memory Hierarchy
On-Chip Components
Control
Size (bytes):
Cost/bit:
Instr
Data
Cache Cache
Speed (cycles):
RegFile
Datapath
Second
Level
Cache
(SRAM)
Main
Memory
(DRAM)
½’s
1’s
10’s
100’s
100’s
10K’s
M’s
G’s
highest
Secondary
Memory
(Disk
Or Flash)
1,000,000’s
T’s
lowest
• Principle of locality + memory hierarchy presents programmer with
≈ as much memory as is available in the cheapest technology at the
≈ speed offered by the fastest technology
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Spring 2011 -- Lecture #11
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Review so far
• Wanted: size of the largest memory
available, speed of the fastest memory
available
• Approach: Memory Hierarchy
– Successively lower levels contain “most
used” data from next higher level
– Exploits temporal & spatial locality
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Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
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Administrivia
• Midterm
– Friday 7/15, 9am-12pm, 2050 VLSB
– How to study:
•
•
•
•
Studying in groups can help.
Take old exams for practice (link at top of main webpage)
Look at lectures, section notes, projects, hw, labs, etc.
Go to Review Session.
– Will cover up to tomorrow’s material.
• Midterm Review Session
– TODAY, 4pm – 6pm, Wozniak Lounge
6/27/2016
Spring 2011 -- Lecture #11
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Administrivia
• HW1 grades are up, check using glookup
– Send questions about grading to your reader.
• Mid-Session Survey
– Short survey to complete as part of Lab 7.
– Let us know how we’re doing, and what we can do
to improve!
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Spring 2011 -- Lecture #11
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Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
6/27/2016
Spring 2011 -- Lecture #11
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Cache Management
• Cache managed automatically by hardware.
• Operations available in hardware are limited,
scheme needs to be relatively simple.
• Where in the cache do we put a block of data
from memory?
– How do we find it when we need it?
• What is the overall organization of blocks we
impose on our cache?
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Spring 2011 -- Lecture #11
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Direct Mapped Caches
• Each memory block is mapped to exactly one
block in the cache
– Only need to check this single location to see if
block is in cache.
• Cache is smaller than memory
– Multiple blocks in memory map to a single block
in the cache!
– Need some way of determining the identity of the
block.
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Spring 2011 -- Lecture #11
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Direct Mapped Caches
• Address mapping:
– (block address) modulo (# of blocks in the cache)
– Lower bits of memory address determine which
block in the cache the block is stored.
– Upper bits of memory address (Tag) determine
which block in memory the block came from.
Tag
6/27/2016
Index
Memory Address Fields (For now…)
Spring 2011 -- Lecture #11
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Block Mapping From Memory
6/27/2016
4-bit memory addresses
0000
0001
Cache
0010
Index Valid Tag
Data
0011
00
0100
0101
01
0110
10
0111
11
1000
1001
1010
1011
1100
1101
1110
1111
(block address) modulo (# of blocks in the cache)
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Full Address Breakdown
• Lowest bits of address (Offset) determine which
byte within a block it refers to.
• Full address format:
Tag
Index
Offset
Memory Address
• n-bit Offset means a block is how many bytes?
• n-bit Index means cache has how many blocks?
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TIO Breakdown- Summary
• All fields are read as unsigned integers.
• Index
– specifies the cache index (which “row”/block of the
cache we should look in)
– I bits <=> 2I blocks in cache
• Offset
– once we’ve found correct block, specifies which byte
within the block we want (which “column” in the cache)
– O bits <=> 2O bytes per block
• Tag
– the remaining bits after offset and index are
determined; these are used to distinguish between all
the memory addresses that map to a given location
Caching: A First Example
Main Memory - 6 bit addresses
0000xx
One word blocks
0001xx
Cache
Two low order bits
0010xx
Index Valid Tag
Data
define the byte in the
0011xx
block
00
0100xx
0101xx
01
0110xx
10
0111xx Q: Where in the cache is
11
1000xx the mem block?
1001xx
Q: Is the mem block in cache?
1010xx Use next 2 low order
1011xx memory address bits –
Compare the cache tag to the
1100xx the index – to determine
high order 2 memory address
1101xx which cache block (i.e.,
bits to tell if the memory
1110xx modulo the number of
block is in the cache
1111xx blocks in the cache)
(block address) modulo (# of blocks in the cache)
6/27/2016
Spring 2011 -- Lecture #11
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Multiword Block Direct Mapped Cache
• Four words/block, cache size = 1K words
31 30 . . .
Hit
Tag
Index Valid
13 12 11 . . . 4 3 2 1 0
20
Index
Byte
offset
Data
Block offset
8
Data (words)
Tag
0
1
2
.
.
.
253
254
255
20
and
32
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Spring 2011 -- Lecture #11
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Caching Terminology
• When reading memory, 3 things can happen:
– cache hit:
cache block is valid and contains proper address,
so read desired word
– cache miss:
nothing in cache in appropriate block, so fetch
from memory
– cache miss, block replacement:
wrong data is in cache at appropriate block, so
discard it and fetch desired data from memory
(cache always copy)
Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
6/27/2016
Spring 2011 -- Lecture #11
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Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
6/27/2016
Spring 2011 -- Lecture #11
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Direct Mapped Cache
• Consider the sequence of memory address accesses
0
Start with an empty cache - all blocks
initially marked as not valid
Time
01
00
00
00
00
Time
•
6/27/2016
00 Mem(0)
00 Mem(1)
4 miss
4
Mem(0)
Mem(1)
Mem(2)
Mem(3)
2
3
4
3
4
15
0000 0001 0010 0011 0100 0011 0100 1111
1 miss
2 miss
3 miss
0 miss
00 Mem(0)
1
00 Mem(0)
00 Mem(1)
00 Mem(2)
3 hit
01
00
00
00
Mem(4)
Mem(1)
Mem(2)
Mem(3)
4
01
00
00
00
00
00
00
00
hit
Mem(4)
Mem(1)
Mem(2)
Mem(3)
Mem(0)
Mem(1)
Mem(2)
Mem(3)
15 miss
01
00
00
11 00
Mem(4)
Mem(1)
Mem(2)
Mem(3)
15
8 requests, 6 misses
Spring 2011 -- Lecture #11
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Taking Advantage of Spatial Locality
• Let cache block hold more than one byte
0
Start with an empty cache - all blocks
initially marked as not valid
3 hit
00 Mem(1) Mem(0)
00 Mem(3) Mem(2)
01
•
3
4
3
4
15
00 Mem(1) Mem(0)
00 Mem(1) Mem(0)
00 Mem(3) Mem(2)
4 miss
00 Mem(1)5 Mem(0) 4
00 Mem(3) Mem(2)
3 hit
01 Mem(5) Mem(4)
00 Mem(3) Mem(2)
4 hit
01 Mem(5) Mem(4)
00 Mem(3) Mem(2)
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2
0000 0001 0010 0011 0100 0011 0100 1111
1 hit
2 miss
0 miss
00 Mem(1) Mem(0)
1
8 requests, 4 misses
15 miss
01 Mem(5) Mem(4)
11
00 Mem(3) Mem(2)
15
14
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Miss Rate vs Block Size vs Cache Size
Miss rate (%)
10
8 KB
16 KB
64 KB
5
256 KB
0
16
32
64
128
256
Block size (bytes)
•
Miss rate goes up if the block size becomes a significant fraction
of the cache size because the number of blocks that can be held
in the same size cache is smaller (increasing capacity misses)
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Spring 2011 -- Lecture #11
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Agenda
•
•
•
•
•
•
Memory Hierarchy Overview and Analogy
Administrivia
Direct Mapped Caches
Break
Direct Mapped Cache Example
Cache Performance
6/27/2016
Spring 2011 -- Lecture #11
37
Average Memory Access Time (AMAT)
• Average Memory Access Time (AMAT) is the average to
access memory considering both hits and misses
AMAT = Time for a hit + Miss rate x Miss penalty
• What is the AMAT for a processor with a 200 psec clock, a
miss penalty of 50 clock cycles, a miss rate of 0.02 misses
per instruction and a cache access time of 1 clock cycle?
1 + 0.02 x 50 = 2 clock cycles
Or 2 x 200 = 400 psecs
• Potential impact of much larger cache on AMAT?
1) Lower Miss rate
2) Longer Access time (Hit time): smaller is faster
Increase in hit time will likely add another stage to the pipeline
At some point, increase in hit time for a larger cache may overcome
the improvement in hit rate, yielding a decrease in performance
6/27/2016
Spring 2011 -- Lecture #12
38
Measuring Cache Performance – Effect
on CPI
• Assuming cache hit costs are included as part of the normal CPU execution
cycle, then
CPU time = IC × CPI × CC
= IC × (CPIideal + Average Memory-stall cycles) × CC
CPIstall
•
A simple model for Memory-stall cycles
Memory-stall cycles = accesses/instruction × miss rate × miss
penalty
•
6/27/2016
Will talk about writes and write misses next lecture, where its
a little more complicated
Spring 2011 -- Lecture #12
39
Impacts of Cache Performance
• Relative $ penalty increases as processor performance
improves (faster clock rate and/or lower CPI)
– Memory speed unlikely to improve as fast as processor
cycle time. When calculating CPIstall, cache miss penalty is
measured in processor clock cycles needed to handle a
miss
– Lower the CPIideal, more pronounced impact of stalls
• Processor with a CPIideal of 2, a 100 cycle miss penalty,
36% load/store instr’s, and 2% I$ and 4% D$ miss rates
– Memory-stall cycles = 2% × 100 + 36% × 4% × 100 = 3.44
– So
CPIstalls = 2 + 3.44 = 5.44
– More than twice the CPIideal !
• What if the CPIideal is reduced to 1?
• What if the D$ miss rate went up by 1%?
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Spring 2011 -- Lecture #12
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“And In Conclusion..”
• Principle of Locality
• Hierarchy of Memories (speed/size/cost per
bit) to Exploit Locality
• Direct Mapped Cache – Each block in memory
maps to one block in the cache.
– Index to determine which block.
– Offset to determine which byte within block
– Tag to determine if it’s the right block.
• AMAT to measure cache performance
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