CALIFORNIA STATE UNIVERSITY, NORTHRIDGE
DESIGN OF TWO STAGE MICROWAVE AMPLIFIER AT 10 GHZ
A graduate project submitted in partial fulfillment of the requirements
For the degree of Master of Science
In Electrical Engineering
By
Dheekshitha Puliyadi Rameshbapu
December 2015
The Graduate Project of Dheekshitha Puliyadi Rameshbapu is approved:
Dr. Ramin Roosta
Date
Dr. Benjamin Mallard
Date
Dr. Matthew M. Radmanesh, Chair
Date
California State University, Northridge
ii
Acknowledgement
I would like to express my gratitude and appreciation to, all those who gave me the opportunity
to complete this report.
I would like to express my special appreciation and sincere gratitude to Dr. Matthew Radmanesh.
He has been a great mentor and a great inspiration for me. My attitude towards learning and to
achieve a better understanding of the subject has changed after taking courses under him. It was
an honor for me to work under his supervision. . He has always made efforts to go through my
project and help me improving my knowledge in every aspect.
I would like to thank Dr.Ramin Roosta and Dr.Benjamin Mallard for providing their valuable
suggestions.
I would also like to thank the Department of Electrical and Computer Engineering for providing
the facilities to complete this project.
Also, I thank almighty, my husband, my parents, my in-laws, brothers, sisters and friends for
their constant encouragement without which this assignment would not be possible.
iii
Table of Contents
Signature page ................................................................................................................................. ii
Acknowledgement .......................................................................................................................... iii
List of Figures ................................................................................................................................... v
List of Table .................................................................................................................................... vii
ABSTRACT...................................................................................................................................... viii
CHAPTER 1: INTRODUCTION ............................................................................................................ 1
CHAPTER 2: DC-CIRCUIT BIASING .................................................................................................... 3
2.1 Classes of Amplifiers Based On Operating Point ...................................................................... 3
2.2 Small Signal Analysis................................................................................................................. 4
2.3 DC-Bias Circuit Design .............................................................................................................. 4
2.3.1 FET Biasing ........................................................................................................................ 5
CHAPTER 3: AMPLIFIER DESIGN ....................................................................................................... 8
3.1 Transistor Selection .................................................................................................................. 8
3.2 Stability..................................................................................................................................... 9
3.2.1 K-∆ Test ................................................................................................................................. 9
3.2.2 µ- Parameter Test........................................................................................................... 10
CHAPTER 4: MINIMUM NOISE AMPLIFIER DESIGN ........................................................................ 11
4.1 Matching Network ................................................................................................................. 11
4.2 Minimum Nosie Amplifier Gain Calculation ........................................................................... 17
CHAPTER 5: MAXIMUM GAIN AMPLIFIER DESIGN......................................................................... 18
5.1 Unilateral Figure of Merit....................................................................................................... 18
5.2 Matching Network ................................................................................................................. 19
CHAPTER 6: TWO STAGE AMPLIFIER DESIGN ................................................................................ 25
6.1 Overall Noise Figure of Two Sage Amplifiers ......................................................................... 25
6.2 Complete Amplifier Schematic (RF and DC) ........................................................................... 26
CHAPTER 7: SIMULATION............................................................................................................... 28
CHAPTER 8: CONCLUSION .............................................................................................................. 63
REFERENCE ..................................................................................................................................... 65
Appendix A ..................................................................................................................................... 66
Appendix B ..................................................................................................................................... 80
Appendix C ..................................................................................................................................... 90
iv
List of Figures
Figure 1: Two Stage Amplifier Schematic ..................................................................................................... 2
Figure 2: NE 3210S01 Transistor Characteristics [8] ..................................................................................... 4
Figure 3: FET Biasing Circuit [1] ..................................................................................................................... 7
Figure 4: The Concept of Matching [2] ....................................................................................................... 12
Figure 5: MNA Input Lumped Elements ...................................................................................................... 14
Figure 6: MNA Output Lumped Elements ................................................................................................... 16
Figure 7: MGA Input Lumped Elements ...................................................................................................... 21
Figure 8: MGA Output Lumped Elements ................................................................................................... 23
Figure 9: Complete Amplifier Schematic (RF and DC)................................................................................. 27
Figure 10: RFMW Design Essential Stability Result ..................................................................................... 28
Figure 11: S-Parameter Simulation of NE3210S01 ..................................................................................... 29
Figure 12: S-Parameter Simulation Result .................................................................................................. 30
Figure 13: Stability Table............................................................................................................................. 30
Figure 14: Simulation Result for Stability and mag (delta) ......................................................................... 31
Figure 15: S-parameter Plot ........................................................................................................................ 32
Figure 16: VSWR of the Transistor .............................................................................................................. 33
Figure 17: Noise Figure of the Transistor .................................................................................................... 34
Figure 18: Minimum Noise Amplifier RFMW .............................................................................................. 35
Figure 19 : Amplifier Specification .............................................................................................................. 36
Figure 20: Parameter Check ........................................................................................................................ 36
Figure 21: MNA Input Matching Network .................................................................................................. 37
Figure 22: MNA Output Matching Network ............................................................................................... 38
Figure 23: Minimum Noise Amplifier (MNA) Design .................................................................................. 39
Figure 24: MNA Input matching Solution 1 with ADS ................................................................................. 40
Figure 25: MNA Input Matching Solution 2 with ADS................................................................................. 41
Figure 26: MNA Output Matching Solution1 with ADS............................................................................... 42
Figure 27: MNA Output Matching Solution 2 with ADS .............................................................................. 43
Figure 28: Power Gain of MNA ................................................................................................................... 44
Figure 29: Noise Figure of MNA .................................................................................................................. 45
Figure30: Overall Noise of MNA ................................................................................................................. 46
Figure 31: Maximum Gain Amplifier Main Page RFMW Essential .............................................................. 47
Figure 32: MGA Amplifier Specification ...................................................................................................... 47
Figure 33: Unilateral Gain Calculations ....................................................................................................... 48
Figure 34: MGA Input Matching Network with RFMW Essentials .............................................................. 48
Figure 35: MGA Output Matching Network with RFMW Essentials ........................................................... 49
Figure 36: Maximum Gain Amplifier (MGA) Design.................................................................................... 50
Figure 37: MGA Input Matching With ADS ................................................................................................. 51
Figure 38: MGA Output Matching with ADS ............................................................................................... 52
Figure 39: Power Gain of MGA ................................................................................................................... 53
Figure 40: Overall Noise of MGA................................................................................................................. 54
Figure 41: Noise Figure of MGA .................................................................................................................. 55
v
Figure 42: VSWR of MGA ............................................................................................................................ 56
Figure 43: Two Stage Amplifier Design with ADS........................................................................................ 57
Figure 44: Impedances for M1, M2, M3, M4 Blocks ................................................................................... 58
Figure 45: Power Gain of Two Stage Design ............................................................................................... 59
Figure 46: S-parameter of Two Stage Design.............................................................................................. 60
Figure 47: Noise of Two Stage Design ......................................................................................................... 61
Figure 48: VSWR of Two Stage Design ........................................................................................................ 62
Figure 49: Minimum Noise Amplifier Input Elements Solutions ................................................................ 82
Figure 50: Minimum Noise Amplifier Output Elements Solutions.............................................................. 84
Figure 51: Maximum Gain Amplifier Input Elements Solutions.................................................................. 86
Figure 52: Maximum Gain Amplifier Output Elements Solutions............................................................... 89
vi
List of Table
Table 1: Comparison of Numerical values and Simulated Value…………………………….….63
vii
ABSTRACT
DESIGN OF TWO STAGE MICROWAVE AMPLIFIER AT 10 GHZ
By
Dheekshitha Puliyadi Rameshbapu
Master of Science in Electrical Engineering
This project is to design a two stage microwave amplifier with an overall gain of 29 dB and an
overall noise figure less than or equal to 1 dB. The two stage microwave amplifier design
consists of a Minimum Noise Amplifier Stage (MNA) followed by a Maximum Gain Amplifier
Stage (MGA). For the amplifier design, I have used the RFMW essentials software which is
provided by my professor Matthew M. Radmanesh, which helps to calculate the baseline
solution, which is later used to design the two stage amplifier. Along with that I have used
Agilent Technologies ‘Advanced Design System Software (ADS)’ to design the amplifier and
also to calculate the required values for impedance matching. I have performed the simulations
for the two stage amplifier design. I have used the transistor NE 3210S01 from NEC vendor for
the two stage amplifier design. After transistor selection, I have calculated the DC biasing circuit
for the two stage amplifier design. Then each stage is calculated using the ADS software and the
results are displayed in the report individually for minimum noise stage and maximum gain
stage. Then I have cascaded the two circuits and have achieved the overall gain of the project as
28.3dB and an overall noise figure of 0.8dB. Along with that VSWR, overall noise, S-parameter
sweep and power gain simulation results of two stage amplifier design is simulated.
viii
CHAPTER 1: INTRODUCTION
An amplifier is the basic element for a wireless communication system. The applications
of amplifiers are universal. “In this design, my goal is to design a two stage amplifier and
achieve an overall gain of 29 dB and an overall noise figure of 1dB or less at 10GHz”.
The two stage amplifier design consists of a Minimum noise Amplifier stage and a
Maximum Gain Amplifier stage.
In RF/Microwave amplifier, the existence of noise plays a very important role in the
overall design procedure and hence need to be reduced as much as possible before a
design process is developed. “Minimum Noise Amplifier is a special case of a ‘Low
Noise Amplifier (LNA)’ where, the noise figure circles are reduced to a single point and
thus the design process is reduced to a single design choice” [4]. The main aim of a
Minimum Noise Amplifier is reducing the noise of the signal and also makes sure that
there are no alterations in the original characteristics of that signal.
“The second stage is the Maximum Gain Amplifier (MGA), which is a special case of
‘High Gain Amplifier (HGA)’ design where, the input and output gain circles are reduced
to single points and thus the design is reduced to a single design choice”[4].
Based on the microwave amplifier specifications for this project, NE3210S01, ‘a super
low noise amplifier N-channel HJ-FET’ device is chosen.
The transistor is then biased, which is used to drive the FET. The stability conditions at
the required frequency are checked with the S parameters value taken from the data sheet.
Once the conditions are met, the appropriate reflection coefficient 𝛤OPT is chosen to
determine the 𝛤s and 𝛤l in case of a minimum noise amplifier to achieve the minimum
noise and for best VSWR at the output. In case of the Maximum Gain Amplifier, 𝛤s and
𝛤l are chosen as the complex conjugate of S11 and S22 in order to achieve the maximum
gain. Thus, with the help of the matching networks, lumped elements for each stage are
calculated.
1
The gain and noise figure for each stage is calculated with the matching network. The
overall gain of the cascaded amplifier design is calculated by multiplying the gain of each
stage and the results are plotted and verified. For the design process, ADS software is
used and the project is done theoretically with no practical implementations.
Figure 1, shows the two stage amplifier design schematic. M1 is the input matching
network of the first stage (MNA) and M2 is the output matching network of the first stage
(MNA). Similarly, M3 is the input matching network of the second stage (MGA) and M4
is the output matching network of the second stage (MGA).
Figure 1: Two Stage Amplifier Schematic
2
CHAPTER 2: DC-CIRCUIT BIASING
Among electronic circuits, signal amplification is the most important radiofrequency
(RF) and microwave circuit functions. In recent times, the wireless communication
revolution had provided an explosion of RF and microwave applications. Major benefits
of transistor amplifiers versus tube amplifiers are smaller size, lighter weight, and higher
reliability, a high level of integration capability, high-volume, high-yield production
capability, greater design flexibility, lower supply voltages, reduced maintenance and
unlimited application diversity. Transistors have much longer operating life and require
much lower warming time. Nowadays, uses of microwave transistors (BJTs and FETs)
have become popular.
2.1 Classes of Amplifiers Based On Operating Point
Historically, amplifier class designations were related to the biasing of amplifier devices,
1. Class A: In this mode, each transistor in the amplifier operates in the active region
for each cycle. This is the biasing scheme used in this project.
2. Class B: In this mode, each transistor is in the active region for approximately
half of the cycle.
3. Class AB: In this mode, an amplifier operates in class A for small signals and in
class B for large signals.
4. Class C: In this mode, each transistor is in active region for less than half of the
signal cycle. They are used in radio-frequency applications.
5. Class D: It’s found in audio application. In vehicles, where it achieves high output
levels, or in personal audio devices, where its efficiency contributes to long
battery life.
3
2.2 Small Signal Analysis
According to the signal level, amplifiers are classified as small signal mode and large
signal mode. In small signal analysis, “the active circuit in which it is assumed that the
signals deviate from the steady bias levels by such a small amount that only a small part
of the operating characteristic of the device is covered and thus the operation is always
linear”[4]. For small signal amplifier design, the biasing values of the transistor is
determined first and connect the DC circuitry correctly to the RF portion of the amplifier.
Design of an amplifier consists of two separate circuits:
a. DC Circuit Design
b. RF/MW Circuit Design.
2.3 DC-Bias Circuit Design
In this amplifier design process we are using an FET transistor. At higher frequencies the
device of choice is N-channel type, since the electrons being the main charge carriers
have higher mobility and thus high speed. It has three components: source, drain and
gate. The resistance of the current path from the source to drain is controlled by applying
a voltage to the gate electrode by varying the depletion layer under the gate area and thus
reducing or increasing the conductance of the path. FET’s gate input impedance is very
large and the current through the gate for all practical purpose can be considered to be
zero.
Figure 2: NE 3210S01 Transistor Characteristics [8]
4
2.3.1 FET Biasing
The following are the steps involved in FET biasing.

Gate to source junction is always reverse biased in a FET

Gate has to be at a negative voltage compared to source for N-channel

Drain to source DC supply is positive to enable majority carriers to flow from
source to drain

A separate negative supply or alternatively a resistance (RS) is placed in the
source lead

The current from drain to source (ID) would develop a voltage across RS with the
source end being positive

The gate is connected to the other end of RS making it negative with respect to the
source end

Gate current of FET is zero

Sometimes a large value of RS is required for better stability which thus increases
the supply voltage for suitable value of VDS and RD

To avoid this and have more flexibility in choosing RS a supply voltage VGG is
used at the gate

Since VGG is positive and gate current is zero, it can be derived from VDD with the
help of potential divider
FET biasing values from data sheet are as follows:
Drain current ID = 10 mA
Drain to source voltage VDS = 2V
Gate to source voltage VGS = -3V
Threshold Voltage Vt = -0.7 V
Saturated Drain Current IDSS = 40mA
5
The FET biasing equations are discussed as follows.
IDSS = K Vt2
K=
𝐼𝐷𝑆𝑆
𝑉𝑡2
=
40
0.49
= 81.63mA/V2
Thus the value of K is calculated to be 81.63mA/V2
From the voltage divider rule we have,
VDD = RD ID + VDS + RS ID
Assume VDD = 17V and RS = 0.5KΩ
RD =
RD =
𝑉𝐷𝐷 − 𝑉𝐷𝑆
- RS
𝐼𝐷
17−2
10
- 0.5K
RD = 1KΩ
The resistance R1 and R2 are calculated as follows
VS = RS ID = 5V
The gate voltage is calculated as follows
VGS = VG – VS
VG = VGS + VS
VG = -3+5 = 2V
VG = VDD (
VG = VDD (
𝑅2
𝑅1 +𝑅2
1
𝑅
1+ 𝑅1
)
)
2
6
(
1
𝑅
1+ 𝑅1
2
𝑅1
𝑅2
)=
2
17
= 7.5
Assume R1 =100 KΩ and R2 = 13.3 KΩ
The biasing circuit for FET is shown in figure 3.
Figure 3: FET Biasing Circuit [1]
7
CHAPTER 3: AMPLIFIER DESIGN
The next step is amplifier design. The following steps are performed in order to achieve
the required amplifier design.
As mentioned earlier, the transistor selected for the design is NE 3210S01 FET. The S
parameters of the transistor are selected at 10GHz, since we are designing the amplifier
for the 10GHz.
3.1 Transistor Selection
Based on the amplifiers specifications, “it is important to select an appropriate device
such that, if the gain (G) is given we have to choose a transistor with typical
ǀ𝑆21 ǀ
ǀ𝑆12 ǀ
> G that
is in the desired frequency range” [4].
Alternatively, if the noise figure (FO) is given, we have to make sure that it is greater than
the Fmin of the selected transistor, i.e., FO > Fmin [4].
The transistor is selected if it satisfies the following condition:
ǀ
𝑆21
𝑆12
ǀ > Specified Gain (G)
Based on the microwave amplifier specifications for this project, NE3210S01, a super
low noise amplifier N-channel HJ-FET device is chosen.
4.063
ǀ0.086 ǀ = 47.244 = 16.7dB > 29/2 = 14.5 dB (the desired gain)
Thus for a two stage design, a maximum of 33dB gain is available and an overall noise
figure of 1dB.
From the data sheet, for 10 GHz frequency, the respective S parameters are taken. The
data sheet NE321S01 is attached in the appendix (A).
8
Thus the values satisfy the condition,
ǀ𝑆21 ǀ
ǀ𝑆12 ǀ
> G. The next step is to calculate the stability
of the device. The transistor selected for the design is operating at an optimal operating
point at VDS = 2V and ID = 10 mA. The S parameters of the transistor are run with the
ADS software to verify if the values obtained are matching with the data sheet of
NE321S01. They are terminated with 50Ω terminations in the input and output port. The
S-parameter result is obtained when the ADS simulation is performed. The values match
with the data sheet provided in the appendix A.
3.2 Stability
In any amplifier design, one of the very important considerations is the stability of the
circuit under different source and load conditions. Stability is defined as, “the ability of
an amplifier to maintain its effectiveness in spite of large changes in the environment
such as temperature, frequency, source and load conditions, etc., in its normal operating
point”[4]. In order to determine the stability of a FET, three steps are performed. They
are the K-∆ test and the µ- parameter test.
3.2.1 K-∆ Test
At the required frequency the stability of K and ∆ of the selected transistor is first
checked.
∆ = S11 S22 – S12 S21
∆ = [(0.554∠−127.2𝜊 )*(0.268∠−86.8𝜊 )] – [(0.086∠18.9𝜊 )*(4.063∠51.3𝜊 )]
∆ = 0.344∠−134.49𝜊
By substituting the S-parameter values of the transistor, ∆ = 0.344∠−134.49𝜊
K=
K=
1−ǀ𝑆11 ǀ2 −ǀ𝑆22 ǀ2 +ǀ∆ǀ2
2ǀ𝑆12 𝑆21 ǀ
1−ǀ0.5542 ǀ−ǀ0.2682 ǀ+ǀ0.3442 ǀ
2ǀ0.086∗4.063ǀ
= 1.058
9
When substituting the values in the above equation we get K=1.058
Thus we have ∆<1 and K>1. By meeting this condition we can conclude that the
transistor is unconditionally stable.
The results are verified with the help of the software as well. When simulated, we get the
values of the delta and k and they are tabulated. Thus, the transistor selected at 10 GHz is
unconditionally stable.
3.2.2 µ- Parameter Test
To determine the unconditional stability of the device as well as its degree of stability to
other devices, a new criterion has been derived that combines K-∆ parameter into a single
parameter test and is often referred to as the µ-parameter test. The parameter µ is defined
as:
µ=
1−ǀ𝑆11 ǀ2
∗ ∆ǀ+ǀ𝑆 𝑆 ǀ
ǀ𝑆22 −𝑆11
21 12
= 1.068
In this case the value is found to be, µ=1.068 >1
Thus the device is unconditionally stable.
By plugging in the values of the S-parameters, it is evident that the device is
unconditionally stable with the help of RFMW design essential software and ADS.
The Stability factor and the magnitude of delta are simulated and the graph is obtained.
The transistor S-parameter plot is also simulated with the help of the ADS software. Also,
the VSWR and the noise figure of the selected transistor are simulated and the results are
obtained with the help of the ADS software.
10
CHAPTER 4: MINIMUM NOISE AMPLIFIER DESIGN
“Minimum Noise Amplifier (MNA) design is a special case of Low Noise Amplifier
(LNA) design where the noise figure circles are reduced to a single point ( 𝛤opt) and thus
the design process is reduced to a single design choice”[4].
From the data sheet attached in the appendix A, the value of the reflection coefficient is
taken. For minimum noise amplifier design, the source reflection coefficient is taken as
the optimum reflection coefficient in order to get best VSWR at the output.
𝛤S = 𝛤OPT
The load reflection coefficient is calculated using the following formula
𝑆12 𝑆21 𝛤𝑂𝑃𝑇
𝛤L = 𝛤OUT* = (S22 +
1−𝑆11 𝛤𝑂𝑃𝑇
)*
Once the value of the source reflection coefficient and the load reflection coefficient are
calculated, the input and output matching networks can be designed.
At 10GHz the S- parameters for the transistor is
S=[
𝑆11
𝑆21
𝑆12
0.554 ∠−127.2𝜊
]=[
𝑆22
4.063∠51.3𝜊
0.086∠18.9𝜊
]
0.268∠ − 86.8𝜊
With the S-parameter values, the source and load reflection coefficient values are
calculated
𝛤S = 0.38∠97𝜊 Ω = 34.5+j30.5 Ω
𝛤L = 0.251 ∠ 122.6𝜊 Ω = 35.13+j15.85 Ω
4.1 Matching Network
“Matching is defined to be connecting two circuits (source and load) together via a
coupling device or network in such a way that the maximum transfer of energy occurs
11
between two circuits. This concept of impedance matching is also called as tuning, and it
is a very important concept in RF/Microwave frequencies since it allows:

Maximum power transfer to occur from source to load and,

Signal to noise ratio to be improved because matching causes an increase in the
signal level” [4].
The most important design used in amplifier and oscillator design is shown as follows.
Figure 4: The Concept of Matching [2]
With the help of RFMW software, the matching network can be calculated. The input
matching network is derived by moving from the center of smith chart to the source
reflection coefficient. In Minimum noise amplifier design the source reflection
coefficient is equal to the optimum reflection coefficient, which is taken from the data
sheet. In this case the load is located outside the unit conductance and the resistance unity
circle. There are four solutions possible, and for this design series C and shunt L (solution
1) is selected.
Solution 1: Series C and Shunt L
Series C1: jXS =
j(-0.5) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶1 (50)
12
C1 = 0.636pF
Shunt L1: jBP =
j(-1.0) =
−𝑗
𝜔𝐿𝑌𝑜
−𝑗
(2𝜋10∗109 )𝐿1 (0.02)
L1 = 0.796nH
The lumped elements are calculated from the smith chart and are shown in figure 5.
Additionally, they are verified with the smith chart tool available in ADS software. The
other three solutions are discussed in appendix B.
13
Solution 1
Figure 5: MNA Input Lumped Elements
14
The output matching network is derived by moving from the center of the smith chart to
the load reflection coefficient. In Minimum noise amplifier design, the load reflection
coefficient is derived with the help of the following equation. In this case the load is
located inside the unit conductance. In this case, there are two solutions possible.
𝛤L = ( S22 +
𝑆21 𝑆12 𝛤𝑂𝑃𝑇
1−𝑆11 𝛤𝑂𝑃𝑇
)*
𝛤L = 0.251 ∠ 122.6𝜊 Ω
Solution 1: Shunt C and Series L
𝑗𝜔𝐶
Shunt C2: jBP =
j(0.65) =
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶2
(0.02)
C2 = 0.207pF
Series L2: jXS =
j(0.94) =
𝑗𝜔𝐿
𝑍𝑜
𝑗(2𝜋10∗109 )𝐿2
(50)
L2 = 0.754nH
For this design, the shunt C and series L (solution 1) lumped element design is chosen for
the output matching network and the values are calculated from the smith chart and are
shown in figure 6. The second solution is discussed in appendix B.
15
Solution 1
Figure 6: MNA Output Lumped Elements
16
4.2 Minimum Nosie Amplifier Gain Calculation
For the Minimum noise amplifier stage, we have terminated with a 50Ω source and load.
With the results of the input and output matching networks, shunt C and series L is
selected for the input matching network and shunt L and series C for the output matching
network. The matching networks are made up of passive components and have no
inherent gain, thus are incapable of generating power. Since input and output matching
networks are capable of increasing the degree of match in the circuit as the signal flows
through, they can be considered to have a positive gain in a relative manner.
The overall gain can be calculated as follows:
GT =
1−ǀ𝛤𝑠 ǀ
2
2 ǀS21ǀ
ǀ1−𝛤𝐼𝑁 𝛤𝑠 ǀ
1−ǀ𝛤𝐿 ǀ
ǀ1−𝑆22 𝛤𝐿 ǀ2
The above equation can be written as:
GT = GS*Go*GL = 21.9 = 13.12(dB)
Where
GS =
GL =
1−ǀ𝛤𝑠 ǀ
ǀ1−𝛤𝐼𝑁 𝛤𝑠 ǀ2
1−ǀ𝛤𝐿 ǀ
ǀ1−𝑆22 𝛤𝐿 ǀ2
= 1.283 (ratio)
= 0.1965 (ratio)
2
Go = ǀS21ǀ = 16.5 (ratio)
𝛤IN =S11 +
𝑆12 𝑆21 𝛤𝐿
1−𝑆22 𝛤𝐿
= 0.6299 ∠−132.35𝜊 Ω
The overall gain of the minimum noise amplifier is calculated as 13dB.
The minimum noise amplifier (MNA), provides a gain of 13dB and an overall noise of
0.669dB which is a very good design, as the goal is achieved, which is the minimum
noise.
17
CHAPTER 5: MAXIMUM GAIN AMPLIFIER DESIGN
Gain consideration in an amplifier plays an important role in the design process. In order
to obtain maximum gain, ‘input and output matching networks are simultaneously
conjugated to the transistor’. Also, the entire amplifier system has to be matched to the
system impedance. “Maximum Gain Amplifier design is a special case of a High Gain
Amplifier design where the input and output gain circles are reduced to a single point and
thus the design process is reduced to a single design choice” [4]. In order to achieve this
condition, the following two conditions should be met:
𝛤S = 𝛤IN*
𝛤L = 𝛤OUT*
5.1 Unilateral Figure of Merit
The next step in the amplifier design process is to check unilateral or bilateral analysis. In
this case S12 ≠ 0, hence I have used unilateral design formulas.
U=
ǀ𝑆12 ǀ ǀ𝑆21 ǀ ǀ𝑆11 ǀ ǀ 𝑆22 ǀ
(1−ǀ𝑆11 ǀ2 )(1−ǀ𝑆22 ǀ2 )
U=
ǀ0.086ǀ ǀ4.063ǀ ǀ0.554ǀ ǀ0.268ǀ
(1−ǀ0.554ǀ2 )(1−ǀ0.268ǀ2 )
U = 0.08064
Where, “U is defined as the Unilateral Figure of Merit” which varies with frequency due
to its S-parameter dependence. When 𝛤S = S11* and 𝛤L = S22*, GTU achieves its maximum
value, GTU, max. Thus, the maximum error introduced using unilateral assumption is given
by,
1
(1+𝑈)2
<
𝐺𝑇
𝐺𝑇𝑈,𝑚𝑎𝑥
<
1
(1−𝑈)2
18
0.9936 <
-0.086 <
𝐺𝑇
𝐺𝑇𝑈,𝑚𝑎𝑥
𝐺𝑇
𝐺𝑇𝑈,𝑚𝑎𝑥
<1.0064
< 0.087 (in dB)
The error is tolerable using the unilateral assumption because GTU, max = 14.16dB. The
selected transistor provides the required maximum gain. Therefore, we can use the
following conditions:
𝛤S = S11*
𝛤L = S22*
These two conditions provide maximum transducer gain (GTU, max):
GTU, max = GS, max * Go* GL, max
Where
GS, max =
GL, max =
1
1−ǀ𝑆11 ǀ2
1
1−ǀ𝑆22 ǀ2
= 1.443 (ratio) = 1.59dB
= 1.0774 (ratio) = 0.3237 dB
Go = ǀS22ǀ2 = 16.508 (ratio) = 12.177dB
Thus the transducer gain is calculated as GTU, max = 14.16dB
5.2 Matching Network
The source and the load reflection coefficients are used to calculate the matching network
for maximum gain amplifier design. An Input network is designed by moving from the
center of the smith chart to the source reflection coefficient and they are calculated with
the help of the smith chart shown in figure 7. It has two possible solutions:
19
Solution 1: Shunt L and Series C
Shunt L3: jBP =
j(-1.4) =
−𝑗
𝜔𝐿𝑌𝑜
−𝑗
(2𝜋10∗109 )𝐿3 (0.02)
L3 = 0.568nH
Series C3: jXS =
j(-0.94) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶3 (50)
C3 = 7.96pF
The second solution is discussed in appendix B.
20
Solution 1
Figure 7: MGA Input Lumped Elements
21
Similarly, the output matching network is designed by moving from the center of the
smith chart toward the load reflection coefficient on the smith chart as shown in figure 8.
It has four possible solutions where we have selected solution 1 as follows:
Solution 1: Series C and Shunt L
Series C4: jXS =
j(-0.42) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶4 (50)
C4 = 6.3pF
Shunt L4: jBP =
j(-1.0) =
−𝑗
𝜔𝐿𝑌𝑜
−𝑗
(2𝜋10∗109 )𝐿4 (0.02)
L4 = 0.796nH
Other three solutions are discussed in appendix B.
22
Solution 1
Figure 8: MGA Output Lumped Elements
23
The overall circuit design for maximum gain amplifier is designed with the help of ADS
software. With the values of the input and output matching networks calculated before,
the circuit is run with the help of the ADS software to calculate the overall gain of the
maximum gain amplifier design and also the noise figure of the circuit.
The unilateral gain calculation shows that the gain of the maximum gain amplifier design
is calculated as 14.16dB. When the graph is plotted with the help of the ADS software, a
power gain of 14.37dB is achieved.
Similarly, the overall noise figure of the maximum gain amplifier design is also plotted
with the help of ADS.
24
CHAPTER 6: TWO STAGE AMPLIFIER DESIGN
6.1 Overall Noise Figure of Two Sage Amplifiers
“Noise is passed into a microwave component or system, either from external source or is
generated within the unit itself” [4]. The design consists of two stage network connected
in cascade where each adds noise to the system, thus degrading the overall signal-to-noise
ratio. If the noise figure of each stage is known, the overall noise figure can be
determined. The noise figure for the two stage amplifier design is given by:
FCAS = F1 +
𝐹2 −1
𝐺𝐴1
Where F1 = Noise Figure of first stage
F2 = Noise Figure of second stage
GA1 = Gain of the first stage
The noise figure of first stage is the minimum noise figure of the transistor.
In this case, F1 = Fmin = 0.32 dB = 1.076 (ratio)
GA1 = 13 dB = 19.95 (ratio)
F2= Fmin +
Where N=
N=
4 𝑟𝑛 𝑁
ǀ1+𝛤𝑜𝑝𝑡ǀ 2
ǀ𝛤𝑠 −𝛤𝑜𝑝𝑡ǀ ǀ2
1−ǀ𝛤𝑠 ǀ2
ǀ0.554−0.38 ǀ2
1−ǀ0.554ǀ2
= 0.0436
From the data sheet [appendix A] we have rn = 0.11
F2 = 1.076 +
4 (5.5)(0.0436)
(1+0.38)2
= 1.186
25
The noise figure of the cascaded network is
FCAS = 1.076 +
1.186−1
19.95
FCAS = 1.1853 (ratio) = 0.738 dB
Thus, the two stage amplifier design yields a power gain of 28.3dB and the overall noise
of 0.738dB at 10 GHz. The VSWR of the two stage amplifier design is also improved.
6.2 Complete Amplifier Schematic (RF and DC)
“It is essential that the amplifier’s bias circuitry be connected to the RF circuit in such a
way that it will; create minimum interaction and leakage for the RF/microwave signals.
To successfully achieve such a task, we use several schemes which can be briefly stated
as follows:
1.) Connect an RF choke (RFC), between the DC source and RF/MW circuitry that is
actually an inductor that allows low frequency or DC to pass through, but blocks all high
frequency signals such as RF signals.
2.) Connect a high impedance quarter-wave transformer between the DC source and the
RF circuitry. The characteristic impedance of the transformer should be high enough to
create a high impedance path for travelling RF signals.
3.) Connect high value capacitors as loads to short the residual RF/MW signals that might
leak into the DC circuitry. These high value capacitors create an open circuit at the input
end of the RF circuit” [4].
Combination of all these schemes will guarantee a high degree of isolation. The complete
amplifier schematic with RF and DC is shown in figure 9.
26
Figure 9: Complete Amplifier Schematic (RF and DC)
27
CHAPTER 7: SIMULATION
With the help of ‘RF and Microwave E-book’ software provided by Dr. Matthew
Radmanesh, I was able to perform some baseline solutions, which helped to verify the
values calculated manually. The screenshot of the results have been provided. Figure 10,
checks for the stability of the transistor NE3210S01 which has been selected for this
design.
Figure 10: RFMW Design Essential Stability Result
28
The transistor selected for the design, NE 3210S01, is a low noise FET. Agilent
technologies have collaborations with NEC, so this particular transistor is found in the
Agilent library. The device characteristics are now found out which are shown in figure
11.
Figure 11: S-Parameter Simulation of NE3210S01
29
The S-parameters are simulated and the following results are obtained. The values are
found to be exactly the same as provided in the data sheet.
Figure 12: S-Parameter Simulation Result
Figure 13: Stability Table
30
The graph for stability factor for the transistor NE 3210S01 is shown in figure 14.
Figure 14: Simulation Result for Stability and mag (delta)
31
The S- parameter plot for the transistor NE 3210S01 is shown in figure 15.
Figure 15: S-parameter Plot
32
The VSWR graph for the transistor NE 3210S01 is shown in figure 16.
Figure 16: VSWR of the Transistor
33
The noise figure graph for the transistor NE 3210S01 is shown in figure 17.
Figure 17: Noise Figure of the Transistor
34
With the help of the RFMW essential tool the baseline solution for the minimum noise
amplifier stage is calculated. Before the actual circuit is designed, this tool helps to
generate a workable solution to create a base design. Once results are generated, later
ADS software is used to build the circuit design and the results are then simulated. The
snapshots of the MNA design calculations are shown as follows:
Figure 18: Minimum Noise Amplifier RFMW
35
Figure 19 : Amplifier Specification
Figure 20: Parameter Check
36
Figure 21: MNA Input Matching Network
37
Figure 22: MNA Output Matching Network
38
Now the ADS software is used to design the first stage which is the minimum noise
amplifier circuit with the base solution obtained with the RFMW tool. The overall circuit
is shown in figure 23.
Figure 23: Minimum Noise Amplifier (MNA) Design
39
The lumped elements for input and output matching network are simulated with the help
of the smith chart tool available in the ADS software. The results are shown as follows:
Figure 24: MNA Input matching Solution 1 with ADS
40
Figure 25: MNA Input Matching Solution 2 with ADS
41
Figure 26: MNA Output Matching Solution1 with ADS
42
Figure 27: MNA Output Matching Solution 2 with ADS
43
The powergain graph for the minimum noise amplifier stage is shown in figure 28.
Figure 28: Power Gain of MNA
44
The Noise figure (NFMIN) of the minimum noise amplifier stage is shown in figure 29.
Figure 29: Noise Figure of MNA
45
The plot for the overall noise of the minimum noise amplifier stage is shown in figure 30.
Figure30: Overall Noise of MNA
46
Similar to the minimum noise amplifier stage, the RFMW essential tool is used to
calculate the baseline solution for the maximum gain amplifier stage.
Figure 31: Maximum Gain Amplifier Main Page RFMW Essential
Figure 32: MGA Amplifier Specification
47
Figure 33: Unilateral Gain Calculations
Figure 34: MGA Input Matching Network with RFMW Essentials
48
Figure 35: MGA Output Matching Network with RFMW Essentials
49
The design for the second stage, which is the Maximum Gain amplifier, is designed with
ADS software. The input and output matching elements, the gain of MGA, noise figure
and the overall noise for MGA design are simulated and the results are displayed.
Figure 36: Maximum Gain Amplifier (MGA) Design
50
The ADS smith chart tool is used to verify the values of the lumped elements calculated
in chapter 5 and the verified results are displayed below for the input and output
matching networks for maximum gain amplifier stage. The results are shown as follows:
Figure 37: MGA Input Matching With ADS
51
Figure 38: MGA Output Matching with ADS
52
The results of maximum gain amplifier stage are plotted with ADS. The power gain of
the MGA design is shown in figure 39.
Figure 39: Power Gain of MGA
53
The overall noise of maximum gain amplifier stage is shown in figure 40.
Figure 40: Overall Noise of MGA
54
The minimum noise figure (NFmin) of maximum gain amplifier stage is shown in figure
41.
Figure 41: Noise Figure of MGA
55
The VSWR of maximum gain amplifier stage is shown in figure 42.
Figure 42: VSWR of MGA
56
The two stage amplifier design with minimum noise amplifier as the first stage and
maximum gain amplifier as the second stage is designed with ADS and the transistor is
already biased at VDS = 2V and IDS = 10mA. Figure 41 shows the schematic of two stage
design.
Figure 43: Two Stage Amplifier Design with ADS
57
Figure 44 shows the impedances for M1, M2, M3 and M4 blocks for the two stage
design.
Figure 44: Impedances for M1, M2, M3, M4 Blocks
58
The plot for the overall power gain of two stage amplifier design is shown in figure 45.
Figure 45: Power Gain of Two Stage Design
59
The S-parameter plot for the two stage amplifier design is shown in figure 46.
Figure 46: S-parameter of Two Stage Design
60
The noise figure plot of two stage amplifier design is shown in figure 47. The overall
noise of the two stage design is 0.814dB. The specifications for the two stage design have
been met.
Figure 47: Noise of Two Stage Design
61
The plot for the VSWR of two stage amplifier design is shown in figure 48.
Figure 48: VSWR of Two Stage Design
62
CHAPTER 8: CONCLUSION
The design of the two stage amplifier has been shown to successfully meet the
performance criteria. The numerical design and the simulation of this project are shown
in table-1. The numerical calculations and simulated results are comparable.
Parameter
Design Goals
Numerical
Simulated Results
Calculation
ADS
RFMW
Book
Gain
29dB ±1dB
28dB
28.348dB
28.4dB
Noise
≤1dB
0.738dB
0.814dB
0.8dB
ADS refers to Agilent’s ‘Advanced Design System’ software
RFMW Book refers to ‘RF and Microwave Book’ software [4]
Table 1: Comparison of Numerical values and Simulated Values
The transistor was initially checked for stability and was found out to be unconditionally
stable. The two stage design using active bias networks (which is modeled in ADS) has
been designed and simulated. The first stage (MNA) is based on NE321S01 transistor. It
was designed, simulated and tuned for the best possible gain and noise figure. From the
results displayed, it is evident that a gain of 13 dB and a noise figure of 0.669dB can be
achieved.
In order to get a better power gain for the designed MNA, a second stage MGA based on
the same transistor is added in cascade after the first stage. This maximum gain amplifier
(MGA) design provides a gain of 14.205dB. The design has been adjusted using
optimization tools applied to matching networks such that the final design is improved in
both gain and noise figure. The final two-stage amplifier design shows a peak power gain
of 28.3 dB and an excellent noise figure of 0.814 dB. This meets our design
requirements. Also, ADS software provided an accurate method for circuit design and
simulations.
63
Overall, working on this project has helped me to understand amplifier design concepts
at microwave frequencies as well as the overall design process at the industrial level.
64
REFERENCE
[1] http://wps.prenhall.com/chet_paynter_introduct_6/0,5779,426159-,00.html
[2] http://www.globalspec.com/reference/75707/203279/2-6-narrowband-matchingnetworks, 2001.
[3] Matthew M. Radmanesh, ‘Electronic Waves and Transmission Line Circuit
Design’, Bloomington, Indiana, AuthorHouse, 2011
[4] Matthew M. Radmanesh, ‘RF & Microwave Design Essentials: Engineering
Design and Analysis from DC to Microwaves’, Bloomington, Indiana,
Authorhouse,2007
[5] Matthew M. Radmanesh, ‘Advanced RF & Microwave Circuit Design: The
Ultimate Guide to Superior Design’, Bloomington, Indiana, AuthorHouse, 2009
[6] http://www.engr.uky.edu/~gedney/courses/ee523/ADSTutorials.html, May 2009.
[7] http://www.uio.no/studier/emner/matnat/ifi/INF5481/h11/undervisningsmateriale/
ADS.pdf, 2009.
[8] http://search.datasheetcatalog.net/key/3210S01, 2014.
[9] Singla, Shrey. “Design of Three Stage Low noise Microwave Amplifier at 10
GHz”, California State University, Northridge; http://hdl.handle.net/10211.2/2621
65
Appendix A
DATA SHEET
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Appendix B
Lumped Element Possible Solutions
Minimum Noise Amplifier Stage (Stage 1):
a) Input Matching Network Solutions:
When calculating the input lumped elements from smith chart, four possible solutions are
possible. The solution selected for this design is series C and shunt L (solution 1). The
other three solutions are discussed below.
Solution 2: Shunt C and Series L
𝑗𝜔𝐶
Shunt C5: jBP =
j(0.67) =
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶5
(0.02)
C5= 0.213pF
Series L5: jXS =
j(1.08) =
𝑗𝜔𝐿
𝑍𝑜
𝑗(2𝜋10∗109 )𝐿5
(50)
L5 = 0.859nH
Solution 3: Series C and Shunt C
Series C6: jXS =
j(-3.03) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶6 (50)
80
C6 = 0.105pF
Shunt C7: jBP =
j(2.13) =
𝑗𝜔𝐶
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶7
(0.02)
C7= 0.68pF
Solution 4: Shunt C and Series C
Shunt C8: jBP =
j(0.66) =
𝑗𝜔𝐶
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶8
(0.02)
C8 = 0.211pF
Series C9: jXS =
j(-0.146) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶9 (50)
C9 = 2.18pF
The input lumped element values are calculated manually from the smith chart and are
shown in figure 49.
81
Solution 4
Solution 3
Solution 1
Solution 2
Figure 49: Minimum Noise Amplifier Input Elements Solutions
82
b) Output Matching Network Solutions:
Similarly when calculating the output lumped elements from the smith chart, two
solutions are possible. For this design, shunt C and series L (solution 1) is selected. The
other solution for output lumped elements is as follows:
Solution 2: Series C and Shunt L
Series C10: jXS =
j(-0.13) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶10 (50)
C10 = 0.49pF
Shunt L6: jBP =
j(-0.6) =
−𝑗
𝜔𝐿𝑌𝑜
−𝑗
(2𝜋10∗109 )𝐿6 (0.02)
L6 = 1.32nH
The output lumped element values are calculated manually from the smith chart and are
shown in figure 50.
83
Solution 1
Solution 2
Figure 50: Minimum Noise Amplifier Output Elements Solutions
84
Maximum Gain Amplifier Stage (stage 2):
a) Input Matching Network Solutions
For input lumped elements, two solutions are possible. Shunt L and Series C (solution 1)
is chosen for the maximum gain input lumped element design. The other solution is
discussed below.
Solution 2: Shunt C and Series L
Shunt C11: jBP =
j(0.04) =
𝑗𝜔𝐶
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶11
(0.02)
C11= 0.013pF
Series L7: jXS =
j(1.3) =
𝑗𝜔𝐿
𝑍𝑜
𝑗(2𝜋10∗109 )𝐿7
(50)
L7 = 1.035nH
The input lumped element values are calculated manually from the smith chart and are
shown in figure 51.
85
Solution 1
Solution 2
Figure 51: Maximum Gain Amplifier Input Elements Solutions
86
b) Output Matching Network Solutions:
For output lumped element design, four possible solutions are possible. The solution used
for this design is series C and shunt L (solution 1). The other three solutions are discussed
below.
Solution 2: Shunt C and Series L
𝑗𝜔𝐶
Shunt C12: jBP =
j(0.24) =
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶12
(0.02)
C12= 0.076pF
Series L8: jXS =
j(0.6) =
𝑗𝜔𝐿
𝑍𝑜
𝑗(2𝜋10∗109 )𝐿8
(50)
L8 = 0.477nH
Solution 3: Series C and Shunt C
Series C13: jXS =
j(-0.26) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶13 (50)
C13 = 1.22pF
Shunt C14: jBP =
j(0.35) =
𝑗𝜔𝐶
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶14
(0.02)
87
C14= 0.11pF
Solution4: Shunt C and Series C
Shunt C15: jBP =
j(0.1) =
𝑗𝜔𝐶
𝑌𝑜
𝑗(2𝜋10∗109 )𝐶15
(0.02)
C15 = 0.031pF
Series C16: jXS =
j(-0.4) =
−𝑗
𝜔𝐶𝑍𝑜
−𝑗
(2𝜋10∗109 )𝐶16 (50)
C16 = 0.796pF
The output lumped element values are calculated manually from the smith chart and are
shown in figure 52.
88
Solution 4
Solution 3
Solution 1
Solution 2
Figure 52: Maximum Gain Amplifier Output Elements Solutions
89
Appendix C
S2P Data file Used
NEC Compound Semiconductor Devices Ltd.
16. July 2002
NE3210S01
N-channel HJ-FET
Vds = 2V Id = 10mA
GHz S MA R 50
f
S11
S21
S12
GHz
MAG
ANG
MAG
ANG
MAG
ANG
(Deg)
(Deg)
(Deg)
2.00
0.973 -21.2 4.450
154.2
0.022 75.9
2.50
0.951 -27.7 4.453
147.1
0.028 71.2
3.00
0.935 -34.3 4.439
140.3
0.033 66.7
3.50
0.914 -40.6 4.389
133.5
0.038 63.5
4.00
0.893 -46.3 4.314
127.3
0.042 57.7
4.50
0.872 -51.4 4.230
121.1
0.045 54.5
5.00
0.848 -55.9 4.158
115.3
0.048 49.7
5.50
0.829 -60.0 4.118
109.9
0.050 48.2
6.00
0.814 -64.8 4.130
104.3
0.053 46.1
6.50
0.781 -70.1 4.149
98.3
0.058 42.8
7.00
0.745 -76.3 4.180
91.8
0.063 40.4
7.50
0.699 -82.7 4.170
85.3
0.065 36.6
8.00
0.660 -90.3 4.184
78.7
0.070 33.7
8.50
0.635 -99.8 4.197
71.7
0.074 29.4
9.00
0.602 -109.5 4.171
64.7
0.077 25.4
9.50
0.578 -118.3 4.109
57.9
0.081 22.3
10.00 0.554 -127.2 4.063
51.3
0.086 18.9
10.50 0.537 -135.2 4.030
44.6
0.092 15.3
11.00 0.507 -144.1 3.978
37.6
0.095 10.8
11.50 0.477 -154.0 3.950
30.8
0.099 5.9
12.00 0.445 -166.2 3.906
23.5
0.103 2.1
12.50 0.428 -179.6 3.851
16.0
0.108 -2.2
13.00 0.418
165.3 3.762
8.5
0.110 -6.6
13.50 0.430
150.6 3.642
1.1
0.111 -10.3
14.00 0.453
137.9 3.517
-6.1
0.110 -14.8
14.50 0.486
126.7 3.395
-13.0
0.112 -19.6
15.00 0.513
116.7 3.259
-19.9
0.111 -22.0
15.50 0.526
108.4 3.150
-26.4
0.113 -25.6
16.00 0.531
100.4 3.046
-33.3
0.110 -29.3
16.50 0.539
91.1 2.911
-40.7
0.112 -32.1
17.00 0.533
82.1 2.739
-48.0
0.111 -36.1
17.50 0.537
72.2 2.573
-54.3
0.110 -40.1
18.00 0.546
64.7 2.400
-59.4
0.106 -41.6
90
S22
MAG
0.550
0.538
0.523
0.511
0.500
0.495
0.492
0.484
0.482
0.472
0.450
0.423
0.393
0.360
0.327
0.290
0.268
0.251
0.233
0.224
0.211
0.187
0.157
0.123
0.110
0.125
0.161
0.207
0.255
0.299
0.329
0.343
0.347
ANG
(Deg)
-15.2
-19.9
-25.2
-30.3
-34.9
-39.1
-42.9
-45.8
-48.8
-52.6
-56.3
-59.2
-62.6
-67.3
-72.4
-78.8
-86.8
-96.2
-105.3
-114.3
-123.1
-132.5
-146.2
-164.0
169.0
141.4
121.7
113.4
109.0
105.4
101.5
95.9
90.6
f
GHz
2.00
4.00
6.00
8.00
10.00
12.00
14.00
16.00
18.00
Fmin
dB
0.25
0.26
0.28
0.30
0.32
0.34
0.42
0.56
0.72
Gammaopt
MAG
ANG
(Deg)
0.940
12.0
0.800
26.0
0.660
44.0
0.500
68.0
0.380
97.0
0.290
133.0
0.270
177.0
0.330
-129.0
0.390
-82.0
91
Rn/50
0.38
0.33
0.26
0.18
0.11
0.09
0.08
0.11
0.23