International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
1
A New subset I2C protocol for interfacing Camera module with baseband processor
Mamita kushwaha,M-tech 4thsem pursuing, embedded system &VLSI Design from Electronics
&communication,GGITS Jabalpur(M.P)kushwaha.mamita@gmail.com,
Prof.Vinod Kapse, HOD(Electronics & Communication)GGITS Jabalpur (M.P)
Abstract: High speed serial interface between camera sensor and mobile baseband processor it
shall support 3.4 MHZ operation and 7-bit Slave addressing according to a new industry
Standard that support unidirectional transmission of capture image from sensor to memory of
baseband processor for controlling the sensor from baseband processor, we need to have an
interface that exchange control signals between the two sides .We use Camera control
Interface (CCI) protocol for the same .A receiver shall be configured as a CC I master and a CSI-2
transmitter shall be configure as a slave on the CCI bus.CCI is a two-wire ,bi-directional ,half
duplex, serial interface for controlling the transmitter.CCI is compatible with the fast mode
variant of the I2C interface .CCI support400khz operation and 7-bit Slave Addressing. CCI is
capable of handling multiple slaves on the bus. However, multi-master mode is not supported
by CCI. Any I2C commands that are not described in this section shall be ignored and shall not
cause unintended device operation. Typically, there is a dedicated CCI interface between the
transmitter and the receiver. CCI is a subset of the I2C protocol, including the minimum
combination of obligatory features for I2C slave devices specified in the I2C specification.
Therefore, transmitters complying with the CCI specification can also be connected system to
I2C bus.The data protocol is presented in the following section.
Introduction: A new Subset I2C protocol is a sub module of HI2C protocol We are replacing
HI2C by SI2C which will reduce by area upto 50% at existing HI2C based CCI while maintaining
same speed 3.4 MHZ. SI2C is a two-wire, bi-directional, half duplex, serial interface for
controlling the transmitter.SI2C is compatible with the fast mode variant of the I2C interface.
SI2C shall support 3.4MHz operation and 7-bit Slave Addressing is a High Speed Serial Interface
between camera sensor and mobile baseband processor according to a new Industry Standard
that support unidirectional transmission of captured image from sensor to memory of baseband
processor. For controlling the sensor from baseband processor, we need to have an interface that
exchange control signals between the two sides. We use Camera Control Interface (CCI)
protocol for the same.
A receiver shall be configured as a CCI master and a CSI-2 transmitter shall be configured as a
Slave on the CCI bus. Shown in the figure CCI bus.
Copyright © 2012 SciResPub.
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
Device e.g a camera containing the CSI transmitter
& SI2C Slave
CSI Transmitter
U unidirectional high
2
Device e.g an application engine or baseband
containing the CSI receiver & SI2C Master
CSI Receiver
Data N+
Data N+
Data N-
Data NSpeed data link
Data 1+
Data 1+
Data 1-
Data 1-
HI2C Slave
Control link 3.4MHZ
SDA
HI2C Master
SDA
2. Data Transfer Protocol The data transfer protocol is according to I2C standard. The START,
REPEATED START and STOP conditions as well as data transfer protocol are specified in the I2C
specification. 2.1 Message Type A basic CCI message consists of START condition, slave address
with read/write bit, acknowledge from slave, sub address (index) for pointing at a register
inside the slave device, acknowledge signal from slave, in write operation data byte from
master, acknowledge/negative acknowledge from slave and STOP condition. In read operation
Copyright © 2012 SciResPub.
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
3
data byte comes from slave and acknowledge/negative acknowledge from master. The slave
address in the CCI is 7-bit. The CCI supports 8-bit index with 8-bit data
.
From Slave to Master
From Master to slave
Direction dependent on operation
S = START condition P = STOP conditionA = AcknowledgeA = Negative acknowledge
2.2 Read/Write Operations The CCI compatible device shall be able to support four different
read operations and two different write operations; single read from random location, sequential
read from random location, single read from current location, sequential read from current
location, single write to random location and sequential write starting from random location. The
read/write operations are presented in the following sections. The index in the slave device has to
be auto incremented after each read/write operation. This is also explained in the following
sections.
2.2.1 Single Read from Random Location In single read from random location the master does
a dummy write operation to desired index, issues a repeated start condition and then addresses
the slave again with read operation. After acknowledging its slave address, the slave starts to
output data onto SDA line. The master terminates the read operation by setting a negative
Copyright © 2012 SciResPub.
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
4
acknowledge and stop condition
. 2.1.2 Sequential Read Starting from the Current Location
A sequential read starting from the current location is similar to a sequential read from a random
location. The only exception is there is no dummy write operation. The master terminates the
read operation by issuing a negative acknowledge and stop condition.
2.1.3 Single Write to a Random Location The master issues a write operation to the slave then
issues the index and data after the slave has acknowledged the write operation. The write
Copyright © 2012 SciResPub.
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
5
operation is terminated with a stop condition from the master
. 2.1.4 Sequential Write The slave auto-increments the index after each data byte is received.
The sequential write operation is terminated with a stop condition from the master.
Comparison of Occupied Slices:
I2C [1]
Copyright © 2012 SciResPub.
SPI [1]
SI2C(Our proposed)
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
6
Xilinx's
FPGA
Number
of total
slice
Number
of
occupied
slice
Utilization
Number of
occupied
slice
Utilization
Number
of
occupied
slice
Utilization
XC2S506tq144
786
510
66%
363
47%
309
40%
XC3S505tq144
768
503
65%
354
46%
309
40%
XC2V806cs 144
512
504
98%
366
71%
319
62%
XC4v1x1512sf363
6114
512
8%
360
5%
317
5%
Comparison of Delays
I2C[1]
Copyright © 2012 SciResPub.
SPI[1]
SI2C(Our
Purposed)
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
Xilinx's
Clock-to –
setup paths
Clock-tosetup paths
clock-setup
paths
XC2S50-6tq144
12.079ns
12.234ns
11.622ns
XC3S50-5tq144
7.636ns
7.835ns
4.288ns
XC2V80-6cs
144
6.483ns
6.604ns
5.589ns
XC4v1x1512sf363
4.863ns
5.006ns
4.288ns
7
Discussion: In single read from random location the master does a dummy write operation to
desired index, issues a repeated start condition and then addresses the slave again with read
operation. After acknowledging its slave address, the slave starts to output data onto SDA line.
The master terminates the read operation by setting a negative acknowledge and stop condition.
Test Procedure for Master: Configure the Master to transmit a write operation to an index
using either a 8, issue a repeated start condition, and then send a read operation to the Testing
Station acting as a CCI slave. The Testing Station should output data onto the SDA line. The
master should then terminate the read by transmitting a negative acknowledge and stop
condition.
Test Procedure for Slave: Configure the Testing Station acting as a Master to transmit a write
operation to an index using either a 8, issue a repeated start condition, and then send a read
operation to the CCI slave. The Slave should output data onto the SDA line. The Testing Station
acting as Master should then terminate the read by transmitting a negative acknowledges and
stop condition.
Observed Results:
1. Verify that the Master or Slave properly completed the Single Read from Random Location
operation.
6. Conclusion For cameras the command set is dependent on the architecture, and still there is
no any standard for the same. For flexibility CSI-2 does not specify a command set. Proposed
architecture of Camera Control Interface (CCI) is suitable as per the observed results for writing
generalized commands in Camera modules.
Reference:
Copyright © 2012 SciResPub.
International Journal of Advancements in Research & Technology, Volume 1, Issue7, December-2012
ISSN 2278-7763
8
[1]FPGA Implementation of I2C & SPI Protocols,A.K. Oudjida, M.L. Berrandjia, R. Tiar, A. Liacha,
K. Tahraoui,Microelectronics and Nanotechnology DivisionCentre de Développement des
Technologies Avancées, CDTAAlgiers, Algeria(2009)IEEE
[2] A New standard protocol for Camera Control Interface Andy Baidman David Woolf
djwoolf@iol.unh.edu. Inter Operability Laboratory, University of New Hampshire Jim Rippie
IEEE-ISTO in 2009
[3] MIPI Alliance Standard for Camera Serial Interface 2 Version 1.00 29 November 2005 (CSI-2
Standard) .
[4]THE I2C BUS SPECIFICATION VERSION 2.1 January, 2000, Philips Semiconductors.
[5] Design and Interfacing of High speed model of FPGA using I2C protocol ISSN 2229-6093.
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