Intellectual Property
Selector Guide
IP Functions for System-on-a-Programmable-Chip Solutions
March 2003
Contents
• Introduction to Altera IP
Megafunctions
Page 3
• DSP Solutions
Page 5
• Communications Solutions
Page 11
• Microsystems Solutions
Page 16
• Development Kits
Page 20
• AMPP Partners Directory
Page 22
I
Introduction to Altera IP
Megafunctions
With the advent of multi-million-gate FPGAs, designers
are developing more flexible systems with increased integration, complexity, and functionality by implementing
entire digital sub-systems into a single FPGA, a systemon-a-programmable-chip (SOPC). System-level intellectual
property (IP) blocks, or megafunctions, play a key role in
this SOPC development process. Combining Altera® IP with
Altera FPGAs and development software can significantly
lower your production costs and reduce your time-to-market.
AMPP Partners
Leading third-party IP vendors partner
with Altera to bring their design expertise to Altera FPGA users. These vendors, called AMPP
partners, develop IP that is optimized for Altera devices
and license them directly to Altera customers.
Premier AMPP Partners
Premier AMPP partners focus on the
FPGA market and work closely with
Altera to provide integrated SOPC solutions to our mutual
customers. Current Premier AMPP partners are listed in
Table 6 on page 22 and on the Altera web site
(www.altera.com).
Dramatically Reduce Time-to-Market
Experienced designers have found that using ready-made,
pre-tested IP to augment existing hardware description
language (HDL) design methodology significantly shortens
time-to-market for current as well as future systems.
Reusable and optimized for reprogrammable FPGA architectures, Altera IP facilitates system development by
providing large, standard functional blocks for specific
applications. Using Altera IP frees you to focus more time
and energy on improving and differentiating your product,
instead of on redesigning commonly used functions.
FPGA IP vs. ASIC IP
Using IP in FPGAs offers many advantages over ASIC
implementations. FPGA IP often offers the same performance as ASIC IP, but FPGA IP is pre-tested and ready to
use in hardware, providing optimal performance with
minimal development time. Off-the-shelf FPGAs also offer
reduced time-to-market due to the elimination of manufacturing lead times. In addition, FPGAs may be reprogrammed
in-house, eliminating costly and time-consuming re-spins
for bug fixes or specification changes. Finally, with programmable logic, systems can be upgraded in the field,
eliminating costly recalls and lost sales.
Extensive IP Portfolio
Altera’s IP megafunction portfolio includes Altera-designed
MegaCore® functions and megafunctions offered through
Altera Megafunction Partners Program (AMPPSM) partners.
MegaCore Functions
MegaCore functions are developed, verified,
documented, and licensed directly by Altera.
These functions are highly parameterizable
and are optimized for specific Altera device
architectures, allowing user-specific performance goals to
be met.
Altera Corporation
AMPP Software Program
The AMPP Software Program is a partnership between Altera and software IP
providers for processor-based SOPC solutions. AMPP software partners develop software IP optimized for use with
Altera’s Nios® embedded processor and Excalibur™ devices.
Altera IP Features
Altera is committed to delivering quality, easy-to-use
MegaCore and AMPP IP. Altera pioneered plug-and-play IP
methodology with MegaWizard® Plug-In parameterization
tools, OpenCore® evaluation, and the AMPP Approved certification. With the introduction of the new OpenCore Plus
evaluation feature and the I-Tested and SOPC Builder
Ready certifications, Altera offers new levels of freedom in
IP evaluation and system integration.
Products listed on the Altera IP MegaStore™ web site
(www.altera.com/IPmegastore) may support one or more
of the following features:
MegaWizard Plug-Ins
Altera MegaWizard Plug-Ins allow you to customize IP via intuitive graphical user interfaces
and integrate it into standard HDL design flows.
Using IP powered by MegaWizard Plug-Ins
saves considerable time and money while
hiding the complexities of implementation.
OpenCore IP Evaluation
The OpenCore feature lets you test-drive
functions for free when using the Quartus® II
OpenCore design software. You can download IP from
the web and then evaluate the functionality, size, and speed
of the function in your system before making a purchase
decision. You may not, however, generate
3
device programming files. The OpenCore feature is supported
by all MegaCore functions and most AMPP functions.
OpenCore Plus IP Evaluation
The OpenCore Plus feature complements the
evaluation flow by adding free register transfer
level (RTL) simulation and hardware evaluation. OpenCore Plus RTL simulation allows
you to simulate an RTL model of a MegaCore function in
your design. You can perform simulation using either the
Visual IP simulator-independent models or compiled simulator-specific models that are shipped with the function.
The OpenCore Plus hardware evaluation feature allows you
to generate time-limited programming files for a design
that includes MegaCore or AMPP functions. You can use
the OpenCore Plus hardware evaluation to perform boardlevel design verification before deciding to purchase a
license. With this feature, you only need to purchase a
license when you are completely satisfied with a core’s
functionality and performance, and would like to take your
design to production. Selected MegaCore and AMPP functions support the OpenCore Plus feature.
IP Certifications
Altera is committed to providing IP cores that work seamlessly with Altera tools or interface specifications. To help
you identify appropriate IP cores, some megafunctions may
carry these Altera-defined certifications:
AMPP Approved
The AMPP Approved certification
confirms that third-party IP
has undergone Altera’s thorough internal review process
and has been fully optimized for Altera devices. All
third-party IP in the AMPP program have the AMPP
Approved certification.
DSP Builder Ready
The DSP Builder Ready certification is given to IP that has plugand-play integration with the DSP Builder software. These
cores can be instantiated and parameterized within the DSP
Builder design flow, making it easier for users to design
complex DSP systems.
SOPC Builder Ready
The SOPC Builder Ready certification is given to IP that has
plug-and-play integration with Excalibur devices or Nios
embedded processors via the SOPC Builder software. These
cores support interfaces for the Avalon™ bus for the Nios
processor or advanced high-performance bus (AHB) and
include software drivers, low-level routines, or other software design files.
Atlantic Compliant
The Atlantic™ Compliant certification is given to IP cores that
are compliant with the Atlantic interface specification, a
high-performance point-to-point interface for asynchronous
cell- or packet-based transfers. The standard Atlantic
interface makes it easy to integrate multiple IP cores and
user-designed logic, potentially saving weeks of design time.
Licensing Megafunctions
Altera offers flexible licensing options for MegaCore
functions. All MegaCore licenses are for perpetual use,
are node-locked (licensed for a single computer), include
upgrades and support for one year, and may be used in
multiple projects.
In addition to single licenses, you can purchase additional
licenses for a significant discount. Suites of MegaCore
functions are also offered at a discount. Contact your Altera
sales representative or distributor for pricing options.
I-Tested
IP that has been tested in an
Altera device on a board for
interoperability with ASSPs is awarded the I-Tested, or
“interoperability-tested," certification. Altera or an Altera
partner performs interoperability testing on functions
whose correct operation can only be guaranteed through
physical testing in hardware. This testing is carried out in
addition to rigorous software simulation using testbenches
and bus functional models that are performed for all IP.
4
AMPP functions are offered under different licensing terms,
conditions, and pricing models. Contact the AMPP partners
directly for detailed information.
IP Design Flow
Figure 1 shows the recommended design flow for obtaining, evaluating, and purchasing Altera IP. Visit the Altera
IP MegaStore web site for a more detailed description of
this flow.
Altera Corporation
Figure 1. Altera IP Design Flow
Download
Customize
Evaluate in
Quartus II Software
Simulate RTL &
Evaluate Hardware
Purchase
BUY
IP Support
Additional Documentation
All IP support or information requests may be directed to
Altera’s on-line issue entry and tracking system, mySupport
(www.altera.com/mysupport). You may also contact AMPP
partners directly for AMPP IP support.
Altera provides IP reference documentation such as data
sheets, user guides, application notes, and solution briefs.
For the latest Altera literature, information, and IP updates,
go to the Altera web site.
D
DSP Solutions
Performance Advantages
Code:DSP is a major Altera
initiative to extend the reach
of FPGAs from multi-channel, high-performance signal
processing functions to a wide range of mainstream digital
signal processing (DSP)-based applications. Highlighted by
the industry's first C-code-based design flow for programmable logic, the Code:DSP project sharpens Altera's focus
on the DSP market by offering designers a broad range
of support services, tools, and development platforms for
implementing reconfigurable DSP designs in Altera’s
leading-edge FPGAs.
Offering compelling performance advantages over dedicated digital signal processors, FPGAs can be thought of
as an array of elements, each of which can be configured
as a complex processor routine. These processor routines
can then be linked together serially (the same way digital
signal processors would execute them) or they can be
connected in parallel. In parallel, they offer many times
the performance of standard digital signal processors by
executing hundreds of instructions simultaneously.
Algorithms that benefit from this improved performance
include forward error correction (FEC), image processing,
modulation/demodulation, and encryption (see Figure 2
on page 6).
In addition to the new design flow, Altera's Code:DSP
initiative includes a development platform based on the
industry-leading Stratix™ FPGA family and comprehensive
support programs. By delivering a complete DSP solution,
Altera can take advantage of opportunities in the DSP
market that reach beyond the wireless infrastructure
applications. Table 1 on page 9 lists the DSP IP.
Hardware Acceleration for Existing Designs
DSP algorithms can be easily integrated as hardware
accelerators for a Nios processor or into the data path as
a pre- or post-processor to implement computationally
rigorous routines, leaving the digital signal processor at the
center of the original design. Adding a high-performance
FPGA to address bottlenecks at both ends of a process
allows DSP software engineers to leverage existing software
code while reaping the benefits of hardware acceleration.
Altera Corporation
DSP Design Flow
Altera offers an innovative design flow that extends the
benefits of programmable logic to DSP designers without
the need for them to learn new design flows or programming languages.
Altera DSP Design Flow
The Altera DSP design flow provides system-level integration and flexibility for hardware and software partitioning
of the DSP system. In addition, Altera supports hardware
description language (HDL)-based and C/C++-based
design flows. Altera's suite of development tools—including
DSP Builder, SOPC Builder, and the Quartus II software—
provide a complete design platform with the performance
and flexibility of a combined hardware and software
implementation in a single system (see Figure 3 on page 6).
5
ment, simulation, and verification capabilities of The MathWorks MATLAB and
Simulink system-level design tools with
HDL synthesis, simulation, and Altera
development tools.
Figure 2. DSP IP Advantage
Traditional DSP Serial
Operation
FPGA Parallel Operation
fx
DSP Engine
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
fx
Memory
fx
Sequential (Serial) Operation
Parallel Operation
n Clocks
1 Clock
DSP Builder: DSP System Design Tool
DSP system design in Altera FPGAs requires both highlevel algorithm and HDL development tools. DSP Builder
integrates these tools by combining the algorithm develop-
fx
DSP Builder shortens DSP design cycles
by helping you create the hardware
representation of a DSP design in an
fx
algorithm-friendly development
fx
environment. You can combine existing
MATLAB functions and Simulink blocks
with Altera DSP Builder blocks and
fx
Altera IP MegaCore functions to link
system-level design and implementation
with DSP algorithm development. DSP
Builder allows system, algorithm, and
hardware designers to share a common
development platform. You can use DSP
Builder blocks to create a hardware
implementation of a system modeled in Simulink in sampled time. DSP Builder contains bit- and cycle-accurate
Simulink blocks, which cover basic operations such as
fx
Figure 3. DSP Design Flow Overview
DSP Builder
Altera Blockset
MATLAB/
Simulink
IP
Signal Compiler
Custom
HDL IP
Simulation
• Testbench
• TCL Script
Synthesis &
Place-and-Route
• VHDL/Verilog
• TCL Script
Custom
Testbench
System Integration
• class.ptf
• Wrapper files for
Custom Instruction
Embedded Software
• C Header Files
• Custom Library
• Peripheral Drivers
• OS/RTOS Kernals
SOPC Builder
Hardware
C/C++ Compiler/Linker
• GNUPro Tools
Download
Software Code
Optional
System Level
SignalTap® II
Analyzer
6
®
®
Third-Party Tools
• Operating Systems
• Debuggers
Software with
Hardware
Acceleration
Altera Corporation
arithmetic or storage functions. You can integrate complex
functions by using MegaCore functions in your DSP Builder
model. See Figure 4.
Figure 4. DSP Builder
easy when using Altera’s FIR Compiler, Constellation
Mapper/Demapper, and Numerically Controlled Oscillator
(NCO) functions. Using programmable logic to implement
your modulation scheme lets you test your design in hardware the day you build the design.
Transforms
Fast Fourier transform (FFT) functions implemented in
programmable logic offer a considerable increase in performance compared to DSP processors. Altera's FFT functions
are parameterizable for high-performance applications and
implements complex input and output transforms for FFT
and inverse FFT (IFFT).
Encryption/Decryption
Altera’s data encryption standard (DES) IP is certified by
the National Institute of Standards and Technology (NIST)
and can be used in applications requiring electronic code
book (ECB) or triple-DES encryption. Using an FPGA for
encryption makes it easy to implement DES in any operating mode or to add proprietary pre-processing to the
encryption stream. In addition to the DES core, Altera
offers Rijndael (AES), SHA-1, and MD5 cores.
DSP IP
Altera’s large portfolio of DSP functions greatly simplifies
the design of complex wireless transmission systems such
as the one shown in Figure 5.
Filtering
Digital filters such as finite impulse response (FIR) and
infinite impulse response (IIR) filters offer more than 10
times the performance of digital signal processors when
implemented in FPGAs. Altera’s FIR Compiler and IIR
Compiler signal processing functions reduce design time
from weeks to hours. Altera’s Stratix FPGA family has several DSP-specific features such as embedded multipliers and
DSP blocks, which are optimized for filtering functions.
Modulation/Demodulation
Designing modulators and demodulators, such as quadrature
amplitude modulation (QAM), m-ary phase shift keying
(MPSK), and differential phase shift keying (DPSK) becomes
Correlation
When implemented in programmable logic, correlation
functions (such as a correlator) provide significant
performance and ease-of-use advantages over competing
solutions. Maximum flexibility can be attained by using
parameterizable features of these functions on various
Altera FPGAs.
Signal Generation
When implemented in programmable logic, signal generation
functions, such as NCOs or linear feedback shift registers
(LFSRs), provide significant performance and ease-of-use
advantages over competing solutions. You can attain maximum flexibility by using parameterizable features of these
functions on Altera FPGAs.
Figure 5. Typical Transmitter Using DSP IP
Encryption
Basic Math
Functions
Filters
FEC
CRC1
Transforms
Comparators
& Shift
Registers
NCO
Mapper
QAM
Antenna
Note: CRC: Cyclic Redundancy Code
1
Altera Corporation
7
Figure 6. Error Detection & Correction Block Diagram
Data
In
Outer
Encoding
Encryption/
CRC/FEC
Inner
Encoding
FEC
Noisy
Channel
Inner
Decoding
FEC
Outer
Decoding
Decryption/
CRC/FEC
Image & Video Processing
Image and video processing functions such as JPEG and
MPEG encoders and decoders are ideal for programmable
logic implementations. Altera’s AMPP partners offer an
extensive selection of image and video processing IP cores.
Error Detection/Correction
When starting a new design, communications systems engineers must weigh the trade-off between data reliability and
throughput. Using modern FEC techniques, receivers can
correct data that was corrupted during signal transmission,
thereby increasing the effective data bandwidth, as shown
in Figure 6.
• Reed-Solomon: Reed-Solomon is an advanced FEC
technique that is widely used in data communication,
storage, and mobile computing. The efficient ReedSolomon algorithm uses polynomials to add redundancy
to the transmitted data. Implementing Reed-Solomon
functionality using a DSP processor is expensive and
unsuitable for high-performance applications. Altera’s
DSP IP solutions provide a wide range of Reed-Solomon
encoders and decoders, including discrete, streaming,
continuous, and erasures-support.
• Viterbi: High-performance, area-optimized Viterbi
decoding (or convolutional decoding) with flexible
constraint lengths, soft bits, and traceback length can be
implemented in an Altera FPGA. As with all signal
processing functions, performance is not compromised;
the maximum data throughput is increased from a typical DSP processor rate of 1 Mbps to over 150 Mbps.
• Turbo: As specified by the third-generation partnership
project (3GPP) for third-generation (3G) wireless infrastructure, turbo convolutional codes are complex and
difficult to implement in digital signal processors.
However, Altera’s DSP solution allows designers to
easily implement turbo convolutional codes.
DSP IP Applications
DSP IP functions are ideal for high-performance, highthroughput applications. These applications, which would
normally require several digital signal processors, can be
placed into a single, highly flexible, high-performance FPGA.
8
Data
Out
Wired
DSP IP is ideal for communications applications
requiring high throughput such as DSL access
multiplexers (DSLAMs), or for flexible modulation
schemes such as cable broadcasting. Media storage applications, such as mass storage (magnetic
or optical), digital video disc, and digital tape
applications require robust FEC algorithms.
Wireless & Broadband
The Altera DSP communications solution is ideal for the
rigorous high-throughput requirements of wireless and
broadband applications. The performance advantages of
parallel processing coupled with the traditional flexibility
of programmable logic make DSP IP ideal for emerging
areas such as 3G wireless, digital audio and video broadcasting, multi-channel multipoint distribution services
(MMDS), and orthogonal frequency division multiplexing
(OFDM) systems. Using IP, designers can quickly adapt to
changing standards such as the wireless 802.11 standard,
Air Interface for Fixed Broadband Wireless Access Systems
(802.16), and HiperLAN2. The building blocks for these
applications require FEC, modulation, filtering, and encryption—all areas addressed by Altera’s DSP portfolio.
OFDM
OFDM has recently surged in popularity for wireless systems. Broadcast applications, such as terrestrial digital
video broadcast and digital audio broadcast (DAB), and
“last-mile" connectivity applications, such as MMDS and
wireless local area networks (LANs), have all adopted
OFDM as the modulation method of choice. With highperformance, parameterizable FFT, Reed-Solomon, and
Viterbi functions, Altera’s DSP IP portfolio contains all the
major blocks required to implement an OFDM system, as
shown in Figure 7.
Proven Solutions
Examples of complete systems using IP from the DSP
portfolio include:
• 3G wireless code-division multiple access (CDMA)
basestations
• Digital video basestations
• Wireless broadband modems
• Global system for mobile communication (GSM) edge
basestations
• MMDS basestations
• Professional DVD recorders
• Multimedia satellite ground stations
Altera Corporation
Figure 7. Complete System Solution for a Typical OFDM Transmitter
Data
In
FEC
Coder
Interleaver
Constellation
Mapper
Buffer
Inverse
Fast
Fourier
Transform
Parallel
to
Serial
Shaper
FIR
Filter
Cyclic
Prefix
Insertion
DAC
OFDM Modulator
Altera IP Solution
Altera FPGA Solution
Non-FPGA Solution
• VDSL modems
Altera currently offers these reference designs and more on
the Altera web site:
• Video processing systems
• Local multipoint distribution service (LMDS) basestations
• Digital Down Converter (DDC)
• QPSK Modem
Reference Designs
Altera provides many reference designs that are useful to
designers of FPGA-based DSP solutions. The no-cost reference
designs, which are provided in clear text VHDL or Verilog,
can be used as an experiment platform, a design starting
point, or as a reference. Designers can use Altera reference
designs to focus on innovative new solutions, differentiate
their products from competitors, and reduce time-to-market.
• Direct Sequence Spread Spectrum (DSSS)
• Filtering
DSP Development Kits
Altera DSP development kits are effective platforms for
prototyping and debugging DSP designs for programmable
logic. For more information on Altera’s DSP development
kits, refer to “Altera DSP Development Kits” on page 20.
Table 1. DSP IP (Part 1 of 2)
CATEGORY
Arithmetic
Correlation
Encryption/Decryption
Filtering
Error Detection/Correction
Altera Corporation
FUNCTION DESCRIPTION
VENDOR
Logarithm Function
Altera Corporation
Square Root Function
Altera Corporation
Floating-Point Operator Library
Amphion Semiconductor, Ltd.
Floating-Point-to-Integer Pipelined Converter
Digital Core Design
Floating-Point Pipelined Divider Unit
Digital Core Design
Floating-Point Pipelined Multiplier Unit
Digital Core Design
Integer-to-Floating-Point Pipelined Converter
Digital Core Design
Floating-Point Mathematics Unit
Digital Core Design
Correlator
Altera Corporation
Binary Pattern Correlator
Nova Engineering, Inc.
DES Encryption Processor
Altera Corporation
High-Speed Rijndael/Advanced Encryption Standard (AES) Encryption &
Decryption
Altera Corporation
Low-Speed Rijndael/AES Encryption & Decryption
Altera Corporation
MD5A Hash Function
Altera Corporation
SHA-1 Hash Function
Altera Corporation
DES Cryptoprocessor
CAST, Inc.
AES Cryptoprocessor
CAST, Inc.
Secure Hash Algorithm (SHA)
CAST, Inc.
High-Speed AES Rijndael Encryption
D’crypt Pte. Ltd.
High-Speed AES Rijndael Decryption
D’crypt Pte. Ltd.
FIR Compiler
Altera Corporation
IIR Compiler
Altera Corporation
CRC Generator/Checker
Altera Corporation
Reed-Solomon Compiler, Decoder
Altera Corporation
Reed-Solomon Compiler, Encoder
Altera Corporation
9
M
Table 1. DSP IP (Part 2 of 2)
CATEGORY
FUNCTION DESCRIPTION
VENDOR
Error Detection/Correction
Symbol Interleaver/Deinterleaver
Altera Corporation
(cont.)
Turbo Decoder Function
Altera Corporation
Turbo Encoder Function
Altera Corporation
Viterbi Compiler, High-Speed Parallel Decoder
Altera Corporation
Viterbi Compiler, Low-Speed/Hybrid Serial Decoder
Altera Corporation
Reed-Solomon Decoder Minicore
Altera Corporation
DVB FEC Codec
Amphion Semiconductor, Ltd.
Reed-Solomon Decoder
Amphion Semiconductor, Ltd.
Reed-Solomon Encoder
Amphion Semiconductor, Ltd.
Viterbi Decoder
Amphion Semiconductor, Ltd.
Reed-Solomon Decoder
Mentor Graphics – Inventra
Reed-Solomon Encoder
Mentor Graphics – Inventra
DVB-RCS Turbo Decoder TC1000
TurboConcept
Turbo Product Code Decoder TC3000
TurboConcept
Color Space Converter
Altera Corporation
CCIR-656 Encoder
Adaptive Micro-Ware
CCIR-656 Decoder
Adaptive Micro-Ware
JPEG Encoder & Decoder Functions
Amphion Semiconductor, Ltd.
JPEG 2000 Encoder
Amphion Semiconductor, Ltd.
JPEG 2000 Decoder
Amphion Semiconductor, Ltd.
JPEG CODEC
Amphion Semiconductor, Ltd.
MPEG2 Video Decoder
Amphion Semiconductor, Ltd.
MPEG2 Audio Decoder
Amphion Semiconductor, Ltd.
MPEG4 Decoder
Amphion Semiconductor, Ltd.
2D DCT IDCT
Barco Silex
Fast Black & White JPEG Decoder
Barco Silex
Fast Color JPEG Decoder
Barco Silex
Color Space Converter
CAST, Inc.
Forward Discrete Cosine Transfer (DCT)
CAST, Inc.
2D Discrete Wavelet Transform (RC_2DDWT)
CAST, Inc.
Fast JPEG Encoder
CAST, Inc.
Fast JPEG Decoder
CAST, Inc.
Constellation Mapper/Demapper
Altera Corporation
Complex Tuner
CommStack, Inc
Dual Resampler 1Y
CommStack, Inc
Dual Resampler 4Y
CommStack, Inc
Up Converter
CommStack, Inc.
Complex Multiplier/Mixer
Nova Engineering, Inc.
Digital IF Receiver
Nova Engineering, Inc.
Digital Modulator
Nova Engineering, Inc.
Numerically Controlled Oscillator Compiler
Altera Corporation
Telephony Tone Generation
Ncomm, Inc.
Telephony Gain Generation
Ncomm, Inc.
Numerically Controlled Oscillator
Nova Engineering, Inc.
u-Law and A-Law Companders
Altera Corporation
Multi-Standard ADPCM Encoder/Decoder
Amphion Semiconductor, Ltd.
Early/Late-Gate Symbol Synchronizer
Nova Engineering, Inc.
Cordinate Rotation Digital Computer (CORDIC)
Altera Corporation
FFT/IFFT
Altera Corporation
Hadamard Transform Processor
Altera Corporation
FFT/IFFT High-Performance 64-Point
Amphion Semiconductor, Ltd.
FFT/IFFT Low-Latency 64-Point
Amphion Semiconductor, Ltd.
Image & Video Processing
Modulation/Demodulation
Signal Generation
Speech & Audio Processing
Transforms
10
Altera Corporation
C
Communications Solutions
SONET/SDH Functions
SONET/SDH remains the primary transport technology used
in public infrastructure due to its high-reliability and
familiarity. As fundamental building blocks, SONET/SDH
framing and overhead processing functions are found on
line-cards throughout the network. Altera’s SONET/SDH
Compiler can be used to configure framing and overhead
processing functions for line-rates ranging from OC-1 to
OC-192. Complimentary functions providing ATM cell
delineation, point-to-point protocol (PPP) packet delineation,
T3 framing and mapping, and E3 mapping are also available,
as well as Reed-Solomon encoder/decoders used in G.709
FEC. These functions can be integrated with proprietary
functions for a unique, single-chip solution.
Today, telecom and datacom equipment manufacturers face
the challenge of developing systems that will expand voice
and data networking services over existing fiber. To address
these requirements, a variety of new standards have emerged,
such as 10 Gigabit Ethernet (GbE), GbE over SONET/SDH,
virtual concatenation (VC) and the link capacity adjustment
scheme (LCAS), and generic framing procedure (GFP),
which are used to interconnect LANs into a wide-area network (WAN) over existing SONET/SDH backbones. To
deploy services based on these new protocols, carriers are
faced with the additional challenge of continuing to support
existing services based on the plesiochronous digital hierarchy (PDH) that use T1/E1 and T3/E3 lines for network
access. With the Stratix, Stratix GX, and Cyclone™ device
families, Altera provides the FPGAs required for all of
these applications.
10 Gigabit Ethernet Functions
With the low-cost 10/100 Ethernet standard used ubiquitously to interconnect computers, servers, and peripheral
devices in LANs, and Ethernet switching rates increasing to
1 Gbps, higher-performance interconnects between multiple
LANs for campus networking and WAN applications are
necessary. The 10 GbE standard uses the same frame format
as 10/100 Ethernet and GbE, yet it eliminates bottlenecks
with 10-Gbps fiber connections.
Altera and its partners have developed a broad portfolio
of communication IP that can be used to accelerate FPGA
design cycles (see Table 2 on page 14). These standardsbased functions can be configured to system requirements
and use well-defined on-chip interfaces for the simple
connection of complimentary functions. Altera’s Atlantic
interface is a synchronous interface used for packet- or
cell-based transfers of asynchronous traffic between blocks
of IP. The midbus interface is a time division multiplexer
(TDM) bus for synchronous data, such as SONET/SDH
streams. Detailed technical specifications for these and the
Access to Internal Registers (AIRbus) interfaces are available
on the Altera web site.
AMPP partner MorethanIP provides 10 GbE MAC and
64B/66B physical coding sub-layer (PCS) functions.
Additionally, Altera provides the 10 GbE WIS with its OC-192
SONET/SDH framer and overhead processor configuration,
available through the SONET/SDH Compiler. Figure 8 illustrates a 10 GbE LAN-PHY implementation with the addition
of the WIS layer for 10 GbE WAN-PHY applications.
Figure 8. 10 GbE LAN-PHY & WAN-PHY Implementations
10 GbE LAN-PHY
FPGA Boundary
XSBI
Interface
Integrated
Fiber-Optic
Transponder
XGMII
Interface
10 GbE
PCS
(64B66B)
Atlantic
Interface
10 GbE
MAC
Atlantic
Interface
User
Logic
SPI-4.2
Interface
PL4
10 GbE WAN-PHY
FPGA Boundary
SFI-4
Interface
Integrated
Fiber-Optic
Transponder
Altera Corporation
Midbus
Interface
OC-192c
SONET
Framer
XGMII
Interface
10 GbE
PCS
(64B66B)
Atlantic
Interface
10 GbE
MAC
Atlantic
Interface
User
Logic
SPI-4.2
Interface
PL4
11
The 10 GbE attachment unit interface (XAUI) uses four
lanes (or channels) of 8B/10B-encoded data for CDR at
4 ✕ 3.125 Gbps, significantly extending the reach of the
signal. The Altera Stratix GX device family provides the
dedicated hardware circuitry required to implement a XAUI
transceiver, including clock-data recovery (CDR), serializer/deserializer (SERDES), 8B/10B encoder/decoder, word
aligner, and channel aligner.
To address the issue of system interoperability, many
manufacturers have used a frame-mapped generic framing
procedure (GFP) to encapsulate the GbE frames with the
port address information. AMPP partner Nuvation has
developed the 10:1 GbE to SONET Multiplexer megafunction, which includes frame-mapped GFP encapsulation
and Atlantic interfaces on both sides of the core for direct
connection to Altera’s POS-PHY Level 4 function.
Figure 9 illustrates a 10 GbE backplane implementation in
a Stratix GX device using MorethanIP’s 10 GbE MAC function and Altera’s POS-PHY Level 4 MegaCore function.
For cost-efficiency, a Stratix GX device can be implemented
as the multi-channel GbE PCS and MAC layers with multiple instances of MorethanIP’s 10/100/1000 Ethernet MAC
function directly connected to Nuvation’s 10:1 GbE to
SONET Multiplexer over their Atlantic-compliant interfaces.
Because the ten MAC cores consume roughly the same
amount of logic as the 10-port POS-PHY Level 4 function
in the three-chip solution, this integrated two-chip design
saves the cost of one device, as illustrated in Figure 10.
Gigabit Ethernet over SONET/SDH Functions
Recognizing that only a small number of enterprises have
the bandwidth to utilize 10 GbE WAN connections, a number
of standards have evolved to interconnect LANs using GbE
as the WAN access technology. The simplest approach takes
the Ethernet frames from multiple GbE channels, applies a
routing tag (port address) to the packet, and then multiplexes
the packets into a single OC-192c packet over SONET/SDH
(POS) stream for transport through the carrier networks.
Multi-channel GbE MAC devices are available from a
number of ASSP vendors, as well as OC-192c POS devices.
To implement the GbE port addressing and multiplexing
functions, proprietary protocols are implemented in a
third device, typically an FPGA with SPI-4.2 interfaces on
both sides of the device (single-PHY on the OC-192c POS
side and multi-PHY on the multi-channel GbE side). The
most significant limitation of this approach is the use of
the proprietary GbE port addressing protocol, which forces
carriers to use equipment from a single vendor to ensure
system interoperability.
For more information on SONET/SDH functions, visit the
Altera web site.
ATM Functions
The inherent advantages of switching fixed-length cells, as
opposed to variable-length packets, continue to be important
in latency-sensitive applications, such as voice communications. In addition to ATM cell delineation functions (up to
2.5 Gbps), Altera and its partners offer inverse multiplexing
for ATM (IMA) and ATM adaptation layer 5 segmentation
and reassembly (AAL5 SAR).
Altera and its partners also provide an array of UTOPIA
interface functions, which are typically employed to interconnect ATM devices, including UTOPIA Level 2 and 3
Master and Slave interfaces.
Figure 9. XAUI Backplane Transceiver
Stratix GX Boundary
Atlantic
Interface
SPI-4.2
Interface
10-Gbps
Network
Processor
12
Dynamic Phase
Alignment (DPA)
PL4
Atlantic
Interface
User
Logic
XAUI
Interface
8B10B
10-Gbps
Encoder/ Decoder
MAC
& CDR/SERDES
Backplane
Connector
Altera Corporation
Figure 10. GbE over SONET/SDH
ASSP
Altera’s communication IP portfolio would not be complete
without broad support for the variety of external device
interface protocols found in legacy ASICs and ASSPs. Chipto-chip interfaces are a central part of the system glue, and
Altera and its partners provide a range of interface functions
for the data path and control plane of communication
systems. Control plane interfaces are discussed in
“Microsystems Solutions" on page 16.
POS-PHY Interfaces
Initially defined by the Saturn Development Group as the
interface between the physical (PHY) and link layers for
POS applications, POS-PHY interfaces have become common
in a variety of other applications, including GbE, multiGbE, 10 GbE, and ATM over SONET/SDH. POS-PHY Level 3
and POS-PHY Level 4 have been adopted by the Optical
Interconnect Forum (OIF) as SPI-3 and SPI-4.2, respectively.
Altera’s POS-PHY Level 4 MegaCore function leverages
Stratix and Stratix GX device features—such as advanced
I/O capabilities, 3.125-Gbps transceivers, 1-Gbps LVDS
channels, and dynamic phase alignment (DPA) circuitry—
with SPI-4.2-compliant processing logic. This highly configurable function can be used in a variety of applications
with support for single-PHY and multi-PHY configurations
up to 256 ports with embedded addressing in a single FIFO
Altera Corporation
8B10B Encoder/ Decoder
& CDR/SERDES
GbE MAC
GbE MAC
Ethernet over SONET
Multiplexer (EOSMUX)
POS-PHY LEVEL 4
POS-PHY Level 4
Chip-to-Chip Interface Functions
Dynamic Phase Alignment (DPA)
SPI-4.2
Interface
OC-192c
Packet over SONET/SDH Framer
buffer or multiple independent memory elements with
buffer management. The internal data path width may be
configured for either 64- or 128-bit, allowing designers to
trade off logic consumption for performance and tailor
the solution to their system’s specific requirements. The
MegaCore function also provides a configurable Atlantic
interface along with fixed start-of-packet (SOP) alignment
to the most significant byte lanes, significantly reducing
the complexity of neighboring logic design.
Altera’s POS-PHY Level 2 and 3 Compiler delivers configurations for POS-PHY Level 2 and POS-PHY Level 3, link-layer
and PHY-layer interfaces, and turnkey bridges between these
interfaces. The Cyclone device family provides the industry’s
lowest-cost FPGA for POS-PHY Level 2 and Level 3 applications, while the Stratix device family provides the density for
the highest level of integration in your SOPC design.
Flexbus Interfaces
Flexbus interfaces were developed by AMCC in conjunction
with their initial OC-48 and OC-192 POS framer devices as
the interface between the PHY and link layers. Because the
initial developments preceded the advent of high-speed
LVDS technologies, a wide 64-bit interface using high-speed
transceiver logic (HSTL) signaling was specified for OC-192
applications, known as Flexbus 4, and later adopted by the
OIF as SPI-4.1. Use of SPI-4.1 interfaces is in decline, with
13
AMCC adopting the narrower SPI-4.2 interface for its family
of OC-192 POS framers, 10 GbE MAC, and 10 Gbps network
processing and traffic management devices. During the
migration period, some of the legacy devices can be used
with Flexbus 3 and Flexbus 4 megafunctions from Altera
AMPP partner Modelware.
UTOPIA Interfaces
Defined by the ATM Forum, UTOPIA interfaces continue to
be widely used to interconnect PHY-layer and ATM layer
devices. Altera and a number of AMPP partners offer
UTOPIA interface solutions, including support for UTOPIA
Level 2 and Level 3 Master and Slave functions.
CSIX-L1 Interfaces
Defined by the Network Processing Forum, Common Switch
Interface Layer 1 (CSIX-L1) is an industry-standard datapath interface between traffic management (or network
processing) devices and switch fabrics (or their queuing
engine transceivers). The CSIX-L1 protocol defines fixed-
size frames (CFrames) as the fundamental element to be
switched. CSIX-L1 utilizes a 32-bit interface for OC-48
applications, and 64- or 128-bit interface for OC-192 and
10 GbE applications, with HSTL Class I or II signaling. With
wide acceptance of the narrower SPI-4.2 interface, some
vendors have implemented the CSIX-L1 protocol over 16-bit
LVDS signaling.
Altera’s CSIX-L1 megafunction is a configurable IP core,
supporting 32-, 64- and 128-bit interface widths, with
adjustable FIFO depths and optional vertical parity generation and checking. Altera’s Cyclone FPGAs provide the
density and I/O circuitry needed to implement OC-48 traffic
management co-processing, while Stratix FPGAs deliver the
performance required for 10 Gbps applications. Stratix GX
FPGAs feature high-speed transceiver channels for a highly
integrated solution that incorporates traffic management, a
CFrame queuing engine, and a high-speed backplane interface in a single device.
Table 2. Communications IP (Part 1 of 2)
CATEGORY
VENDOR
FUNCTION DESCRIPTION
Bluetooth
Bluetooth Baseband Core
NewLogic Technologies
802.11
802.11a WLAN Baseband
Amphion Semiconductors, Ltd.
Cell/Packet
ATM Cell Processor Compiler (up to 2.5 Gbps)
Altera Corporation
PPP Packet Processor 155 and 622 Mbps
Altera Corporation
ATM Formatter
Adaptive Micro-Ware
ATM Deformatter
Adaptive Micro-Ware
AAL5 SAR (Segmentation and Reassembly)
Innocor
ATM Cell Delineator
Innocor
Packet Over SONET Controller
Innocor
Bit Error Rate Tester (BERT)
Innocor
Inverse Multiplexing for ATM (IMA)
Modelware
ATM Cell Delineation
Paxonet Communications
Commons Switch Interface - Layer 1 (CSIX-L1)
Altera Corporation
CSIX Interface
SOCmagic
8B10B Encoder/Decoder
Altera Corporation
Data Encoder/Decoder
Innocor
8B10B Encoder/Decoder
PLD Applications
Flexbus 3 Link-Layer
Modelware
Flexbus 4 (SPI-4.1)
Modelware
32 Channel HDLC
Amphion Semiconductors, Ltd.
SDLC Controller
CAST, Inc.
HDLC, Bit-Oriented
Innocor
HDLC Single Channel with FIFO Buffers
Mentor Graphics – Inventra
Multi Channel HDLC
Modelware
E3 Mapper
Altera Corporation
T3 Framer
Altera Corporation
CSIX
Encoding/Decoding
Flexbus
HDLC
PDH (T/E Carrier)
14
Altera Corporation
Table 2. Communications IP (Part 2 of 2)
CATEGORY
PDH (T/E Carrier) (cont.)
VENDOR
FUNCTION DESCRIPTION
T3 Mapper
Altera Corporation
T1 Framer
Adaptive Micro-Ware
T1 Deframer
Adaptive Micro-Ware
T1 Deframer
Mentor Graphics – Inventra
T1/E1 Framer
Mentor Graphics – Inventra
T3 Framer
Paxonet Communications
POS-PHY Level 2 PHY-Layer
Altera Corporation
POS-PHY Level 2 Link-Layer
Altera Corporation
POS-PHY Level 3 PHY-Layer
Altera Corporation
POS-PHY Level 3 Link-Layer
Altera Corporation
POS-PHY Level 4 (SPI-4.2)
Altera Corporation
POS-PHY Level 4
Innocor
POS-PHY Level 4 (SPI-4.2)
Modelware
SONET/SDH
SONET/SDH Compiler (OC-1 to OC-192)
Altera Corporation
Ethernet
10/100 Ethernet MAC
Altera Corporation
PE-GMAC0 - Gigabit Ethernet Media Access Controller
Alcatel
PE-MACMII - 10/100 Ethernet Media Access Controller
Alcatel
10/100 Ethernet MAC
CAST, Inc.
10/100/1000 Ethernet MAC
MorethanIP
10 Gigabit Ethernet MAC
MorethanIP
10 Gigabit Ethernet PCS
MorethanIP
Gigabit Ethernet to SONET Multiplexer
Nuvation
Fast Ethernet MAC Receive
Paxonet Communications
Fast Ethernet MAC Transmit
Paxonet Communications
Fibre Channel MAC
Gadzoox
10 Gigabit Fibre Channel FC-1
MorethanIP
UTOPIA Level 2 Master
Altera Corporation
UTOPIA Level 2 Slave
Altera Corporation
UTOPIA Level 3 Master
Altera Corporation
UTOPIA Level 3 Slave
Altera Corporation
UTOPIA L2 Master Receiver
AMIRIX Systems, Inc.
UTOPIA L2 Slave Transmitter/Receiver
AMIRIX Systems, Inc.
UTOPIA L3 Slave Transmitter/Receiver
AMIRIX Systems, Inc.
UTOPIA L2 Master Receive
Paxonet Communications
UTOPIA L2 Master Transmit
Paxonet Communications
UTOPIA L2 Slave Receive
Paxonet Communications
UTOPIA L2 Slave Transmit
Paxonet Communications
UTOPIA L2 to L3 Multiplexer
SOCmagic
UTOPIA L3 to L2 De-multiplexer
SOCmagic
Mercury™ Gigabit Transceiver
Altera Corporation
IX Bus
Modelware
Starfabric Link
Stargen
POS-PHY
Fibre Channel
UTOPIA
Other
Altera Corporation
15
M
Microsystems Solutions
Altera’s microsystems IP functions provide SOPC integration with standard interfaces, flexible processor cores, and
peripherals. Table 3 on page 18 lists the microsystems
interface IP, and Table 4 on page 19 lists the microsystems
processor and peripheral IP.
Interfaces
Altera’s portfolio of interface IP includes standards such as
HyperTransport™, RapidIO™, PCI, PCI-X, universal serial bus
(USB), IEEE 1394, Ethernet MAC, high-speed memory interfaces, and processor interfaces to the AMBA™ bus, PowerPC
bus, and Avalon bus (the peripheral bus used in Altera’s
Nios embedded processor solutions.)
PCI Interfaces
The PCI bus is a universal device-level
interconnect for peripherals on a circuit
board and a well known standard for expansion cards.
The PCI bus architecture is ideal for applications such as
network adapters, storage area networks, embedded controllers, graphic accelerator boards, and audio-video
products. Altera’s FPGA devices provide a programmable
logic solution for a variety of PCI applications. Altera PCI
IP supports 32- and 64-bit master/target functions at
speeds up to 66 MHz and PCI-X at speeds up to 133 MHz.
All PCI MegaCore functions are fully tested in both software and hardware to meet the requirements of the PCI
Special Internet Group (SIG), PCI Local Bus Specification
Revision 2.2 and Compliance Checklist Revision 2.2.
Altera PCI Development Kits
Altera’s PCI development kits provide a flexible hardware
platform to quickly begin hardware testing and validation
of your PCI-based design. With a variety of memory,
interfaces, and peripherals available on the standard PCI
card form factor, the PCI development kits offer a complete
design environment with support for 32- or 64-bit, 33- or
66-MHz PCI, as well as PCI-X operations. Each board
comes with a user application and a library of reference
designs to exercise PCI transactions straight out of the box.
OpenCore Plus hardware evaluation enables designers to
use these kits as the perfect prototyping platform for a
variety of interface IP. These development kits are intended
for evaluation of the PCI core and for rapid prototyping
and debugging in a real-time environment.
16
Memory Interfaces
Although Altera FPGAs provide abundant internal SRAM
memory resources on-chip, system bandwidth requirements
often necessitate the use of large, fast, off-chip memory
devices. Altera memory controller IP solutions are hardware-tested, drop-in design blocks that greatly simplify the
local interface to complex memory devices such as double
data rate (DDR) and single data rate (SDR) synchronous
dynamic random access memory (SDRAM), quad data rate
(QDR) SRAM, and zero-bus turnaround (ZBT) SRAM.
Stratix, Stratix GX, and Cyclone FPGAs include I/O features
designed specifically for interfacing with external memory
devices. These features include dedicated delay paths for
data strobe signal (DQS) alignment, multiple I/O registers to
support DDR data transmission, and delay elements to
reduce bus contention for ZBT protocols.
RapidIO
The RapidIO interface is a high-performance, packetswitched interconnect technology, designed to pass data
and control information between microprocessors, digital
signal processors, communications and network processors,
system memories, and peripheral devices.
The Stratix GX device family is ideally suited for serial or
parallel RapidIO interconnect with up to 45 receiver and 45
transmitter LVDS channels that support data transfer rates
up to 1 Gbps with integrated dynamic phase alignment
(DPA) circuitry, and up to 20 full-duplex 8B/10B encoded
transceiver channels with integrated CDR up to 3.125 Gbps.
Altera's RapidIO Physical Layer MegaCore Function leverages the Stratix and Stratix GX devices with the RapidIO
physical layer processing. This configurable function can
be used in a variety of applications with support for 8-bit
interfaces at up to 1 Gbps, 16-bit interfaces at up to
750 Mbps, and serial support up to 3.125 Gbps. The function provides buffering, flow control, error detection,
packet assembly and delineation, port training, user-defined
ordering of message retrieval, fixed start-of-packet (SOP)
alignment, and configurable Atlantic interface widths and
buffer depths.
HyperTransport
The HyperTransport interface is packet-based with two unidirectional point-to-point links found in network, storage,
computer, and embedded applications. Optimized for Stratix
and Stratix GX FPGAs, the HyperTransport MegaCore
function implements high-speed packet transfers between
physical (PHY) and link-layer devices and is fully compli-
Altera Corporation
ant with the HyperTransport specification 1.01a and 1.03.
This MegaCore function allows designers to quickly and
easily interface to a wide range of HyperTransport interface-enabled devices, including network processors, coprocessors, video chipsets, and ASICs.
Hardware tested up to 800 Mbps, the HyperTransport
MegaCore function has an 8-bit data width and supports
end chain applications. The HyperTransport MegaCore
function offers data transfer rates up to 800-Mbps per
pair of HyperTransport differential I/O pins. These high
data transfer rates take advantage of the specialized
HyperTransport differential I/O buffers in Stratix and
Stratix GX FPGAs that have been characterized and
guaranteed to achieve critical timing.
Next-Generation Processor Interfaces
A key advantage of programmable logic design is its ability
to quickly adapt to next-generation interface standards
such as the HyperTransport, RapidIO, and PCI Express standards. Working closely with ASSP vendors and the IP
development community, Altera is continuously involved in
designs that meet the bandwidth and flexibility needed for
tomorrow’s processor systems. If a required interface is not
listed in this selector guide, check for updated information
on the Altera IP MegaStore web site.
Processors & Peripherals
Excalibur Devices
Altera Excalibur devices combine
the performance of an industrystandard ARM922T™ 32-bit RISC
hard processor core with the flexibility of
programmable logic, providing a cost-effective embedded
system development platform. Excalibur devices are available
in a variety of densities and memory sizes to fit a wide range
of applications and requirements. The high-performance,
yet flexible, embedded architecture is ideal for computeintensive and high data-bandwidth applications.
SOPC Builder
SOPC Builder is an automated system generation tool
integrated with the Quartus II design software. SOPC
Builder can generate a custom embedded microprocessor
system and supports system-level architecture changes to
analyze performance tradeoffs. Using the wizard-based
SOPC Builder (shown in Figure 11), you can easily select
and customize system-level building blocks, including
Excalibur devices and Nios embedded processors, IP cores,
software libraries, and user-defined building blocks. SOPC
Builder automatically connects the hardware components
using high-performance on-chip bus architectures, and then
customizes software components to match the hardware.
Figure 11. SOPC Builder
Embedded systems IP from Altera’s microsystems portfolio
provides fully supported, high-performance soft processor
cores, along with a comprehensive library of peripheral
functions such as integrated drive electronics (IDE), universal asynchronous receiver/transmitters (UARTs), interrupt
controllers, and PCI bus bridges. These solutions enable
designers to focus on differentiating elements of the design
and use existing building blocks to create systems ranging
from interface line cards to communication systems.
Nios Embedded Processor
Altera’s Nios embedded processor is the first
RISC soft core processor to be developed
specifically for programmable logic. The Nios
embedded processor includes a 16- and 32-bit instruction
set and a user-selectable 16- or 32-bit data path. With the
complete, easy-to-use tool kit, the Nios embedded processor
can be implemented in any Altera FPGA, simplifying the
design process and improving time-to-market.
Altera Corporation
17
Table 3. Microsystem Interface IP (Part 1 of 2)
CATEGORY
VENDOR
FUNCTION DESCRIPTION
CAN
CAN 2.0 Network Controller
Mentor Graphics – Inventra
HyperTransport
HyperTransport Interface
Altera Corporation
I2C
I2C Master
CAST, Inc.
I2C Slave
CAST, Inc.
DI2CM I2C Bus Interface-Master
Digital Core Design
DI2CSB I2C Bus Interface-Slave
Digital Core Design
I2C
Mentor Graphics – Inventra
I2C Master
Sciworx
I2C Slave
Sciworx
DDR SDRAM Controller
Altera Corporation
SDR SDRAM Controller
Altera Corporation
QDR SRAM Controller
Altera Corporation
ZBT SRAM Controller
Altera Corporation
AHB to SDRAM Controller
Eureka Technology Inc.
SDRAM Controller
Eureka Technology Inc.
SDR SDRAM Controller
Northwest Logic
DDR SDRAM Controller
Northwest Logic
FCRAM Controller
Northwest Logic
PCI Compiler, 32-bit Master/Target
Altera Corporation
PCI Compiler, 32-bit Target
Altera Corporation
PCI Compiler, 64-bit Master/Target
Altera Corporation
PCI Compiler, 64-bit Target
Altera Corporation
PCI32 Nios Target
Altera Corporation
32-Bit PCI Bus Master/Target Interface
Eureka Technology Inc.
32-Bit PCI Bus Target Interface
Eureka Technology Inc.
32-Bit PCI Host Bridge
Eureka Technology Inc.
64-bit PCI Bus Master/Target Interface
Eureka Technology Inc.
64-bit PCI Bus Target Interface
Eureka Technology Inc.
64-Bit PCI Host Bridge
Eureka Technology Inc.
PCI Bus Arbiter
Eureka Technology Inc.
PCI-ISA Bridge
Eureka Technology Inc.
PCI-PCI Bridge
Eureka Technology Inc.
Integrated PCI
Northwest Logic
PCI Interface
Northwest Logic
AMBA-AHB PCI Bridge
PLDApplications
32/64-Bit PCI Bus Master/Target Interface, 33/66 MHz
PLDApplications
32/64-Bit PCI Bus Target Interface, 33/66 MHz
PLDApplications
Nios-to-PCI Bridge
PLDApplications
PCI-X Master/Target
DCM Technologies
PCI-X Master/Target, 133 MHz
PLDApplications
Infiniband
Infiniband Link Layer (IBLL)
DCM Technologies
PCMCIA
MPCMCIA1 - PCMCIA Card Interface
Mentor Graphics – Inventra
M82365SL01 - PCMCIA PC Host Interface
Mentor Graphics – Inventra
PowerPC Bus Arbiter
Eureka Technology Inc.
PowerPC Bus Master
Eureka Technology Inc.
PowerPC Bus Slave
Eureka Technology Inc.
RapidIO
RapidIO Physical Layer
Altera Corporation
USB
USB Function Controller
CAST, Inc.
USB 1.1 Function Controller
Mentor Graphics – Inventra
USB 2.0 Function Controller
Mentor Graphics – Inventra
USB 1.0 Host Controller
VinChip Systems, Inc.
USB 1.1 Device Controller
VinChip Systems, Inc.
USB 2.0 Device Controller
VinChip Systems, Inc.
Memory Controllers
PCI
PCI-X
PowerPC Bus
18
Altera Corporation
Table 4. Microsystem Processor & Peripheral IP
CATEGORY
Processors
Peripherals
Altera Corporation
VENDOR
FUNCTION DESCRIPTION
ARM922T Hard Embedded Processor
Altera Corporation
Nios Soft Embedded Processor
Altera Corporation
16-bit Microprocessor, 29116A
CAST, Inc.
4-bit Microprocessor Slice, 2901
CAST, Inc.
8-bit Microcontroller, 8051
CAST, Inc.
C165X RISC Microcontroller
CAST, Inc.
C32025 Digital Signal Processor
CAST, Inc.
C68000 Microprocessor
CAST, inc.
R8051 Microcontroller
CAST, inc.
R80515 Microcontroller
CAST, Inc.
R80530 Microcontroller
CAST, Inc.
CZ80CPU Processor
CAST, Inc.
DR8051 8-Bit RISC Microcontroller
Digital Core Design
DR8052EX 8-Bit RISC Extended Microcontroller
Digital Core Design
Microprocessor, Xtensa
Tensilica
UART, A16450P
Altera Corporation
UART, A6402
Altera Corporation
UART with FIFO Buffer
Altera Corporation
49410 Microprogram Controller
CAST, Inc.
8255A Programmable Peripheral Interface
CAST, Inc.
C8237 Programmable DMA Controller
CAST, Inc.
C8279 Programmable Keyboard/Display Interface
CAST, Inc.
CZ80CTC Programmable Counter-Timer
CAST, Inc.
CZ280P10 Programmable Parallel Input/Output Controller
CAST, Inc.
Microprogram Controller, 2910/2910A
CAST, Inc.
Microprogram Controller, 49410
CAST, Inc.
C6845 Cathode Ray Tube (CRT) Controller
CAST, Inc.
Programmable Interrupt Controller, 8259A
CAST, Inc.
Programmable Interval Timer/Counter, 8254
CAST, Inc.
Programmable Peripheral Interface, 8255A
CAST, Inc.
UART
CAST, Inc.
UART, 16450
CAST, Inc.
UART, 16450S
CAST, Inc.
UART, 16550
CAST, Inc.
UART, 16550S
CAST, Inc.
UART, 16750
CAST, Inc.
UART, 8250
CAST, Inc.
AHB Slave
Eureka Technology Inc.
AHB Master
Eureka Technology Inc.
AHB to PCI Host Bridge
Eureka Technology Inc.
AHB to SDRAM Controller
Eureka Technology Inc.
DMA Controller
Eureka Technology Inc.
ISA/PC Card/PCMCIA/Compact Flash Host Adapter
Eureka Technology Inc.
UART
Eureka Technology Inc.
Programmable Interrupt Controller, 8259
Innocor
M16550DI Enhanced UART with FIFO
Mentor Graphics – Inventra
M16550DI Enhanced UART with FIFOs and Synchronous Interface
Mentor Graphics – Inventra
M16C450 UART
Mentor Graphics – Inventra
M16X50D1 Enhanced UART with FIFO and IrDA
Mentor Graphics – Inventra
M82092IDE – IDE Controller ATA 1
Mentor Graphics – Inventra
M82371IDE – IDE Controller ATA 4
Mentor Graphics – Inventra
M8237ADI – Four-Channel DMA Controller
Mentor Graphics – Inventra
19
D
Development Kits
To support the development and verification of IP designs,
Altera and its partners provide a variety of development
and prototyping kits (see Table 5). These kits speed system
design by allowing application software development to
begin earlier in the design flow. Using these kits, hardware
designers can verify IP functionality quickly and effectively,
while software designers can use the GNUPro toolkit, the
industry-standard compiler and debugger tool suite.
Altera DSP Development Kits
Altera DSP development kits are effective platforms for
prototyping and debugging DSP designs for programmable
logic. Designers can jump-start their designs for broadband
wireless applications by implementing entire wireless modulator/demodulator subsystems in hardware within hours,
using the included hardware evaluation versions of DSP
MegaCore functions. To give users a complete out-of-the
box experience, the DSP development kits feature a Stratix
or APEX™ FPGA and include a DSP development board,
Quartus II software (one year time-limited), DSP Builder
(Quartus II MATLAB/Simulink interface), a 30-day evaluation copy of MATLAB/Simulink, system reference designs,
and OpenCore Plus hardware evaluation files. The system
reference designs are specifically targeted for high-speed
filtering, FEC, and wireless basestation systems that can be
used by designers for their broadband wireless applications.
Figure 12 shows an Altera DSP development kit.
Altera PCI Development Kits
Altera’s PCI development kits provide a flexible hardware
platform to quickly begin hardware testing and validation
of your PCI-based design. With a variety of memory, interfaces, and peripherals available on the standard PCI card
form factor, the PCI development kits offer a complete
design environment with support for 32- or 64-bit, 33- or
66-MHz PCI, as well as PCI-X operations. Each board
comes with a user application and a library of reference
designs to exercise PCI transactions straight out of the box.
OpenCore Plus hardware evaluation enables designers to
use these kits as the perfect prototyping platform for a
variety of interface IP. These development kits are intended
for evaluation of the PCI core and for rapid prototyping
and debugging in a real-time environment.
Altera Nios Development Kits
Altera’s Nios development kits provide everything needed
for embedded system development. These cost-effective kits
include the Nios embedded processor core and peripheral
functions, SOPC Builder, the GNUPro compiler and debugger
from Cygnus, a Red Hat company, the Quartus II software
(one year time-limited), and a development board. Nios
development kits are available for several different Altera
device families.
Figure 12. DSP Development Kit
20
Altera Corporation
Table 5. Development Kits
VENDOR
DEVELOPMENT KITS
DSP Development Kit (Starter Version, APEX)
Altera Corporation
DSP Development Kit (Professional Version, APEX)
Altera Corporation
DSP Development Kit, Stratix Edition
Altera Corporation
DSP Development Kit, Stratix Professional Edition
Altera Corporation
APEX PCI Development Kit (APEX EP20K400E)
Altera Corporation
APEX PCI Development Kit (APEX EP20K1000C, 66-MHz PCI)
Altera Corporation
APEX PCI Development Kit (APEX EP20K1000E, 33-MHz PCI)
Altera Corporation
FLEX® PCI Development Kit (FLEX 10K EPF10K200S)
Altera Corporation
Excalibur EPXA1 Starter Development Kit
Altera Corporation
Excalibur EPXA10 SDR Development Kit
Altera Corporation
Excalibur EPXA10 DDR Development Kit
Altera Corporation
PCI Development Kit, Stratix Edition
Altera Corporation
PCI High Speed Development Kit, Stratix Professional Edition
Altera Corporation
PCI32 Nios Target Add-On Kit
Altera Corporation
Nios Development Kit, Cyclone Edition
Altera Corporation
Nios Development Kit, Stratix Edition
Altera Corporation
Nios Development Kit, Stratix Professional Edition
Altera Corporation
Nios Development Kit, APEX Edition
Altera Corporation
Nios Ethernet Development Kit
Altera Corporation
Stratix Video Processing Development Kit
Avvida
DIGILAB 10K10 Development Board and Starter Kit
El Camino GmbH
DIGILAB 10Kx240 Prototyping Board
El Camino GmbH
DIGILAB 20Kx240 Development Board
El Camino GmbH
DIGILAB picoMAX Prototyping Board and Starter Kit
El Camino GmbH
PROC10K Protyping Board
Gid'el Limited
PROC20K Protyping Board
Gid'el Limited
Stratix PROCStar Kit
Gid'el Limited
Stratix Embedded Kit
MJL
Stratix Technology Kit
MJL
Linux Development Kit (used with Nios Development Kit)
Microtronix
Bluetooth Prototype Board
NewLogic Technologies
Constellation - 10K Prototype Board
Nova Engineering, Inc.
Constellation - 10KE Prototype Board
Nova Engineering, Inc.
Constellation - 20KE Prototype Board
Nova Engineering, Inc.
Smartpack
Parallex
PCI10K-PROD PCI Application Platform
PLDApplications
PCI20K-PROD PCI Application Platform
PLDApplications
PCISYS Data Acquisition and Processing PCI Board
PLDApplications
Megalogic 2A15 Development Board (APEX II)
Princeton Technology Group
Megalogic System 100 Development Board (FLEX 10K)
Princeton Technology Group
Flexible I/O Products (PC104+ Style)
RPA Electronics Design, LLC
Stratix HS Kit
Rapid Technology
PMC Stratix Kit
Rapid Technology
XT1000 Device Emulation Kit
Tensilica
Altera Corporation
21
AMPP Partner Directory
Table 6 lists the Altera AMPP Partners. For the most current list of Premier AMPP, AMPP, and AMPP Software partners,
visit the Altera IP MegaStore web site.
Table 6. AMPP Partner Directory (Part 1 of 2)
PARTNER
ADDRESS
TELEPHONE
E-MAIL & WEB ADDRESS
Premier AMPP Partners
Innocor Ltd.
7 Mill Street, Suite 300, Almonte, ON,
Canada K0A 1A0
(613) 256-5339
info@innocor.com
www.innocor.com
Nova Engineering
5 Circle Freeway Drive, Cincinnati, OH,
USA 45246-1105
(513) 860-3456
info@nova-eng.com
www.nova-eng.com
PLDApplications
32 ZAC de Bompertius-Avenu d'Armenie,
F-13120 Gardanne, France
(33) 442-654-388
email@plda.com
www.plda.com
Adaptive Micro-Ware
6917 Innovation Boulevard, Fort Wayne, IN, USA
46818
(260) 489-0046
ipcores@adaptivemicro.com
www.adaptivemicro.com
Alcatel-Technology
Licensing Group
11707 East Sprague, Suite 106, Spokane, WA,
USA 94206
(509) 777-7330
ipinfi@ind.alcatel.com
www.ind.alcatel.com/enterprise/
products/ip/index.html
AMIRIX
77 Chain Lake Drive, Halifax, NS,
Canada B3S 1E1
(902) 450-1788
info@amirix.com
www.amirix.com
Amphion
50 Malone Road, Belfast, BT9 5BS,
Northern Ireland
(44) 1232-664-664
info@amphion.com
www.amphion.com
Barco Silex
Rue du Bosquet 7, B-1348 Louvain-la-Neuve,
Belgium
(32) 10-86-403
Geert.Decorte@barco.com
www.barco-silex.com
Robert Bosch GmbH
Wernerstrasse 1, D-70469 Stuttgart,
Germany
(49)-(0)711-811-33150
Gerhard.Holfelder@de.bosch.com
www.can.bosch.com
CAST, Inc.
24 White Birch Drive, Pomona, NY,
USA 10970
(914) 354-4945
opencore@cast-inc.com
www.cast-inc.com
Commstack, Inc.
72 Fairfax Avenue, Atherton, CA,
USA 94027
(650) 701-0939
info@commstack.com
www.commstack.com
Paxonet
Communications
46750 Fremont Boulevard, Suite 208, Fremont,
CA, USA 94538
(510) 770-2277
sales@paxonet.com
www.paxonet.com
Digital Core Design
Wroclawska 94, 41-902 Bytom, Poland
(48) 32-282-8266
info@dcd.com.pl
www.dcd.com.pl
DCM Technologies
7501A Capitol of Texas Hwy., Suite 140, Austin,
TX, USA 78731
(510) 710-7686
info@dcmtech.com
www.dcmtech.com
D’crypt Pte. Ltd.
20 Ayer Rajah Crescent, #08-08,
Singapore 139964
(65) 773-9016
ipcore@d-crypt.com
www.d-crypt.com
Eureka Technology
4962 El Camino Real, Suite 108, Los Altos, CA,
USA 94022
(415) 960-3800
info@eurekatech.com
www.eurekatech.com
Gadzoox Networks
2902 Stender Way, Santa Clara, CA,
USA 95054
(408) 235-8406
greg.lara@gadzoox.com
www.gadzoox.com
Mentor Graphics –
Inventra
1001 Ridder Park Drive, San Jose, CA,
USA 95131
(408) 451-5670
inventra_fpga@mentor.com
www.mentor.com/inventra/netlist.
program
ModelWare
10 West Bergen Place, #105, Red Bank, NJ,
USA 07701
(732) 936-1808
info@modelware.com
www.modelware.com
MorethanIP
An der Steinernen Bruecke 1, D-85757, Karlsfeld
Germany
(49) 81-31-333-9390
info@morethanip.com
www.morethanip.com
NewLogic Technologies
Millennium Park 6, A-6890 Lustenau, Austria
(43) 5577-62000-0
info@newlogic.com
www.newlogic.com
AMPP Partners
22
Altera Corporation
M
M
M
Table 6. AMPP Partner Directory (Part 2 of 2)
PARTNER
ADDRESS
TELEPHONE
E-MAIL & WEB ADDRESS
AMPP Partners (cont.)
NComm, Inc.
254 North Broadway, Suite 106, Salem, NH, USA
03079
(603) 893-6186
sales@ncomm.com
www.ncomm.com
Nuvation
234 East Gish Road, San Jose, CA, USA 95112
(408) 573-1500
ipcores@nuvation.com
www.nuvation.com
Nortwest Logic
2460 NE Griffin Oaks Street, Suite 1000,
Hillsboro, OR, USA 97124
(503) 533-5800
ip@nwlogic.com
www.nwlogic.com
Paxonet
Communications
46750 Fremont Boulevard, Suite 208, Fremont,
CA, USA 94538
(510) 770-2277
sales@paxonet.com
www.paxonet.com
Sciworx
Garbsener Landstr. 10, 30419 Hannover Germany
(49) 511-277-1491
info@sci-worx.com
www.sci-worx.com
SOCmagic
Shekou Cuiweiyuan, 1-203 Shenzhen, 51807,
China
(86) 755-686-1129
jerry@socmagic.com
www.socmagic.com
Stargen
225 Cedar Hill Street, Suite 22, Marlborough,
MA, USA 01752
(508) 786-9950
info@stargen.com
www.stargen.com
Tensilica, Inc.
3255-6 Scott Boulevard, Santa Clara, CA,
USA 95054
(408) 873-1000,
Ext. 302
sales@hq.tensilica.com
www.tensilica.com
TurboConcept
1 avenue du technopole, 29280 Plouzane, France
(33) 2-29-00-12-24
info@turboconcept.com
www.turboconcept.com
VinChip Systems, Inc.
13 Burnham Place, Fremont, CA, USA 94539
(408) 879-2062
info@vinchip.com
www.vinchip.com
Future Software Ltd.
4300 Stevens Creek Boulevard, Suite 187, San
Jose, CA, USA 95129
(408) 243 3887,
Ext. 114
info@futsoft.com
www.futsoft.com
HelloSoft, Inc.
2542 South Bascom Avenue Suite 203, Campbell,
CA, USA 95008
(408) 377 0110,
Ext. 111
info@hellosoft.com
www.hellosoft.com
NComm, Inc.
254 North Broadway, Suite 106, Salem, NH, USA
03079
(603) 893-6186
sales@ncomm.com
www.ncomm.com
AMPP Software Partners
Altera Corporation
23
Altera Offices
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
USA
Telephone: (408) 544-7000
www.altera.com
Altera European Headquarters
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1 494 602 000
Altera Japan Ltd.
Shinjuku i-Land Tower 32F
6-5-1, Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
www.altera.com/japan
Altera International Ltd.
2102 Tower 6
The Gateway, Harbour City
9 Canton Road
Tsimshatsui Kowloon
Hong Kong
Telephone: (852) 2945 7000
Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words and logos that
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logo, AMBA, and ARM922T are registered trademarks of ARM Limited. RapidIO is a trademark of the RapidIO Trade Association. HyperTransport is a trademark of the HyperTransport
Consortium. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications,
mask work rights, and copyrights.
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