SONET STS-3 Framer
MegaCore Function
(STS1X3FRM)
June 2001; ver. 1.01
Features
Data Sheet
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Typical
Applications
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants
Quartus® II software and OpenCore® feature allow place-and-route,
and static timing analysis of designs prior to licensing
Secure register transfer level (RTL) simulation models allow
simulation with user design in third-party simulators
Performs synchronous optical network (SONET)/synchronous
digital hierarchy (SDH) framing and transport convergence (TC)
Processes transport overhead (TOH) and path overhead (POH),
using three independent path processors
Supports a data rate of up to 155.52 (3 × 51.84) megabits per second
(Mbps)
Optimized for the Altera® APEXTM 20KE device architecture
Figure 1 shows three independent example system implementations of
the STS1X3FRM connecting to other Altera MegaCore variants via three
Midbus interfaces, and three serial Mapper interfaces. See “Interfaces &
Protocols” on page 4 for more information.
The system implementations include:
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Altera Corporation
A-DS-IPSTS1X3FRM-1.01
An STS1X3FRM interfacing to a T3 Mapper (T3MAP) and T3 Framer
(T3FRM)
An STS1X3FRM interfacing to an E3 Mapper (E3MAP) and E3 Framer
(E3FRM)
An STS1X3FRM interfacing to a VT 1.5 Mapper (VT1P5MAP) and T1
Framer (T1FRM)
Other applications are possible, including:
ATM switches
Digital cross-connection (DCC) systems
Routers
Multiplexers
1
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Figure 1. Typical Applications
STS1X3FRM interfacing to a T3MAP and T3FRM
Midbus
Interfaces
rxclk
Line
Interface
Circuit
Clock
Data
Recovery
Serializer
Deserializer
SONET
STS-3
Framer
(STS1X3FRM)
txclk
External
CPU
CPU Bus
Processor
Interface
Block
Mapper
Interfaces
T3 Mapper
(T3MAP)
T3 Framer
(T3FRM)
T3 Mapper
(T3MAP)
T3 Framer
(T3FRM)
T3 Mapper
(T3MAP)
T3 Framer
(T3FRM)
AIRbus
APEX 20K Boundary
STS1X3FRM interfacing to an E3MAP and E3FRM
Midbus
Interfaces
rxclk
Line
Interface
Circuit
Clock
Data
Recovery
Serializer
Deserializer
SONET
STS-3
Framer
(STS1X3FRM)
txclk
External
CPU
CPU Bus
Processor
Interface
Block
Mapper
Interfaces
E3 Mapper
(E3MAP)
E3 Framer
(E3FRM)
E3 Mapper
(E3MAP)
E3 Framer
(E3FRM)
E3 Mapper
(E3MAP)
E3 Framer
(E3FRM)
AIRbus
APEX 20K Boundary
STS1X3FRM interfacing to a VT1P5MAP and T1FRM
Mapper
Interfaces
Midbus
Interfaces
rxclk
Line
Interface
Circuit
Clock
Data
Recovery
Serializer
Deserializer
txclk
External
CPU
2
CPU Bus
Processor
Interface
Block
SONET
STS-3
Framer
(STS1X3FRM)
VT 1.5 Mapper
(VT1P5MAP)
T1 Framer
28 channels
(T1FRMX28)
VT 1.5 Mapper
(VT1P5MAP)
T1 Framer
28 channels
(T1FRMX28)
VT 1.5 Mapper
(VT1P5MAP)
T1 Framer
28 channels
(T1FRMX28)
AIRbus
APEX 20K Boundary
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
The STS1X3FRM complies with all applicable standards, including:
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Functional
Description
The STS1X3FRM operates in full-duplex mode, and comprises four
blocks, as illustrated in Figure 2. Path processing is independent for each
of the three paths.
Altera Corporation
American National Standards Institute (ANSI), Synchronous Optical
Network (SONET) –Basic Description including Multiplex Structure,
Rates, and Formats, ANSI T1-105–1995.
American National Standards Institute (ANSI), Synchronous Optical
Network (SONET) –Payload Mappings, ANSI T1-105.02–1995.
Telcordia, Synchronous Optical Network (SONET) Transport Systems:
Common Generic Criteria, GR-253-CORE, Issue 3, September 2000.
Telcordia, Synchronous Optical Network (SONET) Transport Systems:
Common Generic Criteria Issue List Report, GR-253-ILR, Issue 3A,
October 2000.
International Telecommunication Union, Network node interface for the
synchronous digital hierarchy (SDH), ITU-T Recommendation G. 707,
March 1996
International Telecommunication Union, Characteristics of
synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T
Recommendation G. 783, January 1994
The following list of functions is based on a full feature
STS1X3FRM. See Table 2 for all possible options.
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Transport overhead receiver (RXTOH)
–
Inputs raw SONET data
–
Descrambles the data
–
Performs frame alignment
–
Performs error checking
–
Maintains counters and buffers
–
Captures the TOH bytes for processing by software, and
parameterized hardware extraction
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Path overhead receiver (RXPOH_0,_1,_2)
–
Processes the pointer
–
Performs error checking
–
Maintains counters and buffers
–
Captures the POH bytes for processing by software, and
parameterized hardware extraction
–
Outputs payload data
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Transport overhead transmitter (TXTOH)
–
Generates the pointer (normal, positive stuff, negative stuff, or
new data flag (NDF) selected by software)
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SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
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Interfaces &
Protocols
Allows the flexible insertion of the TOH by software, or by
parameterized hardware
Generates parity bytes
Maintains counters and buffers
Scrambles the data
Outputs raw SONET data
Path overhead transmitter (TXPOH_0,_1,_2)
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Inputs payload data
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Allows the flexible insertion of the POH by software, or by
parameterized hardware
–
Generates parity bytes
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Maintains counters and buffers
Two interfaces support the STS1X3FRM: the middle interface (Midbus),
and the access to internal registers (AIRbus) interface.
Midbus
The Midbus interface is a simple synchronous full-duplex data path bus.
The STS1X3FRM Midbus runs at 19.44 MHz over a single byte lane in each
direction. In the receive (RX) direction, data is transferred from the
Midbus master (RXPOH_0,_1,_2) to the slave. In the transmit (TX)
direction, data is transferred from the slave to the master
(TXPOH_0,_1,_2). In each direction, RX and TX, the Midbus can carry
eight bits per clock cycle. It includes Midbus receive data
(mrxdat_0,_1,_2[7:0]) and Midbus receive
enable(mrxena_0,_1,_2) lines to indicate valid data transfers in the RX
direction, and Midbus transmit data (mtxdat_0,_1,_2[7:0]) and
Midbus data enable(mtxena_0,_1,_2) lines to indicate valid data
requests in the TX direction.
AIRbus
The AIRbus interface provides access to internal registers using a simple
synchronous internal bus protocol. This consists of separate read data
(rdata[31:0]) and write data (wdata[31:0]) buses, a data transfer
acknowledge (dtack) signal, and a block select (sel) signal. An address
(addr[12:2]) bus and read (read) signal indicate the location and type
of access within the block. The rdata buses and dtack signals can be
merged from multiple blocks using a simple OR function. The dtack
signal is sustained until the block sel is removed (four-way
handshaking), meaning the AIRbus can cross clock domain boundaries. In
this block the AIRbus has a data width of 32 bits.
B
4
More detailed information on the Midbus, and AIRbus is available from
the Altera web site at http://www.altera.com/IPmegastore.
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Figure 2. Block Diagram
rxpohfp_0,_1,_2
rxpohval_0,_1,_2
rxclk_en
rxreset_n
RXTOH
RXPOH_0
_1 _2
mrxdat_0,_1,_2[7:0]
mrxena_0,_1,_2
mrxval_0,_1,_2
mrxffp_0,_1,_2
mrxefp_0,_1,_2
mrxfoh_0,_1,_2
mrxeoh_0,_1,_2
TXPOH_0
_1 _2
mtxdat_0,_1,_2[7:0]
mtxena_0,_1,_2
mtxval_0,_1,_2
mtxffp_0,_1,_2
mtxefp_0,_1,_2
mtxfoh_0,_1,_2
mtxeoh_0,_1,_2
rxclk domain
txpohen_0,_1,_2
txpohfp_0,_1,_2
txpohrdy_0,_1,_2
txpoh_0,_1,_2
sel
read
addr[12:2]
rdata[31:0]
wdata[31:0]
dtack
irq
AIRbus
txpohclk_0,_1,_2
TOH Insert
txclk
txclk_en
txreset_n
TXTOH
stxdat[7:0]
stxval
stxfr
stxfp
txtohclk
txtoh
txtohen
txtohfp
txtohrdy
txsdcc
txsdccrdy
txldcc
txldccrdy
txe1f1e2
txe1f1e2fp
txe1f1e2rdy
SONET
txclk domain
Midbus
SONET
srxdat[7:0]
srxval
srxfr
align_data[7:0]
lopc
los
lof
sef
rxclk
rxtohclk
rxtoh
rxtohval
rxtohfp
rxsdcc
rxsdccval
rxldcc
rxldccval
rxe1f1e2
rxe1f1e2val
rxe1f1e2fp
TOH Extract
rxpoh_0,_1,_2
rxpohclk_0,_1,_2
POH Extract
POH Insert
I/0 Signals
The following is a port list for the STS1X3FRM. The signal direction is
indicated by (I) for input, or (O) for output.
RX Clock Domain Signals: rxclk (I), rxclk_en (I), rxreset_n (I);
SONET Signals: srxdat[7:0](I), srxval (I), srxfr (I); Maintenance
Signals: align_data[7:0](O), lopc (I), los (O), lof (O), sef (O);
Hardware Serial TOH Extract Signals: rxtohclk (O), rxtoh (O),
rxtohval (O), rxtohfp (O), rxsdcc (O), rxsdccval (O), rxldcc (O),
rxldccval (O), rxe1f1e2 (O), rxe1f1e2val (O), rxe1f1e2fp (O);
Hardware Serial POH Extract Signals: rxpohclk_0,_1,_2 (O),
rxpoh_0,_1,_2 (O), rxpohval_0,_1,_2 (O), rxpohfp_0,_1,_2
(O); Midbus Signals: mrxdat_0,_1,_2[7:0] (O), mrxena_0,_1,_2
(O), mrxval_0,_1,_2 (O), mrxffp_0,_1,_2 (O), mrxefp_0,_1,_2
(O), mrxfoh_0,_1,_2 (O), mrxeoh_0,_1,_2 (O).
Altera Corporation
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SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
AIRbus Signals: sel (I), read (I), addr[12:2] (I), rdata[31:0] (O),
wdata[31:0] (I), dtack (O), irq (O).
TX Clock Domain Signals: txclk (I), txclk_en (I), txreset_n (I);
SONET Signals: stxdat[7:0] (O), stxval (O), stxfr (I), stxfp (O);
Hardware Serial TOH Insert Signals: txtohclk (O), txtoh (I),
txtohen (I), txtohfp (O), txtohrdy (O), txsdcc (I), txsdccrdy (O),
txldcc (I), txldccrdy (O), txe1f1e2 (I), txe1f1e2fp (O),
txe1f1e2rdy (O); Hardware Serial POH Insert Signals:
txpohclk_0,_1,_2 (O), txpoh_0,_1,_2 (I), txpohen_0,_1,_2 (I),
txpohfp_0,_1,_2 (O), txpohrdy_0,_1,_2 (O); Midbus Signals:
mtxdat_0,_1,_2[7:0] (I), mtxena_0,_1,_2 (O), mtxval_0,_1,_2
(O), mtxffp_0,_1,_2 (O), mtxefp_0,_1,_2 (O), mtxfoh_0,_1,_2
(O), mtxeoh_0,_1,_2 (O).
Performance
Table 1 shows the required speed and estimated gate count of the
STS1X3FRM in an APEX 20KE device.
Table 1. Performance
Note (1)
LEs
ESBs
fMAX (MHz)
8,395 – 12,132
5 – 21
19.44 to support 155.52 Mbps
Note:
(1)
Generating
Variants
The numbers for the logic elements (LEs) and embedded system blocks (ESBs) are
approximate as of May 25, 2001. They reflect the range from the basic to the full
feature variant.
Table 2 shows the optional features available to generate all variants.
Table 2. Optional Features
Note (1)
Options
Parameters Choices
LEs
ESBs
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8,395
5
Serial insertion/extraction of TOH and POH bytes
SOH
Y/N
1,005
0
64-byte insert, extract, and expect buffers
Automatic monitoring of extracted section trace J0 (transport overhead)
J0B
Y/N
212
3
64-byte insert, extract, and expect buffers
Automatic monitoring of extracted path trace J1 (path overhead)
J1B
Y/N
944
9
BM1S
Y/N
1,584
4
Basic Configuration
Bit error rate monitoring with one second window
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Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Note from Table 2:
(1)
The numbers for the LEs and ESBs are approximate as of May 25, 2001. Users are strongly advised to run the
MegaWizard Plug-In and the Quartus II software to see exact numbers for each STS1X3FRM variant.
Licensing
A license is not required to perform the following trial operations using
your own custom logic:
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Instantiation
Place-and-route
Static timing analysis
Simulation on a third-party simulator
Only when you are ready to generate programming files, do you need to
obtain licenses through your local Altera sales representative.
Deliverables
The following elements are provided with the STS1X3FRM package:
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101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
lit_req@altera.com
7
All current variants use a single license with ordering code:
PLSM-STS1X3FRM.
Data sheet
User guide
Midbus and AIRbus interface functional specifications
MegaWizard Plug-In
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Encrypted gate level netlist
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Place-and-route constraints (where necessary)
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Secure RTL simulation model
Demo testbench
Access to problem reporting system
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks
and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the
trademarks of other organizations for their respective products or services mentioned in this document. Altera
products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights,
and copyrights. Altera warrants performance of its semiconductor products to current specifications in
accordance with Altera’s standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out
of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to
obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
Copyright 2001 Altera Corporation. All rights reserved.
Altera Corporation
