®
HardCopy
The Ideal Solution for High-Density PLD Migration
September 2001
The Ideal Solution for HighDensity PLD Migration
Figure 1. HardCopy Die Size
The decision to migrate from a highdensity programmable logic device
70% Reduction
in Die Size
(PLD) to an ASIC is a difficult one.
Uncertainty, development costs,
resource issues, time-to-market
pressures, and conversion risks are just a few of the difficult
challenges product development teams face. Altera now offers
a new solution: HardCopy™ devices. Through a combination of
proprietary silicon design and an automated conversion
APEX 20KE
EP20K1500E
process, Altera helps customers to move seamlessly from a
programmable solution to a low-cost, custom implementation
of their designs. As a result, Altera® HardCopy devices extend
the flexibility, power, and time-to-market advantages of high-
HardCopy
HC20K1500
reduce costs and shorten time-to-market because they are a
natural extension of the flexibility of PLDs.
density PLDs to the higher volume, more cost-sensitive
applications traditionally covered by ASICs. Using HardCopy
HardCopy devices provide many cost advantages:
devices, customers can leverage Altera’s solutions from
■ Significantly lower unit cost due to a die size shrink of up
prototype to production, while reducing costs and accelerating
time-to-market.
HardCopy devices, a risk-free alternative to ASICs, are created
by Altera’s proprietary design conversion methodology. They
are directly based on Altera PLD architectures and use an
area-efficient sea-of-logic-elements core. Essentially,
HardCopy devices are an exact reproduction of the PLD of
choice with the programmability removed and the customerspecific configuration and routing implemented using metal
interconnect. The result is a much smaller and more cost-
to 70% (see Figure 1)
■ Lower non-recurring engineering (NRE) costs than ASICs’
equivalent technology
■ Lower total cost of ownership (see Figure 2)
■ No requirement for customer design engineering resources
■ No additional licensing fees or recharacterization when
converting Altera MegaCore® functions for use in
HardCopy devices
effective device (see Figure 1).
■ Guaranteed device functionality and performance
The HardCopy products support Altera’s high-density
Using HardCopy devices saves money, time, and resources, all
APEX™ 20KE, APEX 20KC, Excalibur™, and APEX II devices.
with no risk. Together, these advantages result in a significant
HardCopy devices are manufactured with the same process
reduction to the cost of ownership that no ASIC conversion
technology as their APEX 20K, Excalibur, and APEX II
can match.
counterparts (see Table 1).
Figure 2. HardCopy Cost Ownership
Reduce Development Costs
Opportunity Cost
Unit Cost
NRE Cost
Development Cost
Designing and implementing complex ASICs is becoming
increasingly expensive and sometimes prohibitive. Creating
a system-on-a-chip (SOC) requires integrating complex
functions such as embedded memory blocks and soft- and/or
hard-core embedded processors along with other complex IP
cores and logic. In addition, the rapid evolution of
Total
Cost ($)
technology, features, and standards can result in shortened
product life and rapidly escalating revision costs. The
development cost of high-density, full-featured ASIC designs
with state-of-the-art technology requires an extensive budget
and months of engineering resources. HardCopy devices
Altera Corporation
ASIC
HardCopy
Seamless Conversion Process
The conversion process uses Altera-developed software and
industry-leading, third-party design tools (see Figure 3).
Altera’s proprietary design conversion methodology generates
a HardCopy device that matches the exact functionality of its
PLD counterpart and offers equal or better performance. To
convert a high-density PLD design to a HardCopy device,
Customers do not need to provide test vectors or run extensive
functional and timing simulations to verify the conversion.
Because Altera performs all of the conversion tasks, HardCopy
requires very little customer effort.
Altera requires output files directly from the Quartus® II
software. Customers do not need to resynthesize their design
State-of-the-Art Features
to target a specific ASIC library, and they do not need to
HardCopy devices offer design flexibility and high-
invest in costly ASIC development tools.
performance system-integration. They support the highAltera requires the following output files to complete the
HardCopy conversion process:
density APEX 20KE, APEX 20KC, APEX II, and Excalibur
devices and designs, including the Nios™ embedded processor.
■ SRAM Object File (.sof)
HardCopy devices support powerful system-level device
features such as:
■ Compiler Setting Report File (.csf.rpt)
■ Packaging: HardCopy devices are available in the same
■ Pin-out File (.pin)
packages with the same pin-outs as the corresponding PLD,
■ Standard Delay Format Output File (.sdo)
■ Verilog Output File (.vo)
maintaining pin-compatibility (see Table 1).
■ Performance: Altera guarantees that the performance of
HardCopy devices will be equal or better than the highest
Figure 3. HardCopy Design Flow
speed grade version of the PLD being converted. Careful
Customer
Deliver SRAM Object
File to Altera
scaling and tight timing controls ensure no timing
Altera
Generate Netlist
violations are introduced during the conversion.
■ Features: HardCopy devices maintain the exact features of
the corresponding PLD circuitry, including the look-up
Check for Test & Fix
table (LUT) logic structure, True-LVDS™ circuitry, embedded
Place & Route
system blocks (ESBs), phase-locked loops (PLLs), all
Verify Timing
supported I/O standards, MultiVolt™ operation, and leadingedge process technology. This eliminates any need to
Fabricate Prototypes
recharacterize the HardCopy device when its programmable
counterpart is already qualified.
Assembly & Test
Customer Receives Prototypes
Send Prototypes to Customer
Customer Approves Prototypes
Volume Production
■ Built-in testability: All HardCopy devices include enhanced
scan capability automatically inserted during conversion.
Altera automatically generates production test vectors with
a high fault coverage and does not require any customergenerated test vectors.
The SRAM Object File (.sof) generated by the Quartus II
software is used as the input to the HardCopy conversion
■ Intellectual property: Migration of Altera MegaCore® and
process. The other files are required for verification purposes.
Altera Megafunction Partners Program (AMPPSM)
Table 1. HardCopy Device Packaging
Devices
Family
Packages
APEX 20K
EP20K400E, EP20K600E, EP20K1000E, EP20K1500E,
EP20K400C, EP20K600C, EP20K1000C
652-Pin BGA, 672-Pin FineLine BGA™,
1,020-Pin FineLine BGA
Excalibur
EPXA4, EPXA10
612-Pin BGA, 864-Pin BGA, 672-Pin FineLine BGA,
1,020-Pin FineLine BGA
APEX II
EP2A25, EP2A40, EP2A70
724-Pin BGA, 672-Pin FineLine BGA,
1,020-Pin FineLine BGA, 1,508-Pin FineLine BGA
Altera Corporation
Figure 4. Implementation Timeline
Conversion &
Verification
Prototype
Fabrication
Prototype
Signoff
Production
2 to 3 Weeks
5 Weeks
1 to 2 Weeks
8 Weeks
16 to 18 Weeks
megafunctions from the PLD to the HardCopy device is
seamless; no customer involvement is necessary. In
Contact Altera Today
addition, customers pay no extra licensing fees for
HardCopy devices provide the best high-volume production
converting Altera IP functions.
solution for your high-density PLD designs. Visit the Altera
■ Power consumption: HardCopy devices use significantly
less power than their PLD counterparts in most designs.
web site today to learn more about HardCopy devices and
Altera SOPC solutions at http://www.altera.com.
Faster Time-to-Market
Using competitively priced HardCopy devices, manufacturers
can enjoy all the benefits of an ASIC and take advantage of
shorter development times, expedited production schedules,
and fast time-to-market. With an easy conversion process,
minimal customer involvement, and base wafers already
manufactured and ready for customization, Altera HardCopy
devices can deliver guaranteed, fully operational production
units and prototypes in the shortest time possible, as shown in
Figure 4. As system-on-a-programmable-chip (SOPC) design
features and IP requirements become more and more complex,
HardCopy devices provide the fastest way to convert highdensity PLD designs to a no-risk, low cost device.
®
The Programmable Solutions Company ®
Altera Offices
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Telephone: (408) 544-7000
http://www.altera.com
Altera U.K., Ltd.
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1 494 602 000
Altera Japan, Ltd.
Shinjuku i-Land Tower 32F
5-1, Nishi-Shinjuku, 6 Chome
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
http://www.altera.com/japan
Altera International, Ltd.
2102 Tower 6
The Gateway, Harbour City
9 Canton Road,
Tsimshatsui, Kowloon
Hong Kong
Telephone: (852) 2945-7000
Copyright © 2001 Altera Corporation. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks
are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. Other brands or products are trademarks of their respective holders.
The specifications herein are subject to change without notice. All rights reserved.
M-GB-HARDCOPY-01