® Stratix New Levels of System Integration October 2002 New Levels of System Integration Introducing Stratix™ FPGAs, Altera’s newest product family that breaks the performance and density barriers for high-density programmable logic. The Stratix family is the first programmable logic device (PLD) family designed to enable a comprehensive block-based design methodology. For the first time, in conjunction with the Quartus® II design software, designers can optimize and lock the performance of individual design blocks even when blocks are moved or integrated with other optimized functions. By eliminating the time-consuming process of performance re-optimization during system integration, Stratix FPGAs significantly enhance the time-to-market advantages of highdensity programmable logic. In fact, Stratix devices deliver on average a 50%—and as high as 100%—improvement in push-button performance over previous architectures. Stratix FPGAs are based on a 1.5-V, 0.13-µm, all-layer-copper SRAM process, with densities ranging from 10,570 to 114,140 logic elements (LEs). The Stratix family offers up to 10 Mbits of embedded RAM with its TriMatrix™ memory structure. With three sizes of memory blocks, the TriMatrix memory structure is optimized for high-memory bandwidth and large memory storage requirements. Stratix devices include up to 28 digital signal processing (DSP) blocks that eliminate the performance bottlenecks in arithmetic applications. Comprised of multiply and accumulate circuitry, the DSP blocks provide predictable performance and significant resource savings for complex applications that require high data throughput. With up to 12 phase-locked loops (PLLs), up to 40 system clocks, and support for many single-ended and differential I/O electrical standards, Stratix devices bring new levels of system integration for system-on-aprogrammable-chip (SOPC) designs. Table 1 describes some of the highlights of the Stratix devices, and Table 2 shows the wide range of features and packages available. High-Bandwidth Solution The Stratix device family was specifically designed to address the increasing bandwidth requirements of high-speed systems. All aspects of bandwidth are increased: overall memory bandwidth, arithmetic bandwidth for DSP applications, I/O bandwidth, and core performance. Built on the performance-optimized and highly flexible MultiTrack™ continuous routing structure, Stratix devices offer dramatically higher core performance than any other previous architecture. Combined with embedded features such as TriMatrix memory, DSP blocks, and dedicated highspeed I/O interfaces, Stratix devices deliver the best possible system integration to meet the requirements of highbandwidth systems. TriMatrix Memory Stratix devices feature the TriMatrix memory structure, made up of three sizes of embedded RAM blocks. TriMatrix memory includes the 512-bit M512 blocks, the 4-Kbit M4K blocks, and the 512-Kbit M-RAM blocks, each of which can be configured to support a wide range of features. Each embedded RAM block in the TriMatrix memory structure targets a different class of applications: the M512 blocks Table 1. Stratix Highlights Feature 2 Benefit High-Performance Architecture New routing structure that provides the basis for block-based design methodology for maximum system performance with minimum development time TriMatrix Memory Three sizes of embedded memory blocks with up to 10 Mbits of RAM, up to 12 terabits per second of memory bandwidth, and data transfer rates of over 250 MHz DSP Blocks Predictable 300-MHz performance for data throughput of up to 2.4 GMACS per DSP block High-Bandwidth I/O Standards and High-Speed Interfaces Support for high-speed I/O standards and high-speed interfaces such as 10-Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4, HyperTransport™, RapidIO™, and UTOPIA Level 4 interfaces at up to 840 Mbps, as well as support for advanced external memory device interfaces Clock Management Circuitry Up to 12 PLLs and up to 40 system clocks with features such as clock switchover, PLL reconfiguration, spreadspectrum clocking, frequency synthesis, and programmable phase and delay shift Terminator™ Technology On-chip serial, parallel, and differential termination, and driver impedance matching Remote System Upgrades Real-time updates to PLDs from remote locations Cost Reduction Migration Path Cost-reduction migration path to HardCopy™ devices supported for high-density Stratix devices Altera Corporation Table 2. Stratix Family Overview Feature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 EP1S120 LEs 10,570 18,460 25,660 32,470 41,250 57,120 79,040 114,140 M512 RAM Blocks (512 bits + parity) 94 194 224 295 384 574 767 1,118 M4K RAM Blocks (4 Kbits + parity) 60 82 138 171 183 292 364 520 M-RAM Blocks (512 Kbits + parity) 1 2 2 4 4 6 9 12 10,118,016 Total RAM Bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520 DSP Blocks 6 10 10 12 14 18 22 28 Embedded Multipliers (1) 48 80 80 96 112 144 176 224 PLLs Maximum User I/O Pins Available Packages 6 6 6 10 12 12 12 12 426 586 706 726 822 1,022 1,238 1,314 956-Pin BGA 956-Pin BGA 672-Pin BallGrid Array (BGA) 672-Pin BGA 672-Pin BGA 956-Pin BGA 956-Pin BGA 484-Pin 672-Pin 780-Pin 1,020-Pin 1,020-Pin 1,508-Pin FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA 1,923-Pin FineLine BGA 484-Pin 672-Pin 780-Pin 1,020-Pin 1,508-Pin 1,508-Pin 1,923-Pin FineLine BGA® FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA FineLine BGA 672-Pin 780-Pin 1,020-Pin FineLine BGA FineLine BGA FineLine BGA 780-Pin FineLine BGA Note: (1) Total number of embedded 9x9 multipliers. To obtain the total number of 18x18 multipliers per device, divide the total number of 9x9 multipliers by 2. To obtain the total number of 36x36 multipliers per device, divide the total number of 9x9 multipliers by 8. can be used for small functions such as first-in first-out (FIFO) applications; the M4K blocks can be used to store incoming data from multi-channel I/O protocols, and the M-RAM blocks can be used for storage-intensive applications such as Internet protocol packet buffering or as program/data memory for an on-chip Nios® embedded processor. All memory blocks include extra parity bits for error control, embedded shift register functionality, mixed-width mode, and mixed-clock mode support. Additionally, the M4K and M-RAM blocks support true dual-port mode and byte masking for advanced write operations. With up to 10 Mbits of RAM and up to 12 terabits per second of device memory bandwidth, TriMatrix memory offers the highest memory-to-logic ratio and the highest memory bandwidth of any PLD family. The TriMatrix memory structure, shown in Figure 1, makes the Stratix family an ideal choice for memory-intensive applications. DSP Blocks The programmable DSP blocks in Stratix devices are highperformance embedded arithmetic units that are optimized for applications such as rake receivers, voice over Internet Altera Corporation Figure 1. TriMatrix Memory Structure More Bits for Larger Memory Buffering More Data Ports for Greater Memory Bandwidth M512 Blocks M4K Blocks M-RAM Blocks ■ 512 bits per block ■ 4 Kbits per block ■ 512 Kbits per block ■ Up to 1,118 blocks ■ Up to 520 blocks ■ Up to 12 blocks ■ IP packet buffering Applications ■ Rake receiver correlator ■ ATM cell packet processing ■ Shift register ■ ■ System cache Small FIFO buffers ■ Header/cell storage ■ ■ Video frame buffers Finite impulse response (FIR) filter delay line ■ Channelized functions ■ Echo canceller data storage ■ Program memory for processors ■ Processor code storage 3 protocol (VoIP) gateways, orthogonal frequency division multiplexing (OFDM) transceivers, image processing applications, and multimedia entertainment systems. Flexible, efficient, and valuable for a variety of applications that require high data throughput, these DSP blocks can implement a variety of typical DSP functions, such as finite impulse response (FIR) filters, fast Fourier transform (FFT) functions, correlators, and encryption/decryption functions, and are ideal for the wireless communication, telecommunication, video, and image processing markets. Figure 2. DSP Block Architecture Optional Input Registers Optional Pipeline Registers Optional Output Registers The DSP blocks eliminate performance bottlenecks in complex arithmetic applications, provide predictable and reliable performance, and save resources without compromising performance. This makes DSP blocks ideal for implementing computationally complex systems while providing high data throughput at the same time. Stratix DSP blocks consist of hardware multipliers, adders, subtractors, accumulators, and pipeline registers. DSP blocks in Stratix devices can run at 300 MHz to provide data throughput performance of up to 2.4 GMACS per DSP block. With up to 28 DSP blocks, Stratix devices can provide a combined throughput that is more than 10 times the data throughput available from leading digital signal processors today. Summation Unit Table 3. DSP Block Features Programmable Element Because the Stratix DSP blocks are implemented with dedicated circuitry as shown in Figure 2, they can offer designers optimal performance. Table 3 highlights the features of Stratix DSP blocks. Multiplier High-Bandwidth I/O Standards & HighSpeed Interfaces Adder/Subtractor/ Accumulator Stratix devices support a variety of single-ended and differential I/O standards to interface easily with backplanes, host processors, buses, memory devices, and 3D graphics controllers. Stratix devices offer designers an aggregate device bandwidth of up to 600 Gbps and access to up to 116 high-speed differential I/O channels. Each of these I/O channels includes dedicated serializer/deserializer (SERDES) circuitry for high-speed interface standards as shown in Table 4. This support for high-speed I/O interfaces and high-bandwidth protocols makes Stratix devices an ideal solution for complete system integration. Differential I/O Standard Support Stratix devices offer the True-LVDS™ circuitry to support the LVDS, LVPECL, PCML, and HyperTransport differential I/O standards as well as differential HSTL and SSTL. The Stratix device family has up to 116 high-speed input and 4 Adder/Subtractor/ Accumulator Multiplier Benefit ■ 9x9, 18x18, and 36x36 multiplication ■ Floating-point arithmetic ■ Signed and unsigned operation ■ Full precision in all modes ■ Optional shift register chain on inputs ■ Dynamic switching between adder and subtractor ■ 9-bit, 18-bit, or 36-bit operation for adder and subtractor ■ 52-bit accumulator ■ Signed and unsigned operation Summation Unit ■ Summation of up to four products in one clock cycle Complex Shift Function ■ Barrel shifter, cross-bar switch, and encryption 116 output differential I/O channels with up to 80 channels optimized for 840-Mbps operation. Single-Ended I/O Standard Support To interface with other devices on a board, Stratix devices support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, GTL, GTL+, PCI-X, AGP, and CTT. Devices using single-ended I/O standards provide more current drive capacity than differential I/O standards, and Altera Corporation Table 4. Stratix I/O Standard & Interface Support Feature Single-Ended I/O Standards Differential I/O Standards External Memory Interfaces Electrical Standards LVTTL, LVCMOS, SSTL, HSTL, PCI-X, CTT, AGP, GTL+ LVDS, LVPECL, HyperTransport, PCML SSTL-2, SSTL-3, SSTL-18, HSTL Class I & II, Differential SSTL, Differential HSTL Dedicated Circuitry ■ True-LVDS circuitry Dedicated DDR circuitry ■ Related Altera® Intellectual Property (IP) Cores & Reference Designs Terminator technology on-chip termination PCI compliant ■ Dedicated SERDES circuitry ■ Dedicated DQS circuit ■ Differential I/O buffers ■ DDR timing circuit ■ Data realignment ■ Dedicated I/O registers ■ PCI-X ■ POS-PHY Level 4 ■ DDR SDRAM controller ■ 32-/64-Bit PCI ■ UTOPIA Level 4 ■ ■ CSIX ■ Flexbus Level 4 Single data rate (SDR) SDRAM controller ■ Direct memory access (DMA) controller ■ HyperTransport ■ DDR FCRAM controller ■ RapidIO ■ ■ Universal serial bus (USB) controller Quad data rate (QDR) SRAM controller ■ ZBT RAM controller they are necessary when working with advanced memory devices such as double data rate (DDR) SDRAM and zerobus turnaround (ZBT) SRAM devices. Figure 3. Stratix On-Board High-Speed Interface Support To Host Processor XSBI, SFI-4, UTOPIA IV High-Speed Interface Support Altera continues its industry-leading high-speed differential I/O interface support with Stratix devices. Stratix devices support a wide array of high-speed interface standards, including the 10-Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport, RapidIO, and UTOPIA IV standards. Designers can use Altera intellectual property (IP) cores to bridge between high-speed interfaces through the Atlantic™ local interface. In addition, Stratix devices can support up to four high-bandwidth interfaces in one device for an unparalleled bridging solution, as shown in Figure 3. High-Speed External Memory Interface Support In addition to the on-chip TriMatrix memory, Stratix devices address increasing memory bandwidth requirements by providing customers with additional off-chip data storage that supports external memory interfaces. Designers can easily connect Stratix devices to a wide range of the latest SRAM and DRAM memory devices from leading vendors. Using Stratix device features and customizable IP, designers can integrate high-density memory devices into complex system designs without reducing data access performance or increasing development time. Stratix devices address a wide variety of cutting-edge memory interfaces, as summarized in Table 5. Altera Corporation RapidIO, HyperTransport ASSP ® Network Processing Backplane POS-PHY L4 To Backplane Table 5. Stratix External Memory Interface Support External Memory Device Maximum Data Transfer Rate Memory Clock Speed SDR SDRAM 200 Mbps 200 MHz DDR SDRAM 400 Mbps 200 MHz DDR FCRAM 400 Mbps 200 MHz ZBT SRAM 200 Mbps 200 MHz QDR SRAM 668 Mbps 167 MHz QDRII SRAM 668 Mbps 167 MHz 5 High-Performance Architecture Figure 4. Stratix Clock Management Circuitry Built on an innovative architecture, the Stratix devices allow designers to take advantage of the performance capabilities of dedicated silicon blocks while preserving overall design flexibility. This architecture gives designers the solution they need to reach their designs’ performance and bandwidth targets. Stratix Architectural Advances The Stratix device family is based on a new architecture, built from the ground up, to power complex designs to new levels of system integration. In concert with the LogicLock™ design methodology, Stratix devices simplify the difficult process of design integration, providing the basis upon which block-based designs can be developed and optimized for maximum performance. This new high-performance architecture is based on the MultiTrack interconnect with DirectDrive™ technology. The MultiTrack interconnect consists of continuous, performanceoptimized routing lines of different lengths used for interand intra-design block connectivity. DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function, regardless of its placement within the device. These two new architectural advances simplify the system integration stage of block-based design by eliminating the time-consuming system re-optimization cycles that typically follow design changes and additions. Terminator Technology Terminator technology in Stratix devices is an on-chip termination resistor technology that supports on-chip serial, parallel, and differential termination and driver impedance matching. Driver impedance matching is essential for reducing reflections and improving signal integrity (as shown in Figure 5) for maximum system performance. Figure 5. Terminator Technology Improves Signal Integrity Clock Management Circuitry With up to 12 PLLs and up to 40 system clocks per device, Stratix devices are built to function as the central clock manager to meet your system timing challenges. These devices are the first PLDs to offer the on-chip PLL features for system-level clocking management previously found only in high-end discrete PLL devices. Stratix devices offer two types of PLLs: enhanced PLLs that support advanced features such as external feedback, clock switchover, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth, and fast PLLs that are optimized for high-speed differential I/O interfaces and can be used for general-purpose clocking. Figure 4 illustrates the features of Stratix PLLs. 6 Signal Reflection Improved Signal Integrity Without Termination With Terminator Technology Terminator on-chip termination also reduces board space usage and simplifies board layout by minimizing the number of external resistors required on the PCB when compared to other termination techniques, as Figure 6 illustrates. To provide constant calibration of the internal resistor values, Terminator technology utilizes two external precision resistors per I/O bank and monitors the value of these resistors. The termination resistors can then compensate for process, temperature, and voltage variations. Altera Corporation Figure 6. Terminator Technology Simplifies Board Layout Many External Termination Resistors Only Two Reference Resistors Needed per I/O Bank Logic Device ® External Termination Terminator Technology Remote System Upgrades Increased competition and shrinking windows of opportunity require your product to be the best in the market. While using PLDs gets your designs to market faster, using the remote system upgrade capability in Stratix devices can keep your products on technology’s cutting edge. Remote system upgrades can be transmitted through any communi-cations network to keep your SOPC designs ahead of the competition. Stratix devices provide both enhanced design flexibility and an extended life cycle, as shown in Figure 7. Altera SOPC Solutions Altera offers a set of solutions for creating complete systems on Stratix devices, including the Quartus II design software, optimized IP, the Nios embedded processor, and customer training. Quartus II Design Software Simplifies Design The Quartus II design software provides the most comprehensive environment available for SOPC design. This is because the Quartus II software contains a suite of programmable logic design and verification tools, an integrated embedded software development environment, and integration to third-party EDA software. The Quartus II software allows designers to implement advanced device features to integrate IP megafunctions easily. Table 6 shows the highlights of the Quartus II design software version 2.1 Table 6. Quartus II Design Software Version 2.1 Highlights Feature Uses block-based design and optimization capabilities to shorten design and verification cycles and enable team-based design. PowerFit™ Placeand-Route Improves productivity by intelligently optimizing designs based on user’s timing specifications and delivering the fastest compile times in the industry. Timing Closure Flow Includes timing closure floorplan editor to display physical timing estimates between nodes in real time, ability to make powerful path-based assignments on critical paths to remove performance bottlenecks easily, netlist optimization features, and incremental, block-based placement. SignalProbe™ InSystem Verification Allows incremental routing of internal nodes to unused or reserved pins for analysis with an external scope or logic analyzer. SignalTap® II Embedded Logic Analyzer Enables designers to capture internal signal values in-system and running at system speeds without external probes and without changing user design files. NativeLink® Integration Seamless integration of Quartus II software with third-party EDA synthesis and verification software. SOPC Builder Integration Integrates SOPC Builder automated system definition and integration tool. Figure 7. Remote System Upgrade Benefits Revenue Get to Market Faster Stay in Market Longer Remote-Upgrade-Enabled System PLD-Based System Expanded Life Cycle ASIC-Based System Time Altera Corporation Benefit LogicLock Design Methodology 7 Intellectual Property Altera and Altera Megafunction Partners Program (AMPPSM) partners offer over 60 off-the-shelf IP megafunctions optimized for Altera Stratix devices. Designers can easily implement these parameterized blocks of IP, reducing design and test time. Megafunctions provide total solutions by targeting specific application areas, providing optimized performance and system reusability, and significantly reducing a product’s time-to-market. Nios Embedded Processor Solutions The Nios embedded processors solutions allow designers to integrate embedded processors for complete SOPC designs on Stratix devices. The Nios soft core embedded processor has been optimized for the advanced architectural features of the Stratix device family to deliver increased performance and capabilities. With the Altera SOPC Builder, designers select from the wide array of IP components, customize them for the particular application, and connect them— automatically generating hardware, software and simulation models for the custom implementation. Stratix devices and the Nios embedded processor solutions simplify the design process and accelerate time-to-market. Customer Training For customers interesting in learning more about designing quickly and efficiently with Stratix devices, Altera has launched a unique instructor-led modular training series. This Stratix device-specific series consists of individual training modules that can be arranged to create custom courses tailored to customer needs and based on their existing experience. Altera also offers three one-day courses that cover all modules. Contact Altera Today The Stratix device family provides the ideal solution for your high-bandwidth, high-performance design needs. Visit the Altera web site today to learn more about the Stratix device family and its high bandwidth solutions at www.altera.com/stratix. ® The Programmable Solutions Company ® Altera Offices Altera Corporation 101 Innovation Drive San Jose, CA 95134 Tel: (408) 544-7000 www.altera.com Altera U.K., Ltd. Holmers Farm Way High Wycombe, Buckinghamshire HP12 4XF United Kingdom Tel: (44) 1 494 602 000 Altera Japan, Ltd. Shinjuku i-Land Tower 32F 6-5-1, Nishi-Shinjuku Shinjuku-ku, Tokyo 163-1332 Japan Tel: (81) 3 3340 9480 www.altera.co.jp Altera International, Ltd. 2102 Tower 6 The Gateway, Harbour City 9 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2945-7000 Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. HyperTransport and RapidIO are trademarks of their respective owners and may be registered in certain jurisdictions. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. GB-STRATIX-2.0