®
Mercury
The Programmable ASSP
May 2001
Mercury: The
Programmable ASSP
Figure 1. Mercury Architecture
Altera introduces a new level
of system integration with the
Enhanced PLL
- 12 PLL Clocks
- ClockLock Circuitry
- ClockBoost Circuitry
- ClockShift Circuitry
Mercury™ device family.
Mercury devices seamlessly integrate a high-speed
clock data recovery (CDR)-enabled transceiver with
a performance-optimized programmable logic core
CDR at
1.25 Gbps
- LVDS
- LVPECL
- PCML
Architecture Built
for Bandwidth
- High Core Performance
- Optimized for Speed
- Distributed Multiplier
Capability
that is built for bandwidth. Mercury devices
are ideal for applications that require
rapid data transfer rates.
Mercury CDR provides speeds of up to 1.25 gigabits
Advanced I/O Support
- DDR SDRAM - SSTL-3/-2
- ZBT SRAM - HSTL
- PCI-X
- AGP
- GTL+
- LVTTL
per second (Gbps) per channel and total CDR
bandwidth of 45 Gbps to power the high-speed
backplane, chip-to-chip, and line-side connections
of communications applications. Figure 1 shows the
Quad-Port ESB
- Quad-Port RAM
- CAM
- High-Speed FIFOs
innovative Mercury architecture, and Table 1
describes some of the highlights of the Mercury
devices. Members of the Mercury family are shown
standards encounter clock skew problems at frequencies
in Table 2. Mercury devices offer designers an
nearing 1 Gbps. CDR eliminates these barriers today and
unparalleled solution for their high-performance
enables future programmable logic devices (PLDs) with
communications needs.
speeds of 2.5 Gbps, 3.125 Gbps, and 10 Gbps.
Breaking the Gigabit Barrier
CDR functionality is essential for next-generation high-
CDR is a key element in developing today’s leading-edge
communications systems, which often require serial data
transmission at speeds in excess of 1 Gbps. Single-ended
I/O standards typically reach noise limitations at frequencies of about 250 MHz, while traditional differential I/O
speed connections that use standard protocols such as
Gigabit Ethernet and SONET/SDH. Mercury CDR is
compliant with these protocols and many others. Mercury
devices also feature up to 18 channels of CDR that can
function on the LVDS, LVPECL, and PCML differential
Table 1. Mercury Highlights
FEATURE
BENEFIT
CDR circuitry
Data rates of up to 1.25 Gbps with LVDS, LVPECL, and PCML support
Advanced I/O standard support
Supports PCI, PCI-X, HSTL, GTL+, SSTL-2/-3, AGP, CTT, and LVTTL standards
External memory interface
Built-in support for external zero-bus turnaround (ZBT), double-data rate (DDR), and
quad-data rate (QDR) SRAMs
Flexible-LVDS™ support
LVDS support on regular I/O pins providing over 100 channels of support
Enhanced phase-locked loops (PLLs)
Provides up to 12 PLL clocks with support for ClockLock™, ClockBoost™, and ClockShift™ features
Quad-port embedded system blocks
(ESBs)
Supports quad-port RAM, dual-port RAM, ROM, content-addressable memory (CAM), and
first-in first-out (FIFO) buffers
Prioritized interconnect structure
Reduces routing delays for speed critical signals to increase performance
Distributed multiplier circuitry
Provides over 130-MHz, 16x16 non-pipelined, push-button performance
FlipChip technology
Increased I/O performance and I/O count, in space-saving FineLine BGA™ packages
Advanced 0.15-µm, 1.8-V
copper process
Improved performance over traditional aluminum process technologies
Altera Corporation
Table 2. Mercury Devices
DEVICE
GATES
EP1M120
120,000
EP1M350
350,000
I/O PINS 2
SUPPLY
VOLTAGE
484-Pin BGA1
303
1.8 V
8
4,800
49,152
780-Pin BGA1
486
1.8 V
18
14,400
114,688
PIN/PACKAGE OPTIONS 2
CDR
CHANNELS
LOGIC
ELEMENTS
RAM BITS
Notes: 1 Space-saving FineLine BGA package.
2 Preliminary. Contact Altera for latest information.
standards, making them well-suited for applications such
as the ones described in Table 3 and shown in Figure 2.
The integration of a high-performance programmable core
allows designers to combine their designs with CDR into a
single Mercury device, saving valuable board space and
speeding time-to-market. Figure 3 illustrates the
High-Bandwidth I/O Capabilities
Mercury devices provide advanced support for a wide
variety of I/O transfer protocols, satisfying the everincreasing demand for PLDs with next-generation I/O
support. In addition to the CDR function, Mercury devices
provide a source-synchronous mode with the True-LVDS™
combination of CDR-enabled transceivers with state-ofthe-art programmable logic in Mercury devices.
feature that supports the LVDS, LVPECL, and PCML
standards using built-in, dedicated high-speed differential
interface (HSDI) circuitry. This mode is complimented by
Table 3. Mercury Applications
the Mercury Flexible-LVDS feature, which incorporates
BANDWIDTH
(Mbps)
CHANNELS
SONET Standards
9,953
8
POS-PHY Level 4
9,953
8
RapidIO
8,000
16
Gigabit Ethernet
1,250
Any
IEEE 1394
1,200
Any
Fibre Channel
1,062
Any
High-Definition
Television
742.5
Any
Proprietary
Backplanes
Any
Any
APPLICATION
dedicated LVDS buffers on every I/O pin for an additional
100 channels of 624-Mbps LVDS support to give Mercury
devices true high-bandwidth capabilities.
Figure 3. CDR Integration in PLD
CDR Transceiver ASSP
CDR
Encoding/
Decoding
Additional
Logic
Mercury
CDR
Figure 2. Mercury Backplane Application
Deserializer/
Serializer
Deserializer/
Serializer
Dedicated Circuitry
Encoding/
Decoding
Additional
Logic
Programmable Logic
Dedicated circuitry for interfacing to advanced highspeed external memories such as DDR SDRAM at up to
332 Mbps, ZBT SRAM at up to 200 MHz, and QDR SRAM
at up to 664 Mbps ensures that Mercury devices meet the
memory demands of cutting-edge applications. Mercury
devices also feature enhanced PLLs to simplify the
difficult task of managing system clocks in highperformance systems. The combination of these features
with industry-leading FlipChip packaging and array-driver
technology makes the Mercury family the leader in I/O
performance and next-generation standards support.
Altera Corporation
Architecture Built for Bandwidth
The performance-targeted Mercury architecture is designed
to process data at gigabit rates and simultaneously manage
high CDR-generated bandwidth. Mercury’s interconnect
structure intelligently prioritizes signal routing to provide
the fastest possible routing times for speed-critical signals
and to maximize core performance.
Continuing Altera’s commitment to the DSP and wireless
markets, Mercury devices also offer distributed multiplier
capability. With this capability, designers can implement
16x16 non-pipelined multipliers with over 130-MHz
performance or up to 90 separate 8x8 multipliers in
a single device.
Altera offers a wide selection of intellectual property (IP)
cores specifically optimized for the Mercury architecture.
One example is the Mercury Gigabit Transceiver
MegaCore® function, with an 8B/10B encoder/decoder
that allows designers to seamlessly integrate CDR-required
functions and proprietary logic, providing a complete
programmable solution.
Contact Altera Today
Mercury devices are the ultimate transceiver solution for
your communications needs. Featuring CDR functionality
at up to 1.25 Gbps, support for a wide array of highspeed I/O standards, and a performance-optimized core
that is built for bandwidth, Mercury devices give
The Mercury architecture delivers additional flexibility
designers a complete single-chip gigabit solution. Call
for the memory requirements of high-performance appli-
Altera today to learn more about the Mercury device
cations through an ESB structure that supports quad-port
family, or visit the Altera web site at
RAM, dual-port RAM, single-port RAM, and FIFO buffers
http://www.altera.com for more information.
and CAM functions.
Reducing Time-to-Market:
Development Tools & IP Cores
Mercury devices are supported by the Altera Quartus® II
development software. From synthesis and syntax
checking through behavioral simulations and
configuration, the Quartus II software offers an intuitive
user interface and provides a smooth development path
for complex designs to increase productivity and shorten
time-to-market. Altera also offers the Excalibur™ solutions
to help reduce design cycle time. The Nios™ processor,
an Excalibur solution, allow designers to embed a highperformance processor in a Mercury device in just a
few hours.
Altera Offices
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Telephone: (408) 544-7000
http://www.altera.com
Altera U.K., Ltd.
Holmers Farm Way
High Wycombe
Buckinghamshire
HP12 4XF
United Kingdom
Telephone: (44) 1 494 602 000
Altera Japan, Ltd.
Shinjuku i-Land Tower 32F
5-1, Nishi-Shinjuku, 6 Chome
Shinjuku-ku, Tokyo 163-1332
Japan
Telephone: (81) 3 3340 9480
http://www.altera.com/japan
Altera International, Ltd.
2102 Tower 6
The Gateway, Harbour City
9 Canton Road,
Tsimshatsui, Kowloon
Hong Kong
Telephone: (852) 2945-7000
Copyright © 2001 Altera Corporation. Altera, ClockBoost, ClockLock, ClockShift, Excalibur, FineLine BGA, Flexible-LVDS, MegaCore, Mercury, Nios, Quartus, Quartus II, True-LVDS,
and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Other brands or products are trademarks of their
respective holders. The specifications contained herein are subject to change without notice. All rights reserved.
M-GB-MERCURY-01