Excalibur Web Server
Demonstration
December 2002, ver. 1.0
Introduction
Application Note 285
This document describes the Excalibur™ web server demonstration design
and includes the following topics:
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Design Overview
Installation
Run the Design
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Design
Overview
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AN-285-1.0
The design assumes that you have a basic level of knowledge of
web servers.
For important late-breaking information on this design, you must read the
readme.txt file in the project root directory.
The web server demonstration design is a simple web server running on
top of the Nios Ethernet Development Kit (NEDK) plugs library. The
design runs on the EPXA10 development board and serves web pages,
which are stored in flash memory on the board. The design highlights the
features of the Excalibur EPXA10 embedded stripe and the ability to
incorporate soft intellectual property into the FPGA array. Figure 1 shows
the design block diagram.
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AN 285: Excalibur Web Server Demonstration
Figure 1. Block Diagram
SDRAM
EPXA10 Development Board
SDRAM
Controller
RS-232
UART
EPXA10 Device
10/100
Ethernet MAC
Flash
10/100 PHY
Device
PC
RJ-45
The design serves both static and dynamic web pages. The web server
runs on top of the plugs library, which handles the transmission control
protocol/internet protocol (TCP/IP). On top of the plugs library the web
server embedded software parses incoming HTTP requests and responds
with the requested web page. Web pages are stored in flash using the way
over simplified file system (WOSFS). After an HTTP request is received,
the requested page is retrieved from WOSFS and sent back to the host PC
as an HTTP response. The web server assumes that all HTTP requests are
GET requests.
The design code runs out of on-chip SRAM. TCP/IP packets are
transmitted and received by the Ethernet MAC MegaCore funciton over
the on-board PHY device and RJ-45 connector. The design connects the
Ethernet MAC to bus logic in the FPGA. The Ethernet MAC AHB master
port buffers TCP/IP packets in the SDRAM via the PLD-to-stripe bridge.
The processor configures the Ethernet MAC via its AHB slave port over
the stripe-to-PLD bridge. Status information is sent out of the UART to the
PC via the RS232 port. In addition, flash programming occurs over the
ByteBlasterMV™ download cable, which is connected to the EPXA10
development board JTAG header.
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AN 285: Excalibur Web Server Demonstration
Installation
This sections details the hardware and software requirements and the
design directory structure.
Hardware & Software Requirements
The web server demonstration design requires the following hardware
and software:
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EPXA10 development board
Quartus® II software version 2.2
ARM Developer Suite for Altera (Altera ADS-Lite) software
version 1.1
Altera 10/100 Ethernet MAC MegaCore® function version 1.2.0
OpenCore® Plus evaluation license
Terminal Program, e.g., Minicom or Hyperterminal
Directory Structure
To install the web server demonstration design, unzip an285.zip into the
installation directory of your choice.
Figure 2 shows the directory structure.
Figure 2. Directory Structure
webserver
software
Contains the embedded software source for the design; this includes the source for the
plugs library.
inc
Contains project header files.
lib
Contains the plugs library and other functions used in the design.
web
Contains the web pages.
altera_ahb_ext_irq_wire
Contains a simple SOPC Builder component that is needed to handle the multiple interrupts
for the Ethernet MAC.
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AN 285: Excalibur Web Server Demonstration
Run the Design
Running the web server demonstration design involves the following
steps:
1.
Compile the FPGA Hardware.
2.
Compile the Embedded Software.
3.
Configure the EPXA10 Development Board.
4.
Setup the Host PC.
Compile the FPGA Hardware
The project root directory includes the default hardware image for the
web server demonstration design, webserver.sbi. If you have no changes
to the hardware design, you need not recompile, so proceed to “Compile
the Embedded Software” on page 4.
If you need to change the hardware design, use the SOPC Builder for
design entry.
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For more information on how to use the SOPC Builder to build systems,
refer to www.altera.com/literature/lit-sop.html.
If you perform a hardware recompilation, you must obtain an OpenCore
Plus license to re-synthesize and place-and-route the Ethernet MAC.
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For an OpenCore Plus license, refer to
www.altera.com/support/licensing/ip/lic-ipm-ocp.jsp.
Compile the Embedded Software
The design has the following default TCP/IP settings:
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Development board IP address: 137.57.193.114
Development board subnet mask: 255.255.255.0
Gateway address: 137.57.193.254
DNS address: 137.57.109.1
If the default settings remain unchanged, or if you are connecting to the
board directly with a crossover cable, proceed to “Configure the EPXA10
Development Board” on page 5.
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AN 285: Excalibur Web Server Demonstration
If the default TCP/IP settings are not acceptable for your network,
perform an embedded software build. To build the embedded software,
perform the following steps.
1.
Run the Quartus II software and open the webserver.quartus
project.
2.
Change the IP address for the EPXA10 development board to the
desired settings by modifying the following lines in the
\software\web.c file:
settings.nameserver_ip_address = nm_ip2n(137,57,109,1);
settings.subnet_mask = nm_ip2n(255,255,255,0);
settings.gateway_ip_address = nm_ip2n(137,57,193,254);
settings.ip_address = nm_ip2n(137,57,193,114);
3.
To build the design file, choose Start Software Build (Processing
menu).
Configure the EPXA10 Development Board
You must configure the EPXA10 Development board to work with this
design. To setup the jumpers and connect the development board to the
host PC and network, perform the following steps:
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AN 285: Excalibur Web Server Demonstration
1.
To configure the EPXA10 development board to boot from flash and
enable the 78Q2120 Ethernet PHY device MII clocks to the EPXA10
device, adjust the jumper settings. Table 1 shows the jumper settings.
Table 1. Jumper Settings
Jumper
JP1
On
JP2
Connect 2 to 3
JP3
Connect 2 to 3
JP4
Connect 2 to 3
JP5
Connect 2 to 3
JP6
Connect 2 to 3
JP14
Off
JP15
Off
JP16
Off
JP17
Off
JP18
Off
MSEL0
Connect 1 to 2
MSEL1
Connect 1 to 2
JP31
Off
JP32
Off
JP33
Off
JSELECT
Connect 1 to 2
DEBUG_EN
Connect 2 to 3
BOOT_FLASH
Connect 2 to 3
EN_SELECT
Off
JP40
Connect 2 to 3
JP41
Connect 2 to 3
U179
Connect 2 to 3
JP50
Connect 2 to 3
JP51
Connect 2 to 3
JP52
Connect 2 to 3
JP53
Connect 2 to 3
JP54
Connect 2 to 3
JP55
Connect 2 to 3
JP57
Off
JP58
3V3
JP59
JP_AGND2GND
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Setting
3V3
Connect 1 to 2
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AN 285: Excalibur Web Server Demonstration
2.
Connect a straight-through Ethernet cable from the EPXA10 board to
a network hub. Alternatively, you can use a crossover Ethernet cable
to connect the EPXA10 board directly to your host PC.
3.
Connect a ByteblasterMV™ cable from your PC’s parallel port to the
MasterBlaster™ header on the EPXA10 development board.
4.
Connect null modem cable to the RS-232 P2 port (the one in the
upper left hand corner) on the EPXA10 development board.
Setup the Host PC
The Web Server Demo Design must communicate with a host PC, for flash
programming, to display debug information, and serve web pages. To
setup the host PC, perform the following steps:
1.
Start a terminal session with the following settings:
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38400 Baud
8 Data bits
No Parity
1 stop bit
No Flow control
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2.
In this design, the UART presents status information.
To download the combined PLD and software image,
webserver_flash.hex, to the EPXA10 development board flash, use
the prog_hw.bat file.
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If you have not performed JTAG programming on the host
PC before, start the JTAG server by typing the following
command at a command prompt:
jtagconfig -add byteblastermv lpt1r
3.
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Launch a web browser and enter the board IP address in the URL
field. For example http://137.57.193.114
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AN 285: Excalibur Web Server Demonstration
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
lit_req@altera.com
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