Timing Closure
with the Quartus II Software
July 2002, ver. 1.0
Introduction
Application Note 198
With FPGA designs surpassing the multimillion-gate mark, designers
need new tools that better address timing closure issues and meet system
performance.
The Altera® Quartus® II software offers a fully integrated timing closure
flow that allows more control over how a design is synthesized and
placed-and-routed. New tools are also available to help analyze and
efficiently make assignments to designs. This application note explains
the timing closure flow and the features that help achieve timing closure
with the Quartus II software version 2.1.
This application note is intended for designers who have a basic
understanding of the Quartus II software and the LogicLock™ design
methodology. The following topics will be covered:
■
■
■
■
Timing Closure
Flow
Timing Closure Flow
Netlist Optimization
Design Analysis Using the Timing Closure Floorplan
Timing Closure Assignments
A traditional flow for designs using FPGA tools is to enter constraints,
synthesize your design, and then place-and-route it. The Quartus II
software introduces features that allow you to more effectively close
timing, including netlist optimization, a new timing closure floorplan,
and more powerful user assignments. The Quartus II timing closure flow
also offers more control over the synthesis and place-and-route fitting
steps. Also, fitter information can be used for more efficient synthesis.
Figure 1 shows the Quartus II timing closure flow diagram.
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AN-198-1.0
It is important to understand the design and apply appropriate
assignments such that performance is increased. It is possible to
decrease performance if assignments are applied without full
understanding of the design.
The timing closure flow can be applied to an overall design or to modules
of a design that can be integrated later. For more information on a blockbased design approach, refer to AN 161: Using the LogicLock Methodology in
the Quartus II Design Software.
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AN 198: Timing Closure with the Quartus II Software
Figure 1. Timing Closure Flow Diagram
Compile
Design
Performance
Met?
Yes
Success!
No
Netlist
Optimization
Performance
Met?
Yes
Success!
No
No
Analysis Using
Timing Closure
Floorplan
Make
Assignments
and Compile
No
Performance
Met?
2
Yes
Success!
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AN 198: Timing Closure with the Quartus II Software
Netlist
Optimization
The Quartus II software includes netlist optimization options to further
optimize your design after synthesis and before place-and-route. These
options can be applied regardless of the synthesis tool used. Depending
on your design, some options may have more of an effect than others.
Netlist optimization options can be applied in multiple combinations to
provide optimal results.
Netlist Optimization Options
The three netlist optimization options currently offered are:
■
■
■
WYSIWYG primitive resynthesis
Gate-level register retiming
Logic element duplication.
WYSIWYG Primitive Resynthesis
The WYSIWYG primitive resynthesis option un-maps the logic elements
(LEs) in an atom netlist to gates and then re-maps the gates back to Alteraspecific primitives. This feature allows the Quartus II software to use
different techniques specific to a device architecture during the remapping process. Figure 2 shows the Quartus II software steps for this
option.
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An atom netlist is file that specifies the design as Altera-specific
primitives and is most often generated by a third-party tool. An
example of an atom netlist file is an EDIF Input File (.edf) or a
Verilog Quartus Mapped (.vqm) file.
Figure 2. WYSIWYG Primitive Resynthesis
Un-Map
ATOM
Netlist
Re-Map
Place
&
Route
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The WYSIWYG primitive resynthesis option can be used with the
Stratix™ or the APEX™ device families. This option is not applicable if
native Quartus II synthesis is used. With Quartus II synthesis, you do not
need to un-map Altera primitives; they are already mapped during the
synthesis step using the techniques that are used with the WYSIWYG
primitive resynthesis option.
The WYSIWYG primitive resynthesis option will only un-map and remap logic cell (also referred to as LCELL or LE) primitives. Memory
primitives, DSP primitives, and logic cells that are in carry chains will not
be touched.
Any nodes or entities that have the “Disabled Advanced Netlist
Optimizations” option turned on will not be affected during WYSIWYG
primitive resynthesis. This option can be applied through Assignment
Organizer > Options for Individual Nodes & Entities (Tools menu).
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When the WYSIWYG primitive resynthesis option is turned on,
the node names for primitives in the design can change.
Primitive node names are specified during synthesis and are in
the atom netlist. When this option is applied, node names may
change as primitives are removed and created. This must be
considered if you are using a LogicLock or verification flow that
requires fixed node names.
Any compiler-specific directives that are used in third-party synthesis
tools will be ignored if the WYSIWYG primitive resynthesis option is
turned on. An example of a compiler-specific directive is not to remove
redundant logic.
To turn on the WYSIWYG primitive resynthesis option, choose Compiler
Settings (Processing Menu) and click the Netlist Optimization tab. Under
Synthesis optimizations, turn on the “Perform WYSIWYG primitive
resynthesis” check box. See Figure 3.
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AN 198: Timing Closure with the Quartus II Software
Figure 3. Perform WYWIWYG Primitive Resynthesis Option
Gate-Level Register Retiming
The gate-level register retiming option enables movement of registers
across combinational logic to balance timing, allowing the Quartus II
software to trade-off the delay between critical paths and non-critical
paths. The functionality of your design will not change. If any registers in
your design have the “Power-Up Don’t Care“ logic option assigned, the
values of registers during power-up may change. Registers that are
explicitly assigned power-up values will not be combined with registers
that have been explicitly assigned other values.
Figure 4 shows an example of gate-level register retiming.
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Figure 4. Gate-Level Register Retiming Diagram
D
Q
10 ns
D
Q
5 ns
D
Q
D
Q
7 ns
D
Q
8 ns
D
Q
Register retiming makes changes at the gate level. If you are using an atom
netlist from a third-party tool, you must also use the WYSIWYG primitive
resynthesis option to un-map primitives to gates (so that register retiming
can be performed) and then to re-map gates to Altera primitives. If your
design uses native synthesis, retiming will occur during synthesis before
the mapping to Altera primitives. The design flows for the case of native
Quartus II synthesis and a third-party atom netlist are shown in Figure 5.
Figure 5. Flows for Gate-Level Register Retiming
Native Quartus II Synthesis
Gate
Synthesis
Retiming
Technology
Map
Place & Route
Remap
Place & Route
Third-Pary ATOM Netlist
Unmap
Retiming
The gate-level register retiming options will only move registers across
combinational gates. Registers will not be moved across LCELL
primitives instantiated by the user, memory blocks, DSP blocks, or
carry/cascade chains that you have instantiated. Carry/cascade chains
are always left intact when using register retiming.
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AN 198: Timing Closure with the Quartus II Software
One of the benefits of register retiming is the ability to move registers from
the inputs of a combinational logic block to the output, potentially
combining the registers. In this case, some registers are removed, and one
is created at the output. This case is shown in Figure 6.
Figure 6. Combining Registers with Register Retiming
Registers can only be moved and combined in cases like this if the
following conditions are met:
■
■
■
■
All registers have the same clock domain
All registers have the same clock enable
All registers have asynchronous control signals that are active under
the same conditions
Only one register has an asynchronous load other than VCC or GND
It is always possible to create multiple registers at the input of a
combinational block from a register at the output of a combinational
block. In this case, the new registers will have the same clock and clock
enable. The asynchronous control signals and power-up level will be
derived from previous registers to provide equivalent functionality.
The synthesis section of the Compilation Report provides a list of registers
that were removed and created during register retiming. See Figure 7.
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Figure 7. Synthesis Section of Compilation Report
You can apply the “Disabled Advanced Netlist Optimizations” option to
registers such that they are never moved during register retiming. This
option can be applied either to individual registers or entities in the design
and is applied through the Assignment Organizer (Tools menu).
The following registers will never be moved during register retiming:
■
■
■
■
■
■
■
Registers that have any timing constraint other than global fMAX, tSU
or tCO
Registers that feed asynchronous control signals on another register
Registers feeding the clock of another register
Registers feeding a register in another clock domain
Registers that are fed by a register in another clock domain
Registers connected to serializer/deserializer (SERDES)
Registers that have the “Disabled Advanced Netlist Optimizations”
option turned on
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When the gate-level register retiming option is turned on, the
node names for primitives in the design can change. Primitive
node names are specified during synthesis and are in the atom
netlist. When this option is applied, node names may change as
primitives are removed and created. This must be considered if
you are using a LogicLock or verification flow that requires fixed
node names.
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AN 198: Timing Closure with the Quartus II Software
To turn on the gate-level register retiming option, choose Compiler
Settings (Processing menu) and click the Netlist Optimization tab. Under
Synthesis optimizations, turn on “Perform gate-level register retiming.”
Figure 8. Perform Gate-Level Register Retiming Option
Allow Register Retiming to Trade-Off Tsu/Tco with Fmax Option
The “Allow register retiming to trade off Tsu/Tco with Fmax” option in
the Compiler Settings dialog box (Processing menu) determines whether
it is possible to increase fMAX at the expense of tSU or tCO times. This
option will affect the gate-level register retiming option.
When both the “Perform gate-level register retiming” and the “Allow
register retiming to trade off Tsu/Tco with Fmax” options are turned on,
retiming could affect registers that feed and are fed by I/O pins. If it is not
turned on, the retiming option will not touch any registers that directly
connect to I/O pins.
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Logic Element Duplication
The logic element duplication option allows LEs to be duplicated based on
fitter placement information. An LE that fans out to multiple locations can
be duplicated to reduce the delay of one path without degrading the delay
of another. After place-and-route, the delay and placement information is
used to determine whether or not logic element duplication may decrease
the delays of critical paths. Figure 9 shows an example of logic element
duplication.
Figure 9. Logic Element Duplication
Only combinational logic, in the form of look-up tables (LUTs), will be
duplicated with this option; registers will not be duplicated. If the LE is
packed, the LUT portion of the LE can be duplicated.
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Packed LEs consist of an LUT that does not feed the register in
the LE. Allowing register packing can significantly reduce the
area of your design.
Logic element duplication will not be performed on LEs that:
■
■
■
Are part of a carry/cascade chain
Are considered virtual I/O pins (For more information on virtual I/O
pins, refer to AN 161: Using the LogicLock Methodology in the Quartus II
Design Software.)
Have the “Disabled Advanced Netlist Optimizations” option turned
on
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When the logic element duplication option is turned on, the node
names for primitives in the design can change. Primitive node
names are specified during synthesis and are in the atom netlist.
When this option is applied, node names may change as
primitives are removed and created. This must be considered if
you are using a LogicLock or verification flow that requires fixed
node names.
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AN 198: Timing Closure with the Quartus II Software
To turn on the logic element duplication option, choose Compiler
Settings (Processing menu) and select the Netlist Optimization tab.
Under Fitter optimizations, turn on “Automatically duplicate logic
elements” (see Figure 10).
Figure 10. Logic Element Duplication Option
Applying Netlist Optimization Options
To obtain optimal results when using netlist optimization options, try
varying the options applied to find the best results. If the combination of
options that provide the best results still does not meet performance, the
configurations below you can use as a starting point for design analysis.
By default, all options are off.
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If you are using a third-party tool, try the following combinations:
■
■
■
■
■
No netlist optimization options turned on
“Perform WYSIWYG primitive resynthesis” option turned on
Both the “Perform WYSIWYG primitive resynthesis” option and the
“Perform gate-level register retiming” option turned on
“Automatically duplicate logic elements” option turned on
All three netlist optimization options turned on
If you are using native Quartus II synthesis, try the following
combinations:
■
■
■
■
No netlist optimization options turned on
“Perform gate-level register retiming” option turned on
“Automatically duplicate logic elements” option turned on
Both the “Perform WYSIWYG primitive resynthesis” option and the
“Perform gate-level register retiming” option turned on
Netlist optimization options can have various effects on your designs;
designs that are very well coded or have already been restructured to
balance critical paths may not see a noticeable difference in performance.
If you are using any Quartus II netlist optimization options, you can
generate a Quartus II Verilog Quartus Mapped file (.vqm) to preserve the
changes that were made to your original netlist. This step is necessary to
preserve node names if you wish to back-annotate your design in the
future. For more information on back-annotating, refer to “Timing
Closure Assignments” on page 24.
Design
Analysis Using
the Timing
Closure
Floorplan
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The Quartus II software has introduced a timing closure floorplan to help
you better analyze designs. This new floorplan, used in conjunction with
traditional Quartus II timing analysis features, provides a powerful
method to perform design analysis.
Floorplan Views
The new timing closure floorplan allows you to customize how to view
your design. The Field View shows color-coded resources and allows for
an uncluttered look and feel. Figure 11 shows a Stratix device with the
new Field View.
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AN 198: Timing Closure with the Quartus II Software
Figure 11. Field View of a Stratix Device
M4K
Blocks
DSP
Blocks
M512
Blocks
M-RAM
I/O Blocks
You can also view your design in the timing closure floorplan with the
traditional Interior Cells, Package Top, and Package Bottom views. Use
the View menu to change the floorplan view.
When in the field view, you can view the details of a resource by selecting
the resource, right-clicking, then pressing Show Details. To hide the
details, select all the resources, right click, and press Hide Details. (See
Figure 12.)
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Figure 12. Show Details & Hide Details of an LAB in Field View
Viewing Assignments
With the timing closure floorplan, you can view both user assignments
and fitter placements at the same time. User assignments refer to all
location and LogicLock assignments. To see user assignments, click the
user assignments icon from the floorplan toolbar or choose Assignments
(View menu) and select Show User Assignments. (See Figure 13.)
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AN 198: Timing Closure with the Quartus II Software
Figure 13. User Assignments
Fitter placements refer to where the Quartus II software placed all nodes
after the last compilation. To see fitter placements, click the fitter
assignments icon from the floorplan toolbar or choose Assignments
(View menu) and select Show Fitter Placements. (See Figure 14.)
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Figure 14. Fitter Placements
Viewing Critical Paths
The Viewing Critical Path feature displays paths in the floorplan by
criticality as found in Figure 15. You can also view a percentage of critical
paths or specify how many paths you wish to see. You can also choose to
see paths for all clock domains or a specific clock domain. The paths that
can be displayed are:
■
■
■
■
16
Pin-to-pin (tPD)
Pin-to-register (tSU)
Register-to-pin (tCO)
Register-to-register (fMAX)
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AN 198: Timing Closure with the Quartus II Software
Figure 15. Critical Paths
To view critical paths in the floorplan, select the icon or go to Routing >
Critical Path Settings (View menu). To set the criteria for the critical paths
you wish to view, click the view critical paths icon or choose Routing >
Critical Path Settings (View menu). Figure 16 shows the Critical Paths
Settings window.
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Figure 16. Critical Paths Settings Window
The critical paths feature is extremely useful in determining the criticality
of nodes based on node placement. There are a number of options to view
the details of critical paths. To see the delay of the critical paths, select the
critical paths icon or choose Routing > Show Routing Delays (View
menu).
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Figure 17. Routing Delays for Critical Paths
The default view shows the register-to-register path. You can also view all
the combinational nodes for the worst-case path between the source and
destination nodes. To view the full path, select the path by clicking on the
delay label, right click, and select Show Path Edges. Figure 18 shows a
critical path through combinational nodes. To hide the combinational
nodes, select the path, right click, and select Hide Path Edges.
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The routing delays must be shown in order to be able to select a
path.
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Figure 18. Worst-Case Combinational Path of Critical Path
You can also assign the path to a LogicLock region through the Path
window. Just select the path, right click, and select Properties.
After using the critical path feature at least once, it is possible to determine
the maximum routing delay between two nodes within a LogicLock
region. Place your mouse over a fitter-placed LogicLock region to see the
maximum delay. Figures 19 shows the maximum routing delay of a
LogicLock region.
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Figure 19. Maximum Intra-Region Delay
For more information on making path assignments through the Path
window, refer to “Path-Based Assignments” on page 29.
Physical Timing Estimates
In the timing closure floorplan, you can select a resource and see an
approximate delay to any other resource on the chip. Once a resource is
selected, the delay is visually represented by the color of potential
destination resources. The darker the resource, the longer the delay, as
shown in Figure 20.
Figure 20. Physical Timing Estimates for Large Floorplan
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An approximate delay in nanoseconds can also be determined by
selecting a source and then holding your mouse over a potential
destination resource, as shown in Figure 21.
Figure 21. Delay for Physical Timing Estimate
The delays represented are an estimate based on probable best-case
routing. It is possible for the delay to be greater than what is shown,
depending on the availability of routing resources. In general, there is a
strong correlation between the probable and actual delay.
LogicLock Region Connectivity
You can also see how logic in LogicLock regions interface by viewing the
connectivity between assigned LogicLock regions. This capability is
extremely valuable when entities are assigned to LogicLock regions. It is
also possible to see the fan-in and fan-out of selected LogicLock Regions.
Figure 22 shows standard LogicLock region connections. To view the
connections in the timing closure floorplan, select the LogicLock region
icon from the toolbar or go to Routing > Show LogicLock Connectivity
(View menu).
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Figure 22. LogicLock Region Connections with Connection Count
The connection line thickness indicates how many connections exist
between regions. To view the number of connections between regions,
select the connections icon or go to Routing > Show Connection Count
(View menu).
LogicLock region connectivity is applicable only when the User
Assignments are viewed in the floorplan. When floating LogicLock
regions are used, the origin of the user-assigned region is not necessarily
the same as the fitter-placed region. This is so that you can unlock a region
and then lock it down again at a later time. The origin of your floating
LogicLock regions can be changed to that of the last compilation origin
through the Region Write-back option, which can be set by choosing
Back-Annotate Assignments (Processing menu) and selecting Region
Write-back.
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To see the fan-in or fan-out of a LogicLock region, select the user-assigned
LogicLock region while the fan-in and/or the fan-out option is turned on.
To set the fan-in option, select the fan-in icon or go to Routing > Show
Node Fan-In (View menu). To set the fan-out option, select the fan-out
icon or go to Routing > Show Node Fan-Out (View menu). Only the
nodes that have user assignments will be seen when viewing fan-in or fanout of LogicLock regions. Figure 23 shows the fan-out of a selected
LogicLock region.
Figure 23. Fan-In or Fan-Out
Timing Closure
Assignments
To achieve timing closure once a design has been analyzed, there are a
number of assignments that can be made and a number of methods by
which to make those assignments. This section covers the LogicLock and
location assignments as a means to set the placement of nodes. You can
choose to make assignments to nodes, modules, or paths in the design.
Quartus II Assignments
With the Quartus II software, you can choose to make LogicLock region
assignments, soft LogicLock region assignments, or location assignments.
All of these assignments are described below.
LogicLock Regions
LogicLock regions are contiguous, rectangular blocks of device resources
to which logic you can assign. LogicLock assignments can be made to
nodes, paths, or entities of a design. Anything assigned to a LogicLock
region will be contained within the region’s boundaries.
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f
For information on LogicLock regions and the LogicLock Design
Methodology, refer to AN 161: Using the LogicLock Methodology in the
Quartus II Design Software.
Soft LogicLock Regions
Soft LogicLock regions are defined the same way as LogicLock regions,
but the nodes or entities assigned to soft LogicLock regions do not
necessarily have to stay within the boundaries of the region. The
Quartus II software will place nodes outside of the region if it is likely that
placing it within the region will create a failing critical path. Soft
LogicLock assignments can be made to nodes, paths or entities of a design.
f
For information on soft LogicLock regions, refer to AN 161: Using the
LogicLock Methodology in the Quartus II Design Software.
Location Assignments
Location assignments are hard assignments that must be obeyed by the
software. They are made to nodes or entities and determine which specific
resources they are assigned to. Nodes and entities can be assigned to logic
elements, memory blocks, DSP blocks and pins.
Location assignments can be made through the Assignment Organizer or
the timing closure floorplan. When using the Assignment Organizer, you
can select the nodes through the Node Finder and then assign them to
resources that are specified under Locations. Figure 24 shows the
Assignment Organizer window.
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Figure 24. Assignment Organizer
When using the timing closure floorplan, nodes can be dragged from their
fitter-placed location to a resource for a location assignment. All location
assignments can be seen as long as the User Assignments View is turned
on.
Applying Timing Closure Assignments
In previous versions of the Quartus II software, you could choose to either
make assignments to nodes or entities. The Quartus II software version 2.1
provides a methodology to make path-based assignments.
Node Assignments
Node assignments can be made through the Assignment Organizer, the
timing closure floorplan, or by back-annotating your design.
When using the Assignment Organizer, nodes can be selected using the
Node Finder, as shown in Figure 25. Nodes selected through the
Assignment Organizer can be assigned to LogicLock regions, soft
LogicLock regions, or locations.
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Figure 25. Node Finder
You can make wildcard assignments ( “*” and “?”) using the Assignment
Organizer. The Quartus II software specifies the assignment in the
constraint file (.csf) as a wildcard instead of writing out assignments for
each node.
Nodes can also be selected in the timing closure floorplan. To make
assignments, you can either right click on one of the highlighted nodes
and select Assignment Organizer, or drag the nodes to a LogicLock
region or resource to make a location assignment.
A common way to make location assignments to all nodes is to backannotate your design. This effectively locks down the placement of each
node to the resource it was placed in during your last compilation.
Entity Assignments
Entities can be assigned through the Assignment Organizer, the timing
closure floorplan, or by dragging and dropping in from the Hierarchies
window. Entities are most often assigned to LogicLock regions but can be
assigned directly to resources using location assignments.
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When using the Assignment Organizer, you can specify the entity in the
“Edit specific entity & node settings for” box, or you can select your entity
in the Hierarchies window, right click, and select Assignment Organizer.
After selecting your entity, it can be assigned to a LogicLock region or a
resource through a location assignment.
You can also make assignments by dragging and dropping using the
Hierarchies window. To make a location assignment to a resource (i.e., a
memory block), select the entity in the Hierarchies window and drag to
the specific resource in the timing closure floorplan.
LogicLock assignments can be made to entities by dragging an entity from
the Hierarchies window to one of the LogicLock regions in the LogicLock
Regions Window. If a LogicLock region does not exist, the entity can be
dragged to the “<<new>>” line for a new LogicLock region. This will
create a LogicLock region with the instance name of the entity and assign
the entity to it.
Figure 26. Drag-Drop from Hierarchies Window to LogicLock Region
You can also create a new LogicLock Region for an entity by right clicking
on the entity and selecting Create New LogicLock Region.
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Path-Based Assignments
Path assignments can only be made to LogicLock regions, and only
through the following methods:
■
■
■
Using the new Path window
By dragging and dropping paths from the Timing Analysis section of
the Compilation Report
By dragging and dropping using the critical paths utility in the timing
closure floorplan
The new path assignments that can be made will assign every node in
every path from the source and destination nodes. For a situation as
shown in Figure 27, assume that the path Source > N1 > N2 > N4 >
Destination is the worst-case path. If a path assignment is made from node
Source to node Destination, nodes Source, Destination, N1, N2, N4 and N3
will be assigned to a LogicLock region.
Figure 27. Worst-Case vs. All Paths
f
If you prefer to assign only a worst-case path to a region, you can do so by
making assignments to the individual nodes. For information on how to
make assignments to nodes, refer to “Node Assignments” on page 26.
Path Window
The Path window allows you to specify a path by identifying a source and
destination node. You can use wildcard assignments to specify source and
destination nodes. See Figure 28.
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Figure 28. Path Window with List Nodes & Wildcard
You have the option of excluding the source nodes, the destination nodes,
and any nodes that match a name or a wildcard. It is also possible to
change the LogicLock region to which the path will be assigned.
Before making an assignment, you can select List Node to determine how
many nodes will be assigned to the LogicLock region. A list of nodes will
be provided along with a node count.
The Path window can be accessed through the LogicLock Region
Properties window (shown in Figure 29) by clicking “Add Path…” The
LogicLock Region Properties window can be opened for a LogicLock
region by right-clicking on the region in the LogicLock Regions Window
and selecting Properties.
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Figure 29. LogicLock Regions Properties Window
The Path window can also be accessed when using the Critical Path utility
by selecting the critical path, right-clicking, and pressing Properties (see
Figure 30).
Figure 30. Right Click on Critical Path
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Dragging and Dropping
Paths can be selected from the Timing Analysis reports and assigned to
LogicLock regions. To do this, open the Compilation Report and select
one of the reports under the Timing Analysis section. Select which paths
you would like to assign and drag them from the timing analysis report to
an existing LogicLock region or to the “<<new>>” line to create a region.
(See Figure 31.)
Figure 31. Compilation Report & LogicLock Region Window with Arrow
Critical paths displayed using the Critical Path utility can also be assigned
to LogicLock regions. To create a region, select the critical paths you
would like to assign and drag them from the timing closure floorplan to
an existing LogicLock region or to the “<<new>>” line. See Figure 32.
Figure 32. Timing Closure Floorplan & LogicLock Region Window with Arrow
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Altera Corporation
AN 198: Timing Closure with the Quartus II Software
Conclusion
Today’s multi-million-gate FPGA designs have complex timing needs.
Methodologies for timing closure are a fundamental requirement for
optimal performance in highly complex designs. Altera is the first
programmable logic supplier to develop and deliver a timing closure
methodology as an integrated part of its existing tools suite at no
additional cost.
Using the Quartus II timing closure methodology closes timing quickly on
complex designs, reduces iterations by providing more intelligent and
better linkage between analysis and assignment tools, and balances
multiple design constraints including multiple clocks, routing resources,
and area constraints.
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33
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