®
Using Flexible-LVDS
I/O Pins in
APEX II Devices
August 2002, ver. 1.1
Introduction
Application Note 167
Recent expansion in the telecommunications market and growth in
Internet use have created a demand to move more data faster than ever.
To meet this demand, system designers are relying on solutions such as
differential signaling and interface standards such as RapidIO,
POS-PHY Level 4, and UTOPIA IV.
APEXTM II device high-speed interface I/O pins offer serialization and
deserialization on a single chip to move data at high speeds. They also
utilize a state-of-the-art CMOS process that consumes far less power than
GaAs devices, the other alternative for high-speed devices.
Preliminary
Information
The following documents provide information on APEX II device highspeed I/O standard features and functions. These documents also explain
how system designers can take advantage of these standards to increase
system efficiencies and bandwidth.
„
„
Flexible-LVDS
Differential
Buffers
Application Note 157 (Using CDS in APEX II Devices) describes the
most common clock topologies, and how the unique clock-data
synchronization (CDS) feature in APEX II devices is applied.
Application Note 166 (Using High-Speed I/O Standards in APEX II
Devices) provides information on APEX II device high-speed I/O
standard features and functions. This document also explains how
system designers can take advantage of these standards to increase
system efficiencies and bandwidth.
The APEX II high-speed interface offers four high-speed I/O banks. Each
I/O bank is comprised of 18 channels, offering 36 differential input
channels and 36 differential output channels. Every channel can transmit
data at speeds of up to 1 gigabit per second (Gbps).
APEX II devices also offer 88 Flexible-LVDSTM pins that use internal
phase-locked loops (PLLs) to transmit or receive data at 400 Megabits per
second (Mbps). Flexible-LVDS pins are located in standard user I/O
banks and only require a 100-Ω termination resistor at the input receiver
pins. Flexible-LVDS pins support LVDS, LVPECL, and HyperTransport
signaling on the receiver side and LVDS and HyperTransport signaling on
the transmitter side. Because Flexible-LVDS I/O pins implement
serialization/deserialization (SERDES) with minimal logic in APEX II
devices, they do not require dedicated circuitry.
Altera Corporation
AN-167-1.1
1
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Flexible-LVDS
I/O Interface
Preliminary Information
Designers can use dedicated double data rate (DDR) circuitry to
implement Flexible-LVDS I/O pins in APEX II devices. While single data
rate (SDR) circuitry only samples data at the positive edge of the clock,
DDR circuitry captures data on both the rising and falling edges, and is
therefore capable of doubling the maximum SDR transfer rate.
Designers can use APEX II device shift registers, internal global PLLs, and
I/O cells to perform serial-to-parallel conversions on incoming data and
parallel-to-serial conversions on outgoing data.
Clock Domains
Flexible-LVDS I/O pins use the many clock domains available in APEX II
devices. These clock domains fall into four categories: eight global clock
domains, two I/O element (IOE) clock domains from the peripheral
control bus, four fast I/O clock domains, and unlimited, internally
generated clock domains.
The four general-purpose PLLs generate the eight global clock domains.
Each PLL features two taps that directly drive two unique global clock
networks. A dedicated clock pin drives each of the four general-purpose
PLLs. These eight clock lines are utilized when designing for speeds up to
400 Mbps. Figure 1 shows the PLL connections to the dedicated global
clock lines. For more information on general purpose PLLs, see Application
Note 156 (Using General-Purpose PLLs with APEX II Devices).
2
Altera Corporation
Preliminary Information
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Figure 1. APEX II PLL Clock Connections & Dedicated Global Clock Lines
G6
G8
G2
G4
G3
G1
G7
G5
Transmitter PLL1
VCO
Receiver PLL1
J
RXCLK_IN1P
RXCLK_IN1N
VCO
W
W
TXCLK_OUT1P
TXCLK_OUT1N
PLL4
CLK4
PLL3
INCLK
CLK0
CLK0
CLK1
CLK1
CLK0
CLK0
CLK1
CLK1
PLL2
CLK2
INCLK
CLK3
PLL1
INCLK
INCLK
CLKLK_FBIN2
CLKLK_OUT2
CLK1
CLKLK_FBIN1
CLKLK_OUT1
Transmitter PLL2
VCO
W
Receiver PLL2
J
RXCLK_IN2P
RXCLK_IN2N
VCO
W
TXCLK_OUT2P
TXCLK_OUT2N
Each APEX II device IOE selects clock, clear, clock enable, and output
enable controls from the peripheral control bus, a network of I/O control
signals. The peripheral control bus uses high-speed drivers to minimize
signal skew across devices. In addition to the eight global clock signals,
two of the twelve APEX II peripheral control bus signals can feed the IOE
register’s clock ports. Each one of the two clocks can be driven by any of
the dedicated input pins or from any logic element (LE). Figure 2 shows
the IOE configuration for DDR input. Figure 3 shows the IOE
configuration for DDR output.
Altera Corporation
3
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Preliminary Information
Figure 2. APEX II IOE in DDR Input I/O Configuration
Column, Row
or Local
Interconnect
VCCIO
Eight
Dedicated
Clocks
Optional
PCI Clamp
12 Peripheral
Signals
VCCIO
Programmable
Pull-Up
Resistor
Input Pin to Input
Register Delay
Input Register
D
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Input Clock
Enable Delay
Chip-Wide Reset
Input Register
D
Q
ENA
CLRN/PRN
4
Latch
D
Q
ENA
CLRN/PRN
Altera Corporation
Preliminary Information
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Figure 3. APEX II IOE in DDR Output I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
OE Register
D
Output Clock
Enable Delay
Q
Output
tZX Delay
VCCIO
Optional
PCI Clamp
ENA
CLRN/PRN
OE Register
tCO Delay
Chip-Wide Reset
VCCIO
Programmable
Pull-Up
Resistor
OE Register
D
Q
ENA
CLRN/PRN
Logic Array
to Output
Register Delay
Output Register
D
Output Register
D
Output
Propagation
Delay
Q
ENA
CLRN/PRN
Logic Array
to Output
Register Delay
Used for
DDR SDRAM
clk
Drive Strength Control
Open-Drain Output
Slew Control
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
The four dedicated fast I/O pins can also function as clocks. These fast
I/O pins have a lower maximum speed than the global clocks. A fast I/O
pin drives the IOE clock through the peripheral control bus.
Altera Corporation
5
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Preliminary Information
Flexible-LVDS I/O Receiver Operation
The Flexible-LVDS I/O receiver uses the APEX II device’s DDR input
circuitry to receive high-speed serial data. The DDR input circuitry
consists of a pair of registers used to capture the high-speed serial data
and a latch. One register captures the data on the positive edge of the highfrequency clock (generated by PLL) and the other register captures the
data on negative edge of the high-frequency clock. The data captured on
the negative edge is delayed by one half of the high-speed clock cycle.
Therefore, the data is latched before it interfaces with the system logic.
Figure 4 shows the DDR timing relation between the incoming serial data,
and the high-frequency clock. The inclock signal is running at half the
speed of the incoming data. Figure 5 shows the DDR input and the other
modules used in a Flexible-LVDS receiver design to interface with the
system logic.
Figure 4. DDR Timing Relationship between the Incoming Serial Data & Clock
inclock
datain
B0
neg_edge_out XX
6
A0
B1
B0
A1
B2
B1
A2
B3
B2
A3
B3
dataout_l
XX
B0
B1
B2
dataout_h
XX
A0
A1
A2
Altera Corporation
Preliminary Information
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Figure 5. Flexible-LVDS Receiver Interface (×8 Mode)
DDR Circuit
datain
Shift
Register
DFF
D0, D2, D4, D6
Register
D1, D3, D5, D7
APEX II
Logic
Array
Latch
DFF
Shift
Register
inclock
PLL
Clock
×4
×1
Flexible-LVDS I/O Transmitter Operation
The Flexible-LVDS I/O transmitter uses the APEX II device’s DDR output
circuitry to transmit high-speed serial data. The DDR output circuitry
consists of a pair of registers and a multiplexer. The transmitter has a pair
of shift registers that capture and transfer data to the DDR output
circuitry.
Figure 6 shows the DDR timing relation between the parallel data and the
low-frequency clock. The inclock signal is running at half the speed of
the data. Figure 7 shows the DDR output and the other modules used in a
Flexible-LVDS transmitter design to interface with the system logic.
Figure 6. DDR Timing Relation between Parallel Data & Clock
inclock
dataout_l
B0
B1
B2
B3
dataout_h
A0
A1
A2
A3
dataout
Altera Corporation
XX
A0
B0
A1
B1
A2
B2
A3
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AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Preliminary Information
Figure 7. Flexible-LVDS I/O Transmitter Interface (×8 Mode)
DDR Output Circuit
DFF
D0, D2,
D4, D6
APEX II
Logic
Array
Shift
Register
dataout
DFF
D1, D3,
D5, D7
Shift
Register
×1
PLL
Quartus II
Software
×4
×1
inclock
Designing with Flexible-LVDS I/O buffers requires the use of the ddio
megafunction in the Quartus II software. Other functions such as serial
shift registers and PLLs are also implemented to receive or transmit data
at high speeds.
The following section discusses an example design that consists of both a
VHDL receiver circuit and a transmitter circuit for I/O buffers. The design
used in this section is also available on the Altera web site
(http://www.altera.com). Although this example is for data transfers
where the data rate is 8× the clock rate, the data transfer can be easily
modified for other data/clock relationships.
Building an 8-Bit Flexible-LVDS Receiver
The DDR input register receives the data and separates it into odd bits and
the even bits. The incoming data bits 0, 2, 4, and 6 are connected to the
input of one shift register, and the data bits 1, 3, 5, and 7 are connected to
the input of the other shift register. These two shift registers de-serialize
the data. A third register, clocked by the low-frequency clock, drives the
parallel data to the system design.
Figure 8 shows all the modules necessary for a single Flexible-LVDS
buffer to receive serial data.
8
Altera Corporation
Preliminary Information
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Figure 8. Complete Receiver Module
pll1 (1)
inclk
pll_clk_en
inclock
clock0
clk0
inclocken
locked
locked
×4
dataL[2]
flex_lvds_input (2)
clk0
clk_en
datain[0]
inclock
dataout_h[0]
h[0]
dataout_l[0]
l[0]
inclocken
inst1
clock
clk_en
enable
shiftin
dataL[1]
dataL[0]
lpm_shiftregA
left shift
clk0
dataH[1]
dataH[0]
ddio input
h[0]
dataL[3]
dataH[2]
inst
serial_input
dataH[3]
q[3..0]
clk0
datah[3..0]
clk_en
l[0]
inst2
data[7]
inst11
inst15
inst12
inst16
inst13
inst17
inst14
data[6]
data[5]
data[4]
data[3]
data[2]
data[1]
data[0]
inst18
dataout7
dataout6
dataout5
dataout4
dataout3
dataout2
dataout1
dataout0
lpm_shiftregA
left shift
clock
enable
q[3..0]
datal[3..0]
shiftin
inst3
Notes to Figure 8:
(1)
(2)
Input period = 25 ns; clock0 frequency multiplication factor = 4.
Power up low.
The altddio_in block captures the serial data on both clock edges and
parses the data into two outputs. The bits captured on the negative edges
are latched before they are driven to the shift register modules. This
synchronizes the bits with the data captured on the rising edge of the
clock.
The general-purpose PLL module (PLL1) generates the high-speed clock
for the deserialization registers. The inclk signal is multiplied by a factor
of four, generating the clock signal required by the shift registers for
deserializing the data. The multiplication factor may be changed for
different data-to-clock relationships.
The clk0 PLL output clocks a pair of shift registers, which converts data
from serial to parallel. The incoming data bits 0, 2, 4, and 6 are connected
to the input of one shift register, and the data bits 1, 3, 5, and 7 are
connected to the input of the other shift register. The shift registers
deserialize the data, which then is driven to the system design.
Eight wires reconstruct the data bits and make the connection between the
Flexible-LVDS circuitry and the system design.
Altera Corporation
9
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Preliminary Information
Building an 8-Bit Flexible-LVDS Transmitter
The data is received on two shift registers. Outgoing data bits 0, 2, 4, and 6
are connected to the input of one shift register and data bits 1, 3, 5, and 7
are connected to the input of the other shift register.
The DDR output module uses a high-speed clock generated by the
general-purpose PLL module to transmit the serial data. A counter signals
the shift register to receive data every fourth clock cycle.
Figure 9 shows all the modules necessary for a single Flexible-LVDS
buffer to transmit serial data.
Figure 9. Complete Transmitter Module
flex_lvds_out (1)
hout
datain_h[0]
lout
datain_l[0]
clk0
clk_en
serial_out
dataout[0]
outclock
outclocken
clk_en
ddio output
eq[3]
resulth[3..0]
clk0
clk_en
Serializer
left shift
load
data[3..0]
shiftout
clock
result[7]
in7
inst
inst19
result[5]
in5
inst20
result[3]
in3
hout
inst21
result[1]
in1
inst22
result[6]
in6
enable
inst1
inst23
result[4]
in4
inst24
lpm_counter
result[2]
in2
clk0
clock
eq[]
eq[15..0]
inst25
result[0]
in0
inst26
resulth[3]
resulth[2]
resulth[1]
resulth[0]
resultl[3]
resultl[2]
resultl[1]
resultl[0]
inst2
eq[3]
resultl[3..0]
clk0
clk_en
Serializer
left shift
pll1 (2)
inclk
load
data[3..0]
clock
enable
inst3
pll_clk_en
shiftout
inclock
clock0
clk0
inclocken
locked
output
lout
×4
inst4
Notes to Figure 9:
(1)
(2)
10
Power up low.
Input period = 25 ns; clock0 frequency multiplication factor = 4.
Altera Corporation
Preliminary Information
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
A pair of shift registers is clocked by clk0 (PLL output) and serialize the
data. Data bits 0, 2, 4, and 6 are connected to the input of one shift register,
and data bits 1, 3, 5, and 7 are connected to the input of the other shift
register.
The general-purpose PLL module generates the high-speed clock. The
inclk signal is multiplied by a factor of four, generating the clock signal
the shift registers require to serialize the data. A counter signals the shift
register to receive data on every fourth clock cycle.
The altddio_out megafunction block captures data on clock rising
edges and parses the data to a single output. For both receiver and
transmitter, the ×1 clock should be used to transmit or receive data to or
from the system logic.
Flexible-LVDS
I/O Pin
Locations
Altera Corporation
APEX II Flexible-LVDS I/O pins are located at the edge of the package to
reduce the possible mismatch between a pair of high-speed signals.
Figure 10 shows the I/O blocks and their location relative to the package.
Flexible-LVDS I/O pins are located on top and bottom of the device.
11
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
Preliminary Information
Figure 10. True-LVDS & Flexible-LVDS I/O Pins
Regular I/O Pins & Flexible-LVDS
Input Pins (LVDS, HyperTransport,
LVPECL Inputs) (1)
True-LVDS
Transmitter Pin Area
(LVDS, LVPECL,
PCML, HyperTransport
Outputs) (1)
True-LVDS
Receiver Pin Area
(LVDS, LVPECL,
PCML, HyperTransport
Inputs) (1)
Regular I/O Pins & Flexible-LVDS
Output Pins (LVDS, HyperTransport
Outputs) (1)
Note to Figure 10:
(1)
The shaded ovals show the approximate locations of the True-LVDSTM or Flexible-LVDS pins.
Summary
12
Flexible-LVDS I/O pins are dual-purpose user I/O pins that provide
additional differential channel support in APEX II devices. The FlexibleLVDS solution supports up to 88 transceiver channels at a 400-Mbps data
rate. It also supports applications that need more than 36 LVDS channels.
External resistors are only needed for receivers, not on the transmitters.
The function is easily implemented by instantiating Altera’s library of
parameterized modules (LPM) functions and the supplied reference
design.
Altera Corporation
Preliminary Information
Revision
History
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
The information contained in AN 167: Using Flexible-LVDS I/O Pins in
APEX II Devices version 1.1 supersedes information published in previous
versions.
Version 1.1
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices version 1.1
contains the following changes:
„
„
Altera Corporation
Changed the value from 624 to 400 Mbps throughout the document.
Updated notes of Figures 8 and 9 to read 25 ns instead of 16 ns.
13
AN 167: Using Flexible-LVDS I/O Pins in APEX II Devices
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