Excalibur Solutions—Using
the Expansion Bus Interface
October 2002, ver. 1.0
Introduction
Application Note 143
In the Excalibur™ family of devices, an ARM922T™ processor, memory
and peripherals are embedded on an FPGA. For designers, this
combination of elements provides an easy and flexible way of integrating
highly-complex embedded microprocessor designs into a cost-effective
and faster time-to-market system-on-a-programmable-chip (SOPC)
solution.
In addition to the benefits of easy design development, Excalibur devices
offer the flexibility of configuration through the expansion bus interface
(EBI). The EBI in the Excalibur embedded stripe provides a connection
between external peripherals and the system bus. A flash memory
connected to the EBI can be used to boot and configure the Excalibur
device. In addition, the EBI can also be used to connect slower memorymapped peripherals to the ARM922T processor.
EBI
Characteristics
The EBI is a 16-bit bidirectional interface connecting external memorymapped peripherals to the AHB2 bus on the embedded stripe. The AHB2
slave interface runs synchronously to the AHB2 bus, supporting all
transaction types, as defined in the ARM® document AMBA Specification,
Revision 2.0, and works at a range of frequencies.
The EBI manages data packing and unpacking automatically, based on
endianness, block configuration, and the size of the transaction selected
by the master. It also supports rate adaptation for slow external devices.
Four blocks of up to 32 Mbytes of external memory or memory-mapped
devices can be connected to the EBI. The base address and size of each
block is set in the memory map registers. In boot-from-flash mode, EBI
width and voltage standard are selectable by configuration at power-up.
The EBI is a slave-only interface, with a fixed programmable access period
selectable on a block-by-block basis. A clock can be output for
synchronous operation, if required, with a programmable divide from the
AHB2 clock frequency.
Split responses can be issued to AHB transactions that otherwise tie up the
bus for a long period, e.g., a long burst read from a slow 8-bit external
device.
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A-AN-143-1.0
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The EBI can be configured to operate in various ways, as follows:
■
■
■
Synchronous connection, with variable wait states
8- or 16-bit bus width—optionally using byte enables
Active-high or active-low chip-select polarity
Width and Voltage Operation
The EBI can be set up for 8-bit or 16-bit operation, i.e., devices on the EBI
can be 8 bits or 16 bits wide, using a 2.5-V, 3.3-V or 1.8-V input supply.
Flash memory devices are typically slower than other types of memory, so
EBI outputs are usually driven at a slow slew rate by default. However,
using the Quartus® II MegaWizard® Plug-In, designers can optionally
choose a fast slew rate or open drain output.
EBI Functions
This section describes the internal operation of the EBI and the basic
functions of all the signals on the EBI, as shown in Figure 1.
Figure 1. EBI Internal Block Diagram
Interrupt
Timer
Timeout
Start/
Stop
Data (HWDATA)
32
72
Address (HADDR) 32
Transaction
FIFO
72
AHB Slave
Interface
Control (HSIZE ... )
Data (HRDATA) 32
Control
Read
Return
FIFO
32
EBI Transaction
Sequencer
16
EBI_A
25
EBI_CS
4
EBI_WE_n
32
Read Data
32
Write Data
32
EBI_DQ
EBI_OE_n
EBI_BE
EBI_ACK
Control
and Status
Registers
AHB2 Interface
2
Control
EBI_CLK
EBI Interface
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AN 143: Using the Expansion Bus Interface
Table 1 lists the EBI interface signals:
Table 1. EBI Interface Signals
Signal
Description
EBI_DQ [15:0]
16-bit bidirectional data bus, which carries data between the
EBI and the connected peripheral
EBI_A [24:0]
Unidirectional bus that can be connected to four blocks of 32
Mbytes each
EBI_CS [3:0]
Chip-select signal for each of the four blocks on the EBI.
Individual chip selects correspond to memory map blocks
EBI0, EBI1, EBI2, and EBI3. The default polarity of this
signal is active-low
EBI_WE_n
Write-enable signal to the peripheral.
EBI_OE_n
Read-enable signal to the peripheral
EBI_BE
Optional byte enables, provided to allow byte writes/reads to
a 16-bit bus
EBI_ACK
Asynchronous acknowledgement input to the EBI from the
peripheral to make EBI aware of its ready status. The
conventional use of this signal is currently not supported;
however, an alternative way of using asynchronous memory
is described later in this application note.
EBI_CLK
Clock output from the EBI
EBI Internal Operation
As shown in Figure 1 on page 2, the EBI consists of two interfaces, the
AHB2 interface and the EBI interface, which communicate by means of the
transaction FIFO buffer and the read-return FIFO buffer. The AHB2
interface receives transactions from masters on the AHB2 bus, which it
posts to the transaction FIFO buffer. The EBI interface decodes the
transactions and drives the appropriate signals from the memory interface
based on the settings in the control registers. For read transactions, the EBI
interface posts read data to the read-return FIFO buffer.
f
Altera Corporation
For more information on the EBI FIFO buffers, refer to the Excalibur
Devices Hardware Reference Manual.
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AHB2 Interface
The AHB2 interface consists of the AHB slave interface and control and
status registers, as shown in Figure 1 on page 2.
AHB Slave Interface
The AHB slave interface decodes bus transactions from the AHB2 bus
masters and provides a response based on the settings for the EBI block
that has been targeted for the transaction. The EBI block settings are
maintained in the control registers, which are set up depending on the
options you set for the EBI in the Quartus II MegaWizard Plug-In. See
“Configuring the EBI Using the Quartus II MegaWizard Plug-In” on page
6 for details.
Control and Status Registers
For control and status register read and write operations, the slave
interface can operate at the full speed of the AHB2 clock, and wait-states
are not required. For writes or reads to an EBI block, the slave interface
posts a transaction to the transaction FIFO, and wait-states the AHB2 bus
according to the settings for the block.
For a non-split read, the slave interface stalls the AHB2 bus until the data
from the read is available.
1
f
4
Stalling the bus for a slow device can inhibit the performance of
the EBI. Split transactions are supported to increase the
utilization of the AHB2 bus while interfacing to slow peripherals
on the EBI.
For more information on split transactions on the EBI, refer to the
Excalibur Devices Hardware Reference Manual.
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AN 143: Using the Expansion Bus Interface
EBI Interface
The EBI interface consists of the timer and the EBI transaction sequencer,
which are used in conjunction for interface flexibility.
Timer
The timer is a binary counter that is used to time asynchronous memory
access. In asynchronous operation, the timer counts the number of
EBI_CLK cycles taken to receive an acknowledgement from an
asynchronous device on the EBI and compares it with the acceptable timeout period, which is programmable via the EBI_CR register. If no
acknowledgement is received before the expiration of the time-out period,
the timer generates an interrupt to prevent the bus locking. The
EBI_INT_ADDRSR register maintains the address and byte access
information of the memory location that caused the time-out. Clearing the
interrupt from EBI_INT_SR restarts the timer.
f
For more details about the acknowledgement signal, EBI_ACK, refer to
the Excalibur device errata.
Transaction Sequencer
The transaction sequencer performs the following functions:
■
■
■
■
■
■
Runs state machines that perform reads and writes to the EBI blocks
Controls all EBI external pins
Generates the EBI clock i.e., the EBI_CLK external pin
Assembles bytes/half words into words for reads
Reformats words into bytes/half words for writes
Handles endianness
The transaction sequencer controls all of the external pins of the EBI by
taking input from the transaction FIFO output and using each entry as an
instruction. The transaction sequencer performs a table lookup of the EBI
block number to obtain key parameters for the sequence of memory
accesses that it needs to make to process the instruction. The EBI block
number identifies timing information, such as the polarity of chip-enables
and the number of wait states for the memory access. The block number
also provides other information, such as whether byte enables are used to
access of the external memory.
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Configuring the
EBI Using the
Quartus II
MegaWizard
Plug-In
This section explains how to use the Quartus II MegaWizard Plug-In to
configure the EBI by setting up the control registers with the memory
block characteristics.
Reserving Pins for the EBI
Figure 2 on page 7 shows how to reserve a bank of pins for the EBI, which
is done automatically if you turn on Do you want to boot from FLASH?
If you do not want to boot from flash memory, you can still reserve pins
for the EBI by turning on EBI (FLASH) under Reserve Pins.
Reserving pins for the EBI gives further options for the Inputs and
Outputs voltage supplies. One selects the output slew rate, which for the
EBI is usually slow; another selects the chip input supply, which is
typically 3.3 V, but can be 1.8 V.
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AN 143: Using the Expansion Bus Interface
Figure 2. MegaWizard Plug-In Manager
EBI Block Settings
Figure 3 shows how to specify the start address and memory size for each
of the blocks in the EBI. When you designate the location of a block, the
wizard displays an additional dialog, which is used to specify its
particular characteristics. Figure 3 demonstrates how the wizard is used
to specify characteristics for EBI block 0.
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Figure 3. EBI Block Settings
In this page of the wizard, you can set the following characteristics for
each EBI block:
■
Prefetch—To increase bridge throughput, the EBI supports read
prefetching. Read pre-fetching occurs in situations where the AHB
master interface cannot determine the exact amount of data in a burst
(i.e., an unspecified length burst is in progress). The AHB master
interface continues to fill the read buffer until it is full, anticipating
that the data will be needed. When a new transaction begins, the data
is no longer valid.
1
8
Prefetching should not be used where reads have side effects,
i.e., where a read can have the effect of resetting bits.
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AN 143: Using the Expansion Bus Interface
■
■
■
■
Byte Enable—Devices on the EBI can be 8- or 16-bits wide.
Transactions on AHB2 can be 8-, 16-, or 32-bits wide. If the size of the
AHB transaction exceeds the EBI device width, the transaction
sequencer makes multiple EBI accesses. If the AHB transaction is
smaller than the EBI, the transaction sequencer masks the data read
or, if appropriate, uses byte enables. Byte enables are also used to
allow byte-writes to a 16-bit bus, although this does not work if the
connected flash devices do not use byte-enables. EBI_BE0 is used for
EBI_DQ [7..0]; EBI_BE1 is used for EBI_DQ [15..8].
Wait Cycles—Wait cycles are sometimes required to meet the
read/write timing requirement of the connected memory device.
Inserting wait cycles prolongs the signals EBI_WE_n and EBI_OE_n
by the specified number of wait cycles, where a wait cycle is an
EBI_CLK cycle count.
CS Polarity—Chip-select polarity depends on the specification of the
memory connected to the EBI. Flash memory devices typically have
an active-low chip select, but this is not always the case.
Data Width—This is the data width of the memory connected to the
EBI. It can be either an 8- or 16-bit flash memory or a memorymapped device.
Figure 3 on page 8 shows how each of four EBI blocks is configured for a
different 32-Mbyte address space. Each block can have different flash
settings. (e.g., EBI0 could be 8-bit wide with an active-low chip select and
wait cycles of 0, whereas EBI2 could be a 16-bit wide peripheral with an
active-high chip select and wait cycles of 9; similarly, EBI1 and EBI3 could
have different individual interface settings).
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EBI Global Settings
The wizard allows you to specify global settings for the EBI, in addition to
individual EBI block settings. Figure 3 on page 8 shows the EBI global
settings, which are fixed for all the four EBI blocks. The settings are
described below:
■
■
■
■
f
Bus Clock Divide—The AHB2 clock is divided by the number
specified in this setting, which must be in the range 1 to 16. The
resultant clock is EBI_CLK, as shown in Figure 1 on page 2.
Timeout—This is used for asynchronous connection to flash
memory. The count specified here counts a specified number of EBI
clocks for a flash memory acknowledge signal. If the acknowledge is
not received during the specified time, the time-out condition
generates an interrupt.
Enable external clock—This outputs EBI_CLK as an external clock
pin. It can be used for synchronous memory connection.
Enable split reads—In conditions where the memory connected to
the EBI is extremely slow or stalls the bus, e.g., when a long burst is
read from a slow 8-bit external device, split reads are beneficial.
For more information about split transactions on the EBI, refer to the
Excalibur Devices Hardware Reference Manual.
Excalibur EBI Port
Figure 4 on page 11 shows a block symbol instance of the EBI instantiated
-in the ARM stripe. You use the wizard to set up the EBI port, as explained
in “Configuring the EBI Using the Quartus II MegaWizard Plug-In” on
page 6.
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AN 143: Using the Expansion Bus Interface
Figure 4. EBI Port on ARM Stripe Symbol
The external interrupt pin, intextpin, is implemented on the same set
of input pins (i.e., the same power bank) as the EBI interface pins.
Consequently, this pin is only enabled if the EBI interface is enabled. It is
a shared pin, level-triggered and active-low, whereas all other interrupt
sources are active-high. intextpin does not affect EBI functioning; it is
an input to the embedded stripe interrupt controller.
1
EBI Timing
Diagrams
To create this stripe instance, the minimum options in the wizard
have been chosen, i.e., the only memory-mapped regions are
EBI0, EBI1, EBI2, EBI3 and the general purpose registers.
Figures 5 and 6, starting on page 12, show the synchronous operation of
the EBI interface. Signals are sampled on the rising edge of the EBI clock.
For a read operation, when the chip has been selected, data is sampled
from memory when EBI_OE_n is low. This occurs at T3 in Figure 5. For
write transactions, as shown in Figure 6 on page 13, when the chip has
been selected, data is written to memory when EBI_WE_n is low.
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Figure 5. EBI Synchronous Read (0 Wait States)
T1
T2
T3
EBI_CLK
EBI_A
EBI_CS
EBI_DQ
EBI_OE_n
EBI_WE_n
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AN 143: Using the Expansion Bus Interface
Figure 6. EBI Synchronous Write (0 Wait States)
T1
T2
T3
EBI_CLK
EBI_A
EBI_CS
EBI_DQ
EBI_WE_n
EBI_OE_n
Connecting
Flash Memory
to the EBI
Altera Corporation
This section outlines how to connect different types of flash memory to the
EBI on Excalibur devices, using an Intel 3-V advanced+ boot block 16-bit
flash memory (TE28F160C3TC80) as an example. Figure 7 on page 14
shows a block-level schematic of how this device is connected to the EBI.
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Figure 7. TE28F160C3TC80 Connections to the EBI
(2)
WP#
(1)
Excalibur Solution
EBI_CS [x]
CE#
EBI_WE_n
WE#
EBI_OE_n
OE#
nReset
RP#
EBI_A[16:1]
EBI_DQ[15:0]
LH28F160BVE
A15-A0
DQ15-DQ0
(1) Only for EBI_CS[1], EBI_CS[2], EBI_CS[3]
(2) If high, lockable blocks are unlocked
Flash Memory Timing Requirements
The features of the TE28F160C3TC80 include:
■
■
■
■
■
■
■
Zero-latency, flexible block locking
128-bit protection register
Simple system implementation for 12-V production programming
with 2.7-V, in-field programming
Ultra low-power operation at 2.7 V
VCCQ input of 1.65 V–2.5 V on all I/Os
Minimum 100,000 block erase cycles
Common flash interface (CFI) data structure for software query of
device specifications and features
The TE28F160C3TC80 read and write timing parameters specified below
are abstracted from the device datasheet. Refer to the Intel 28F160C3T
device datasheet for more specific timings.
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Flash Read Timing Requirements
The EBI must satisfy the timing requirements given in Table 2 when
reading from the TE28F160C3TC80 device.
Table 2. TE28F160C3TC80 Read Timing Parameters
Parameter
Value
Read cycle time
80 ns (min.)
Address to output delay
80 ns (max.)
OE# to output delay
20 ns (max.)
CE# to output delay
80 ns (max.)
1
The EBI meets these timing requirements. Refer to the Excalibur
Devices Hardware Reference Manual for details of EBI timing.
Flash Write Timing Requirements
The EBI must satisfy the following timing requirements given in Table 3
when writing to the TE28F160C3TC80 device:
Table 3. TE28F160C3TC80 Write Timing Parameters
Parameter
WE# (CE#) low pulse width
50 ns (min)
Data setup to WE# (CE#) going high
40 ns (min.)
Address setup to WE# (CE#) going high
50 ns (min.)
WE# (CE#) pulse width high
30 ns (min.)
1
Altera Corporation
Value
The EBI meets these timing requirements. Refer to the Excalibur
Devices Hardware Reference Manual for details of EBI timing.
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How EBI Settings Affect the Operation of the EBI
This section explains why you must specify the number of wait states and
clock cycles on the EBI accurately, using two examples to illustrate why
this is important.
For the first example, Figure 8 on page 16 shows settings specified for
block 0 of the EBI connected to the TE28F160C3TC80. For this example,
assume that the AHB2 clock is running at 50 MHz. Because the bus clock
divide of AHB2 is specified as 1, the frequency of EBI_CLK is also
50 MHz. The number of wait states is specified as 0 and, since the
peripheral is a 16-bit flash memory, the data width selected is 16. The chipselect for this flash memory is active-low.
Figure 8. EBI Settings that do not Meet Timing Requirements
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The simulation waveform in Figure 9 shows the effect of writing a burst
of eight words to the flash memory using these EBI settings.
Figure 9. ModelSim Waveform—Flash Write Timing Not Met
EBI_CLK
Chip-enable
CE#
Write-enable
WE#
Figure 9 gives the timing values shown in Table 4.
Table 4. Simulation Results
Parameter
Value
WE# (CE#) pulse width
20.03 ns
Data setup to WE# (CE#) going high
20.03 ns
Address setup to WE# (CE#) going high
80.23 ns
Address setup to WE# (CE#) going high
60.20 ns
Table 4 shows that the timing requirements of the TE28F160C3TC80 are
too low for the Write Pulse Width and the Data Setup to WE going high
parameters. This can be avoided by specifying the correct number of wait
states in the MegaWizard Plug-In.
For the second example, assume that the AHB2 clock is 50 MHz and that
the rest of the settings on the EBI block are the same as in the previous
example, except that the number of wait states is now specified as 6.
Figure 10 shows the simulation waveform of a read and write to the
device, demonstrating that all of its timing requirements have been met.
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Figure 10. ModelSim Waveform—Flash Timing Requirements Met
Figure 10 gives the timing values listed in Table 5:
Table 5. Simulation Results (1)
Parameter
Value
WE# (CE#) pulse width
140.03 ns
Data setup to WE# (CE#) going high
140.03 ns
Address setup to WE# (CE#) going high
200.03 ns
Address setup to WE# (CE#) going high
60.00 ns
Note:
(1)
Although the above example uses 6 wait states, the EBI would work with this Flash
if 2 or more wait states were used.
1
Connecting to
Multiple
Memory Blocks
on the EBI
18
It is very important to understand the timing requirements of the
flash memory used on the EBI block and set the EBI parameters
in the Quartus II MegaWizard Plug-In accordingly.
The EBI can interface to four 32-Mbyte blocks, which means that one flash
memory can be connected per block. For example, a designer could
connect four TE28F160C3TC80 flash memories to the EBI. When
connecting multiple memories on the EBI and using boot-from-flash
mode, the chip-selects for blocks other than EBI0 should be pulled to their
de-select level at power-up. Figure 11 shows a top-level block diagram of
four memories connected to the EBI.
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AN 143: Using the Expansion Bus Interface
Figure 11. Multiple Blocks on the EBI
Block 0
EBI_CS[3:0]
CS0#
EBI_WE_n
WE#
EBI_OE_n
OE#
nReset
RP#
EBI_A[24:1]
A19-A0
EBI_DQ[15:0]
D15-D0
Intel
28F160C3
[0:19]
Excalibur Device
CS1#
(1)
Block 1
WE1#
IDT71V416
OE#
EBI_BE[1:0]
SRAM
A17-A0
D15-D0
EBI_CLK
Block 2
CS2#
(1)
WE2#
OE#
Memory-Mapped
Device
EBI_ACK (2)
A18-A0
D15-D0
CS3#
(1) Memories connected to CS1, CS2 and CS3 must
be pulled such that the devices are not selected
at power-up
(2) The signal is not supported in the present version
of the silicon
(1)
Block 3
WE3#
OE#
RP#
Intel
28F320C3
A20-A0
D15-D0
1
Altera Corporation
EBI_A [0] is unused, to provide the correct addressing offset
for the flash memory connected to the EBI. This is needed to read
the correct 16-bit or 8-bit data from the memory.
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Booting From
Flash Memory
At power-up, the embedded processor in an Excalibur device selects the
memory that is connected to the EBI0 block. Therefore, it is important to
deselect other memories on the same data bus as the block 0 memory.
Pulling CS1, CS2 and CS3 high or low prevents all memories being
simultaneously active.
This section describes how to program flash memory connected to the EBI
using the Altera-provided programming utility, exc_flash_programmer.
This utility runs on a host PC and interfaces to the Excalibur device via
JTAG, using either a ByteblasterMV™ cable connected to a parallel port
(LPT1/LPT2) or a MasterBlaster™ cable via a serial port or USB.
exc_flash_programmer can only program flash memory devices that
include a CFI data structure. The data structure allows
exc_flash_programmer to determine the command interface and obtain
nformation about the device. exc_flash_programmer carries out the
following procedure to authenticate the connected flash memory:
1.
Issues the standard Query Access Command (0x98), allowing read
output of the CFI query data structure.
2.
Checks for the existence of CFI by comparing the first three data
elements with the ASCII string QRY. If this comparison fails, the
device does not support CFI and is rejected.
3.
Reads in the rest of the CFI data structure and checks that the device
interface is × 16. If the interface is × 8 or × 32, the device is rejected.
4.
Checks that the primary command-set ID is 3 (Intel boot-block) or 2
(AMD boot-block). If any other code is found, the device is rejected.
Either top or bottom boot block is acceptable.
5.
Checks that the device supports only two erase regions. Devices
with more than two erase regions are rejected.
To be programmed by exc_flash_programmer, it is necessary for a flash
memory device to meet criteria 1 to 5.
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Flash Memory
Compatibility
with Excalibur
Devices
Excalibur devices expressly support certain types of flash memory device,
although not all. As well as listing the device types, this section explains
how to determine whether a flash memory is compatible and can be
programmed by exc_flash_programmer utility version 2.1, build 166.
Flash Memory Types Supported by Excalibur Devices
The following flash memory types can be programmed using the
exc_flash_programmer utility version 2.1, build 166:
■
■
Any 16-bit flash devices compatible with Intel 28FXX0C3 (top or
bottom block) advanced boot block flash memories (primary OEM
command set to 0003).
Any 16-bit flash devices compatible with AMD AM29DL32XD
advanced boot block flash memories ( primary OEM command set to
0002).
Flash Memory Types Not Supported by Excalibur Devices
The following flash memory types are not supported by the
exc_flash_programmer version 2.1, build 166:
■
■
Any 3-V Intel StrataFlash memory (e.g. 28F128J3A, 28F640J3A,
28F320J3A)
Intel advanced boot block flash memories with the suffix B (e.g.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3)
Determining the Compatibility of Flash Memory
The best way to determine whether exc_flash_programmer supports a
given flash memory is as follows:
Altera Corporation
1.
Ensure that the flash memory supports CFI.
2.
Determine whether the CFI query table meets requirements 1 to 5 in
“Booting From Flash Memory” on page 20.
1
To use a flash memory that is not supported by the Excalibur
flash programmer, you must create a compatible programming
algorithm.
1
Known issues with the EBI are documented in the appropriate
Excalibur device errata sheets. Refer to the Altera website at
http://www.altera.com for further details.
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