Nanoelectronic Scaling Tradeoffs: What does
Physics have to say?
Victor V. Zhirnov
Semiconductor Research Corporation
1
Outline
u
u
u
u
u
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Technology Roadmap on Semiconductors
Fundamentals of information processing,
Fundamental limits to scaling
Thermal Limits
Message: We suggest that the benefits from
nanoelectronics research may, in the -Short term lie with the invention of new structures,
materials and processes that extend the CMOS
technology platform
v
u
Radical thermal solutions are needed
Long term enable invention of entirely new information
processing technologies
2
International Technology Roadmap on Semiconductors
u
A very detailed industrial perspective on the future
requirements for micro/nano electronic technologies
v
u
u
u
u
Goal is to continue exponential gains in performance/price
for the next fifteen years
Built on worldwide consensus of leading industrial,
government, and academic technologists
Provides guidance for the semiconductor industry and for
academic research worldwide
Content: critical requirements and judgment of status
Projects that by 2016, half-pitch spacing of metal lines will
be 22 nanometers and device gate lengths will be 9
nanometers
3
Moore’s Law: Minimum Feature Size
500
Minimum Feature Size (nm)
350
1994
250
1997
1998
180
1999
130
2000
100
70
50
35
25
‘95
‘00
‘05
‘10
4
Devices will soon be on the
“molecular” or “atomistic” scale
1.00E+27
Atoms per Bit
1.00E+24
IC and Bio-based device
converge
ICdensity
and bio-based
device
densities converge
1.00E+21
1.00E+18
1.00E+15
Molecular
Molecular
devices
Devices
1.00E+12
1.00E+09
1.00E+06
1.00E+03
1.00E+00
-60
-50
-40
-30
-20
-10
0
Years from 2000
10
20
30
40
6
Evolution of Electronics
Controllable
resistor
Analog: TV, radio,
communications...
Switch
DIGITAL
INFORMATION
PROCESSING
Digital: Computation
General Purpose Computer (GPC) accepts arbitrary types of data and sets of
instructions to perform arbitrary tasks of transmission, processing, and storing
the information
Parameters of GPC:
u Number of components (integration density/functional complexity)
u Speed
u Energy consumption
7
What is Information?
Information is…
u …Measure of distinguishability
u …A function of a priory probability of a given state or
outcome among the universe of possible states.
I = K ln N
N min = 2
I ( N min ) = 1
1 = K ln 2
The binary choice: YES/NO, 1/0 etc
1
K=
ln 2
N = 2n
1
I = K ln 2 =
n ln 2 = n = log 2 N
ln 2
n
8
Constituents of the Information Theory
u
Constituents of the Information Theory
•
•
u
Sender and recipient
Symbols (microstates) as elementary units of information
Information carriers
Information is physical!
9
The Abacus, an ancient digital
calculating device
Information is represented in digital form
Each column denotes a decimal digit
Binary representation: two possible positions for each bead
A bead in the abacus is a memory device, not a logic gate
10
Source: IBM
Particle Location is an Indicator of
State
1
1
0
0
1 0
12
Two-well bit
a
Eb
w
Eb
a
w
13
A physical system as a computing
medium
u
u
u
u
We need to create a bit first. Information processing always
requires physical carrier, which are material particles.
First requirement to physical realization of a bit implies
creating distinguishable states within a system of such
material particles.
The second requirement is conditional change of state.
The properties of distinguishability and conditional change
of state are two fundamental properties of a material
subsystem to represent information. These properties can
be obtained by creating energy barriers in a material
system.
14
Kroemer’s Lemma of Proven
Ignorance
u
u
If in discussing a semiconductor problem,
you cannot draw an Energy-Band-Diagram,
this shows that you don’t know what are you
talking about
If you can draw one, but don’t, then your
audience won’t know what are you talking
about
15
Barrier engineering in semiconductors
By doping, it is possible to create a built-in field and energy barriers of
controllable height and length within semiconductor. It allows one to achieve
conditional complex electron transport between different energy states inside
semiconductors that is needed in the physical realization of devices for
information processing.
p
n
n
16
Heterojunction barriers
w
Eb
Double barrier
a
Superlattice
17
Example: Field Effect Transistor
Long Channel
Short Channel
It is possible to derive MOSFET I-V equation form the
two-well one-barrier model
18
Ideal von Neumann’s Computer
Designers and Users want:
u Highest possible integration density (n)
v
v
u
Highest possible speed (f=1/t)
v
u
To keep chips size small and increase yields
To increase functionality
Speed sells!
Lowest possible power consumption (P)
v
v
Decrease demands for energy
The generation of too much heat means costly cooling
systems
19
Binary Information Throughput (BIT)
BIT is the maximum number of binary
transition per unit time
BIT = nbit f
- one measure of
computational capability
nbit – the number of binary
states (e.g. transistors)
f-switching frequency
BIT, Mbit/ns
10000
1000
100
10
1
2000
2005
2010
2015
2020
Year
20
Energetics of Computation
P = Ebit nf
Requirements for an ideal computer:
(integration density)
n=max
(switching frequency)
f=max
(power)
P=min
BIT=max
21
Power density will increase
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Sun
Nuclear
Reactor
8086
10 4004
Hot Plate
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Power density too high to keep junctions at low temp
®
14
22
Lowest Barrier:
Distinguishability Barrier
a
Distinguishability D implies low
probability of spontaneous transitions
between two wells (error probability)
D=max,
=0
D=0,
Classic distinguishability:
=0.5 (50%)
Π classic
Eb
Eb
a
Eb
= exp(−
)
k BT
Minimum distinguishable barrier: _=0.5
1
Eb
= exp(−
)
2
k BT
Eb=kTln2
Shannon - von Neumann - Landauer limit
23
Smallest Size:
The Heisenberg Barrier
∆x∆p ≥ h
∆E∆t ≥ h
acrit
h
=
2mEb
t min
h
=
Eb
Eb=kTln2
24
Classic and Quantum
Distinguishability @ =0.5
Π classic
min
b
E
Eb
= exp(−
)
k BT
= k BT ln 2
a
Eb
Eb
a
WKB: (Tunneling)
2 2m
Π quantum = exp(−
a Eb )
h
2
2
h ln 2
min
Eb =
2
8ma
a
Eb
Eb
a
25
Total Distinguishability @
=0.5
Π error = Π classic + Π quantum − Π classic Π quantum =
hEb + 2akT 2mEb
Eb
2 2m
= exp(− ) + exp(−
a Eb ) − exp(−
)
kT
h
hkT
1.2
1.1
min
b
E
2
h (ln 2)
≈ kT ln 2 +
2
8ma
Eb/kT
Generalized expression for
the minimum energy barrier
to create a bit
2
1
0.9
0.8
0.7
kTln2
0.6
0
5
10
15
20
a, nm
26
Least Energy Computer
1) Minimum distance between two distinguishable states (Heisenberg)
xmin
h
=a=
= 1.5nm(300 K )
2mkT ln 2
2) Minimum state switching time (Heisenberg)
h
t st =
= 1.2 × 10 −13 s (300 K )
2kT ln 2
3) Maximum gate density
n=
1
2
xmin
4) Maximum binary throughput BITmax
gate
= 4.6 ×10
cm 2
13
(kT ln 2) 2
7 Tbit
= 2m
= 10
3
h
ps
27
Total Power Consumption at
Minimal Energy per bit - {kTln(2)}
Eb kT ln 2 2
Pbit =
=
= (kT ln 2) 2
t sc
t sc
h
Pchip
W
= 4.74 ×10
2
cm
6
Pchip = nPbit
T=300 K
The circuit would vaporize when it is turned on!
28
Single Electron Devices Don’t Avoid the Power
Problem
Electrostatic energy
to add an electron to
a particle with size w
e-
Ea =
e
4
0
fEa
P = Ea fn = 2
w
f=10 GHz
w
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
100000
Power, W/cm2
Ea, eV
w
Ebit>Ea
10000
1000
100
10
1
0
5
10
w, nm
15
20
0
10
20
30
w, nm
In sub-10 nm single electron devices, the minimum energy to
add/remove electron is much larger than kT, and it increases as
size deceases.
29
Power vs. Error trade-off
Πerr
False bit
occurrence
Computation at Πerr=0.5 is impossible
Additional Static
(leakage) power
In useful computation, Πerr <<0.5,
hence much larger total power is
needed
1.E+08
Ptotal , W
1.E+08
8.E+07
6.E+07
a=1nm;
n=1014 bit/cm2;
f=3x1013 Hz
4.E+07
2.E+07
0.E+00
0
0.1
0.2
0.3
0.4
0.5
0.6
err
30
Dynamic and Static Power
Eb
Pd = I onV = ⋅ n ⋅ ef ⋅
= Eb fn
e
Eb Pd
Ps = ioff V = n ⋅ ef ⋅ Π err ( Eb ) ⋅
= Π err ( Eb )
e
1.00E+09
1.00E+09
1.00E+08
1.00E+08
1.00E+07
1.00E+07
P, W
P, W
a=1nm; n=1014 bit/cm2; f=3x1013 Hz
α=1
α=0.05
1.00E+06
1.00E+05
0
kT
0.05
0.1
0.15
Eb, eV
dynamic power
static power
total power
1.00E+05
dynamic power
static power
total power
1.00E+04
1.00E+06
1.00E+04
0.2
0.25
0
0.05
0.1
0.15
Eb, eV
0.2
0.25
31
Will Spintronics Alleviate the Power
Problem?
u
Expectations:
v
v
u
ultra low power ???
ultra high density ???
E↑
1
∆E = 2
r
B
B
B
E↓
A quote: “Spintronics would use much less power than conventional electronics,
because the energy needed to change a spin is a minute fraction of what is
needed to push charge around”
Example:
T=300 K
B=1.5 T
(practically viable)
u
0
∆E=2 µB B = 2_9.27_10-24 J / T_1.5 T =2.78_10-23 J= 1.74_10-4 eV
Π err
 2 BB 
= exp −
 = 0.99
 kT 
(µB = 9.27_10-24 J / T)
Is the very low energy to change state an advantage (e.g. low dynamic
power) or a disadvantage (e.g. high error probability) for applications of
spin devices in information processing?
32
How much heat a solid system
can tolerate?…
ITRS 2001 projects 93 W/cm2 for MPU in 2016
Several hundred W/cm2 is close to known limits of
heat removal from a 2-dimensional solid material
structure with Tmax =125°C
Experimental demonstrations of on-Si cooling systems
(without active devices):
680 W/cm2
thermoelectric (Zheng et al.)
790 W/cm2
microchannel (Tuckerman and Pease)
33
…and implications to the Roadmap:
Inflexion of ITRS vectors?
300 K
l
Heisenberg barrier
1.00E-08
Memory
1
1.00E-09
l is the “cell size”:
t, s
1.00E-10
I=n-1/2
4
lmin=a
Logic
1.00E-11
lMPU=(11-15)a
P=100 W/cm2
3
1.00E-12
2
1.00E-13
1
10
l, nm
100
Heisenberg barrier
1000
34
Implications for Nanoelectronics
Utilizing ElectronTransport
u
Scaling to molecular dimensions may not yield
performance increases
v
u
We will be forced to trade-off between speed and density
Optimal dimensions (depending on speed/density tradeoffs) for electronic switches should range between 5 and
50 nm, and this may be achievable with silicon technology
v
Within the scope of ITRS projections
35
Fundamentals of Heat Removal
Quotes from anonymous scientists working at the frontiers of
nanoelectronics:
“ Heat removal is not an issue. Simply, engineers must invent
better technologies for heat removal and cooling ”.
“Heat can be dissipated somewhere else”
Three fundamentals of heat removal:
1)The Newton's Law of Cooling: q=h(Th-Ta)
(h-heat transfer coefficient)
2) The Ambient: Ta=300 K !!!Wcool
3) The Carnot’s theorem:
Work to
be done
Ta − Tc −
=
Q
Tc
Heat to be
removed
36
Newton’s law of cooling
Q=h*A**(Th-Ta)
Cooling method
.
Air, natural convection
Air, forced convection
.
Water, natural convection
Water, forced convection
max (Th-Ta)=100K
h, W/cm2·K
0.001
0.01
0.1
1
.
Boiling
10
Max P=1000 W/cm2 ? (A=const)
*h
– the heat transfer coefficient
**A - area
37
The ambient interface
Chip interface
Q1
Tj
Ambient interface
A1
Chip
Q2=Q1+W
Refrigerator
R1
W
R2 A2
1
R=
Ah
- thermal
resistance
Air
air, T=300 K
Q2 > Q1
h2 < h1
A2>A1
Surface extension is
essential for removal of
high heat fluxes to the
environment
Lbox
Device
Ahot<<Acold
Boiling38
Thermoelectric cooling
Chip
R1
T=125 C
Hot
side
R2
Heat rejection to the ambient is a
universal element of all cooling
methods and requires surface
extension
Effect of varying R2 (e.g. changing air’s
humidity, temperature etc.) on the heat
removal rate and junction temperature, for
a thermoelectric cooler, compared with air
cooling by a fan.
39
How Much Volume is Needed to Transfer
Chip Heat to the Ambient?
Air: Ta=300 K
Cold wall:
Q>107 W
Tcold=350 K
Example:
h=0.001 W/cm2K
n=1014 bit/cm2
t=0.01 ps
BIT=104 Tbit/ps
Box size:
a=1 nm
P=107
W;Ahot=1
Ebit=0.08 eV (~4kT)
cm2
Lbox
Πerror=10% /device
P=107 W/cm2
Thot=400 K
Acold>2x108 cm2
Lbox>141 m
Very Big Box!
Example: computer min. size vs power
P, W
Q>P
Acold
P
>
hnc ∆T
Approx. box dimensions, cm
1
3x3x0.5
10
10x8x1
100
30x20x8
1000
100x50x40
10000
182x182x182
40
Carnot’s Refrigerator and
Cryogenic Computation
The efficiency of heat engines dramatically drops at T<<Ta
Wcool
Ta − Tc −
=
Q
Tc
Min. total power needed to run a 100 W chip:
at 77 K - 300 W
at 4.2 K - 7 kW
41
Cryogenic Computation with nanodevices
total
Ebit
Ta − Tdev
Ta
Ta
= Ebit +
Ebit =
Ebit =
Tdev
Tdev
Tdev

h 2 (ln 2) 2 
k BTdev ln 2 +
=
2
8ma 

Ta h 2 (ln 2) 2
= k BTa ln 2 +
> k BTa ln 2
2
Tdev 8ma
1000.00
T=300K
Eb, meV (total)
T=4K
100.00
10.00
0
5
10
15
20
Due to tunneling, the
power consumed by the
device depends on both
operating temperature and
size that manifests itself
with unexpectedly dramatic
increases in total power
consumption at cryogenic
temperatures.
a, nm
42
The barriers dilemma
u
u
u
Energy barriers are key components to provide Information
Flow
Energy barriers are negative factor for Heat Flow
Can we think of radically new ways of heat removal based
on coherent heat flows, e.g. heat lasers or solitons?
Reflection
phonons
Transmission
A driver for physical layout?
43
A question – What to do?
Gate
Source
Drain
Substrate
Silicon MOSFET
?
IBM CNTFET
44
Energy efficiency of CMOS
Does practical CMOS operate far from fundamental limits?
u
2016 ITRS 22-nm Node:
Fundamental limits
h
= 1.5nm(300 K )
2mkT ln 2
v
xmin: Channel length
9 nm
xmin = a =
v
Esw: Switching energy
2 x 10-18 J
Esw > kTln2 = 3 x 10-21 J
v
Eb: S-Ch barrier height
~0.4 eV
Eb>kTln2=0.02 eV
v
Electrons/switching event
~50
1
v
Energy/electron
4 x 10-20 J~12 kT 3 x 10-21J ~ kT
45
Can we decrease the energy of
CMOS?
2 x 10-18 J
3 x 10-21J
Yes (in principle):
Decrease the barrier height:
0.4 eV
0.02 eV
Eb
E
Π err = exp(− b )
kT
12kT
0.001%
8kT
0.03%
4kT
2%
kT ln2
Decrease the number of
electron per switching event:
50
1
50%
46
What to do? (Cont’d)
?
Gate
Source
Quantum Computer
Drain
Substrate
Silicon MOSFET
Cellular Non Linear Network
Conventional von Neumann
Architecture
New Information
Processing Architectures
47
2003 ITRS: Emerging Research
Devices
Device
FET
Density
(dev/cm2)
Switch
Speed
Circuit
Speed
Switching
energy, J
Binary
throughput,
GBit/ns/cm2
3E9
RSFQ
1D
struct
RTD
SET
Molecul
ar
QCA
Spin
transistor
106
3E9
3E9
6E10
1012
3E10
3E9
700
1.2 THz
?
1 THz
1GHz
?
30 MHz 700 GHz
GHz
30
400 GHz 30 GHz 30 GHz 100 MHz 1 MHz
1 MHz
30 GHz
GHz
-18
2x 10-19
10-18
]
-16 E: [> 10
-18
2E-18
2E-18 >2E-18
1.3x10
-17 2 x 10
[>1.4E-17
[>1.5E-17]
M:>4x10
86
0.4
86
86
10
?
0.06
86
48
Classic to Quantum transition
u
Classic memory bits become indistinguishable, which limits
our ability to use them for computation
BUT
u
u
The superposition of indistinguishable states is a key
concept of Quantum Computation
A quantum bit or qbit is a physical system with two
quantum states
49
Power of quantum computing
u
Quantum information storage
v
N quantum bits stores 2N complex numbers
Consider information in 300 entangled qubits
2300 = 1090
n
Compare to the total number of atoms in the Universe:
Natoms=1080
n
If dramatic improvement of the information throughput can be
achieved, the cryogenic operation might be affordable
50
Neuromorphic Computing
u
Implies computational schemes and systems resembling
operation of human brains.
v
u
The potential capabilities of neuromorphic computers could
be close to those of the brain, thus enabling e.g. artificial
intelligence
Properties of brain:
v
v
v
v
v
Mass – 1.5 kg
Volume – 1.5 l
Energy consumption – ~10 W
Information stored – 1e14 bits
1e13 bits/s
51
Conclusions
v
Fundamental considerations suggest that the potential
benefits from replacing CMOS devices with new types of
electron transport devices may be limited
v
Search for radically new methods of heat removal is one of
the most critical research directions
v
The exploration of alternative approaches to von Neumann
type computing, such as brain or Reversible/Quantum
Computation, is becoming a strategic imperative.
n
We need a concerted effort in these areas because of the long
lead times for the introduction of radically new technologies
52