A SUB-THRESHOLD PASSIVE STEP-UP RECTIFIER
FOR VIBRATION ENERGY SCAVENGERS
J. Singh1, C. Robert1, A. Boegli1, P. Janphuang2, D. Isarakorn2*,
D. Briand2, N.F. de Rooij2, P.A. Farine1
Ecole Polytechnique Fédérale de Lausanne (EPFL)
Institute of Microengineering (IMT): ESPLAB1, SAMLAB2
*Presenting Author: jaskaranjeet.singh@epfl.ch
Abstract: This paper reports on the design and experimental verifications of a passive step-up rectifier for MEMS
piezoelectric energy scavengers. The purpose of the proposed circuit is to improve system startup for vibration
micro-generators without the need of an external source of energy. The design chosen is based on a voltage
multiplier where conventional diodes are replaced by PMOS low-VT transistors. The circuit is produced in 1.8V
0.18μm UMC CMOS technology. Test and verifications were performed using a real piezo scavenger providing an
AC voltage of 0 to 350mVpeak at a frequency of around 2.4 kHz. Up to 2V DC was measured at the output of the
rectifier.
Keywords: system startup, sub threshold implementation, passive step-up rectifier, piezoelectric energy
scavengers, 180nm UMC CMOS
with1simulation results and layout. Section IV reports
on the experimental verifications of fabricated circuit
I. INTRODUCTION
and measurement results. Further these results are
Nowadays, the power consumption of ultra low
compared to the simulated ones and discussed. In the
power electronics is reduced to a level, which makes
final section some conclusions are drawn.
possible having devices supplied by micro energy
scavenging systems. However in almost all the cases,
II. POWER SUPPLY MICROSYSTEM
the energy provided by the scavengers cannot be
directly used to power electronic devices, some
This section presents the roles of different blocks
formatting like rectification or stabilisation is thus
of a complete DC power solution based on piezo
mandatory. Many factors have to be taken in account
scavenger (Figure 1).
in the design of the bridge between harvester and
Energy Scavenger Powered System
electronic devices. The major one is obviously
DC Power Supply
efficiency, but the space required and the need of
passive
power
external components has also to be considered.
rectifier
management
In this work, it has been chosen to concentrate on
final
piezoenergy
application
scavenger
storage
AC power systems typically micro piezo scavenger.
active
DC-DC
The considered piezoelectric micro-generators have,
rectifier
under reasonable mechanical excitation, an output
voltage that is comparable to the threshold voltage of
Figure 1: Piezo scavenger based Power supply for an
common CMOS technologies. This makes the use of
application
standard passive methods to rectify AC voltage based
The piezo harvester is the heart piece of the system
on diodes inefficient [1]. To overcome this problem,
since
it is the only power source. Under mechanical
active and self-sustainable rectifiers have been
excitation,
it starts to supply voltage to the rest of the
proposed and successfully developed [2], [3].
system.
Since
the amplitude of AC output voltage is
Nevertheless, the need of an initial energy to activate
low, it has to be rectified and stepped up to a sufficient
these circuits leads to the critical problem of the
DC level to supply the final application. In the
startup phase of the system.
proposed scheme there are two rectifiers, which are
An approach, which is presented in chapter II, was
placed as interface circuits between piezo harvester
proposed by [4] to solve this problem. The idea is to
and energy storage element. During initial phase only
implement two rectifiers (Figure 1), a fully passive one
the passive rectifier can operate. Once the system is
having low efficiency but which can start from scratch
internally sufficiently powered up, the active rectifier
and an active one with high efficiency though with the
can start and thus supply - thanks to its high efficiency
need of an initial power.
- additional energy to system. So the system will
This paper discusses a sub-threshold fully
maintain at high energy level. The power management
integrated passive step-up rectifier. In section II a
block is also an important component, since it has to
typical block schematic of a piezo scavenger powered
system is presented and explained. The justification of
*
Department of Instrumentation and Control Engineering, Faculty
the design chosen for rectifier and its subcomponents
of Engineering, King Mogut’s Institute of Technology Ladkrabang,
parameters are given in section III, linked
Bangkok, Thailand
control the behaviour of the power supply in function
of the energy level.
Piezo harvester
Depending on the technology used in silicon micro
machined piezoelectric scavengers (type of
piezoelectric materials and excitation mode, d31 and
d33) and on the operating conditions (vibration’s
amplitude can be very low), the output voltage level
generated can be limited to few hundred millivolts and
even less. EPFL-SAMLAB has reported recently on a
silicon micro machined scavenger based on epitaxial
piezoelectric thin films [5]. This device exhibits very
interesting characteristics such as high current level
(μA range), high power (μW range) and small
optimum load (k range) but the output voltage is low.
III.
RECTIFIER’S DESIGN
This section justifies the choice of rectifying
circuit and its subcomponents parameters.
Choice of design
The sub-threshold AC input voltage (typically 0 to
350mVpeak) provided by considered piezo-electric
micro-generators has to be converted to DC voltage
and stepped up to a useable level to supply electronic
devices. This step-up conversion can be done in
different ways the most current one being the use of a
transformer [1] for the step-up followed by a passive
step-up rectifier [1] for DC conversion or the use of an
active step-up rectifier [2].
The transformer is made of two inductively
coupled coils. As the integration in ASIC of needed
big value coils is not possible and it is requested to
have a step-up rectifier without any external
components, the transformer is not a suitable solution.
The active step-up rectifier combines capacitors
and switches driven by amplifiers. In order to operate
amplifiers an external power supply is needed. Since
there is no such power supply when the system starts,
the active rectifier cannot be used alone.
In order to fulfil the given specifications of a
passive fully integrated step-up circuit, the voltage
multiplier [6] was chosen as a starting point. It is
composed of a network of capacitors and diodes. Both
components are well suited for ASIC integration. This
permits limiting the need of external components, thus
reducing the required place and total system costs.
Choice of the subcomponents
Given that the amplitude of the provided voltage
by considered piezo scavengers is lower than threshold
voltage of regular diodes, it is not possible to use the
latter in the voltage multiplier circuit. In order to
overcome this problem, the ordinary diodes have been
replaced by special diode-connected transistors.
In the chosen 180nm UMC CMOS technology
design kit, ten types of transistors are proposed.
Among these, the transistor type that well matched an
ideal diode with low threshold voltage has to be
selected. A first simulation consisting of testing all the
transistors in diode-connected configuration permitted
to do a first ranking of the transistors.
The choice of diode-connected transistor type is
critical, as it will directly influence performances of
the step-up rectifier. However before selecting the best
suited transistor type and optimizing it, the capacitor’s
value that has to be driven should be estimated. Given
that bigger capacitor’s values lead to shorter charging
time of the fixed output capacitor (Figure 2) and since
the area for the targeted chip is limited, efforts were
made to maximize the capacitance’s density. Moreover
for testing reason, it was decided to integrate five
independent voltage multipliers, with respectively one
to five stages, on the same piece of silicon, leading to a
total of a thirty capacitors. Due to the highest
capacitance’s density, Gate-Bulk capacitance of PMOS
transistors was chosen to implement the main part of
thirty capacitors. Although the absolute value of this
type of capacitance may greatly vary in function of the
applied voltage, this does not significantly impair the
functionality of the selected design. To maximize even
more the capacitance’s density, dedicated metal-metal
capacitors were stacked over the PMOS capacitors.
This strategy permits obtaining a capacitance density
of 3.2fF/μm2, which is 3.2 times bigger than the one of
meta-metal capacitors. So it was possible to obtain a
value of 150 pF for each of thirty implemented
capacitors.
After having fixed the capacitance value, the
strategy consists of choosing the optimal diode-tied
transistor type. To do so different voltage multipliers
cells composed of different transistor types were
created. Transient simulations with sinusoidal input
signal with amplitude of 150 mV at a frequency of 2.4
kHz have been conducted. The voltage multipliers of
transistor type PMOS 180nm Low-VT gave the
highest output voltage.
Optimization
The next stage of optimization consists of defining
the optimal width and length of each transistor in order
to obtain the best results. Simulations of schematic
represented in Figure 2 were done to characterize the
influence of transistor length and width. There is a
trade-off between the highest output voltage and the
shortest charging time. After multiple iterations
optimal transistor sizes were defined.
Rs
Vin
~2.4 kHz
C1
C1
T1
T2
T1
T2
Vout
C2
C2
CL
(a)
(b)
(c)
Figure 2: (a) simple electrical model of piezo
scavenger, (b) a stage of voltage mutliplier, (c) ouptut
load (1nF)
Simulation results
The following figure represents transient
simulation results of output voltage for the five
targeted voltage multiplier implementation with
optimal parameters.
1.0
thick PZT
cantilever
accelerometer
m
8m
Output after 5 stages
V
rectifier circuit
Vout [V]
Output after 4 stages
Output after 3 stages
0.5
Figure 5: Test setup for the electronics board
interfaced with PZT MEMS based scavenger
Input 150mVpeak
0
1
Time [s]
2
Figure 3: Output Voltage of different stages
The stepwise voltage multiplication in function of
the number of stages is visible.
Layout
1 stage
5 stages
4 stages
2 stages
3 stages
Area : 1.535 mm x 1.535 mm
Technology : UMC 0.18 μm
The ASIC was produced in 1.8V 0.18μm UMC
CMOS technology. It is composed of five independent
sub-circuits which correspond to voltage multipliers
with one to five stages. This allows to measure each
circuit independently, thus allows a better comparison
between measurements and simulations. The chip area
mainly is occupied by thirty 150pF capacitors
connected together with corresponding thirty
transistor-diodes. It also includes necessary test bond
pads without any ESD protection to avoid parasitic and
leakage. The whole chip occupies an area of 2.56mm2
(figure 4).
Figure 4: Photo of rectifier integrated circuit
EXPERIMENTAL VERIFICATION
The fabricated chip was tested under real
conditions in order to compare the measurement
results with the simulation. To achieve best
experimentation results an adequate PCB have been
designed which took care of important points to do the
measurements. This includes the separated application
of input voltage to each cell and the addition of CMOS
based voltage follower with ultra low input current
(range fA) at the output. The very high input
impedance (more than 1TΩ) of such interface prevents
the parasitic effect introduced by the input impedances
Tests Description
At first, the piezo scavenger was replaced by a
laboratory frequency generator. The output voltage
was measured in function of the amplitude and
frequency of the applied voltage.
After these tests, the chip was connected to a thick
sheet piezo scavenger developed at EPFL-SAMLAB
[7]. A modified version of the thick piezo scavenger
providing low voltage at the frequency of around 2.4
kHz was used as a proof of concept. This scavenger
was fixed on a magnetic shaker (Figure 5), whose
amplitude of acceleration and frequency could be set.
Measurement results
The measured DC output voltages after the
different number of voltage multipliers stages are
shown in Figure 6. The step-up conversion can be
observed as well in simulation as in measurement. The
curves obtained from the measurement show a nonlinear behavior, where the curves from the simulation
are quite linear as function of the input voltage. In the
simulation the difference between the outputs of
different stages is noticeable for the given range of
50mVpeak to 400mVpeak. For the measurement this
difference becomes visible for an input voltage bigger
than 150mVpeak. The measured output voltage for “one
stage cell” fits quite well with the simulation. For the
other cells the simulation and measurement results
diverge in function of the number of voltage multiplier
stages. An output of 0.4V to 2V was measured for an
input range of 150mVpeak to 350mVpeak.
3.5
3.0
Vout DC [V]
0.0
magnetic shaker
Output after 2 stages
Output after 1 stage
IV.
of conventional measurement devices.
2.5
2
1.5
Vout DC after 5 stages
Vout DC after 4 stages
Vout DC after 3 stages
Vout DC after 2 stages
Vout DC after 1 stage
input frequency: 2.4 kHz
1
0.5
0
50
100
150
200
250
Vin AC[mVpeak]
300
350
400
Figure 6: Output DC voltage in function of input AC
voltage provided by ideal source, simulation (lines),
measurement (symbols)
Vout [V]
Figure 7 shows the output of voltage multiplier in
function of the frequency of input voltage whose
amplitude is 150mVpeak. The rising of voltage
multiplier’s output voltage in function of the input
frequency can be noticed. Further the outputs of all
cells during simulation and measurement saturate for
an input frequency bigger than a certain value only.
The measured output voltage for “one stage cell” fits
quite well with the simulation. For the other cells the
difference between simulation and measurement
becomes bigger when the number of voltage multiplier
stages in series increases.
CONCLUSION
A sub-threshold step-up voltage rectifier was
designed and fabricated using 0.180μm technology,
which boosts up the low AC voltage provided by
micro-generators to a useful DC voltage. The proposed
design is fully integrated, it uses PMOS Low-VT
transistor in diode-connected configuration instead of
diodes. This circuit was tested and verified using a real
piezo scavenger, which provided an AC voltage of 0 to
350mVpeak at a frequency of around 2.4 kHz. Up to 2V
DC was measured at the output of the rectifier.
1.0
0.9
Vout DC after 5 stages
ACKNOWLDGEMENTS
0.8
Vout DC after 4 stages
The authors would like to thank “armasuisse Sciences
and Technologies” for supporting the project.
0.7
Vout DC after 3 stages
0.6
0.5
Vout DC after 2 stages
0.4
0.3
Vout DC after 1 stage
0.2
0.1
0.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
Frequency [kHz]
Figure 7: Output DC voltage in function of input
frequency of AC voltage provided by ideal source,
simulation (lines), measurement (symbols)
The results of the tests with the piezo scavenger
are shown in Figure 8. The obtained values during this
test are similar to those from the test with a laboratory
frequency generator. This fact validates the proper
operation of the circuit for input voltage at a frequency
in the range of some kHz and with amplitude of some
hundreds of millivolts.
2
1.5
Vout [V]
V.
1
Vout DC after 5 stages
Vout DC after 4 stages
Vout DC after 3 stages
Vout DC after 2 stages
Vout DC after 1 stage
Vout_peak AC of piezo scavenger
input frequency: 2.4 kHz
0.5
0
1
2
3
Acceleration [g]
4
5
Figure 8: Measured output DC or AC voltages in
function of applied acceleration on piezo scavenger
Discussion
Even if post-layout simulations have been taken in
consideration, the measured results are lower than the
simulated ones. One reason is the quality of the model,
indeed the performances in deep sub threshold region
(<150mVpeak) exhibit bigger discrepancies than the one
at higher level. A different explanation is the
technology spread. Sub-threshold circuits are more
dependent on the process variations [8].
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