iBOB1/2 Progress/Plans at
Haystack
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Alan Hinton
New to Haystack since May 2007
Sonar/Acoustics background.
Coming up to speed on current designs and
working on new designs.
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MIT Haystack Projects
using iBOB1
VLBI Mode 1
VLBI Mode 3 Single Duty
VLBI Mode 3 Double Duty
Geodetic Phase I
Geodetic Phase II (SX)
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VLBI Mode 1
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32 Channel PFB
Channel Bandwidth is 16 MHz
2 bit data
16 Channel output (VSI limited)
Output rate 1024MHz
Processes single IF
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VLBI Mode 3 Single Duty
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16 Channel PFB
Channel Bandwidth is 32 MHz
2 bit data
16 Channel VSI output
Output rate 2048MHz
Processes single IF
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VLBI Mode 3 Single Duty
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2-16 Channel PFBs
Channel Bandwidth is 32 MHz
2 bit data
16 Channel VSI output
Combined output rate 4096MHz
Processes 2 IFs
Uses ZDOK connector as second VSI port
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Geodetic Phase I
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32 Channel PFB
Channel Bandwidth is 32 MHz
2 bit data
16 Channel VSI output
Combined output rate 2048MHz
Can process any combination of channels from
IF0 and/or IF1 up to a total of 16 (VSI limited)
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Geodetic SX
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4-16 Channel PFBs
Channel Bandwidth is 16 MHz
2 bit data
16 Channel VSI output
Output rate 1024MHz
2 iBOBs connected via ZDOK
Can process any combination of channels from IF0,
IF1, IF2 and IF3 up to a total of 16 (VSI limited)
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MIT Haystack Projects using iBOB2
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Port existing iBOB1 designs to iBOB2 hardware
VLBI – Higher channel (finer resolution)
Geodetic – User configurable channel selection
Burst Mode Recorder
Spectrometer
Phased Arrays
DBE(iBOB2)-> long haul fiber -> MKVC
demo?
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MIT Haystack Development Plan
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Design/Test/Debug basic HDL Modules to support iBOB2
architecture
Write Linux Applications Modules
iBOB2 GUI
Signal Processing Tool Evaluation (AccelDSP,SynplifyDSP)
Design Application Specific Instrumentation
Need more input form other Observatories on development
status/plan
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iBOB2 current status
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ADC Module has been simulated
10Gbe Xilinx reference has been configured for
transmit only and simulated
QDRII+ Xilinx core has been modified/simulated for
the IC used on the iBOB2
Next is the corner turner
iBOB2 VSI output on GPIO
A lot of work needs to be completed/coordinated to
make iBOB2 fully functional
Need side bar meeting with NRAO to work on a
comprehensive plan, WBS, block diagram, etc.
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Basic DBE2 Modules
One PPS
Sync.
Data Timing
Module
SP Clock
Status
ADC
Atmel
AT84AD001B
N bit
Quantizer
Data Bus
Interface
N Channel
PFB
Digital Gain
Control
3-wire
Serial
Interface
RF Power Estimator
RF Power
Estimator
TVG Module
AGC Interface
QSH-DP
LVDS
Interface
DDR2
Memory
Controller
Data Corner
Turner
QDR II+
Bank1 Memory
Controller
10G
Ethernet
QDR II+
Bank2 Memory
Controller
External Bus
Control (EBC)
Linux OS
Linux Application
Interface GUI
GPIO
Interface
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Future items
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New ADC Design – both near and long term.
Tektronix’s is sampling @ 40Gbs! How do we
get there?
Multi/Parallel iBOB2 system configurations
Collaborate on new designs? WBS (Work
Breakdown Structure)
Any others ?
Questions
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iBOB2 items for discussion
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Board support package
Diag Software
„ Programming utilities (CPLD,FPGA,PPC)
„ Linux - Build
„ Software tools needed (anything special)
„ Manual
„ Borph
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Schedule
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VLBI
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