Hardware Technologies for Robust
Personal Communication Transceivers
Henry Samueli
Asad A. Abidi
Gregory J. Pottie
Yahya Rahmat-Samii
Integrated Circuits & Systems Laboratory
Electrical Engineering Department
University of California
Los Angeles, CA 90024-1594
UCLA Low-Power Transceiver Program
Objective: Low-power, handheld, robust transceivers for
indoor and mobile personal communications
Means: Investigate analog, digital, and antenna
technologies, coupled tightly to system design
Up to 160 kb/s
Robustness
∑ Space Diversity with Multiple Antennas
∑ Frequency Diversity with Spread-Spectrum
∑ Time Diversity with ECC/Interleaving
Low Power Dissipation
∑ Low-Voltage Custom Analog & Digital CMOS
∑ Monolithic CMOS 915 MHz Receive/Transmit Path
∑ Two-chip Design; Minimum Discrete Components
The UCLA Frequency-Hopped
Spread-Spectrum CMOS Transceiver
10b
Frequency
Control
Logic
Frequency & Timing
Acquisition
Baseband Data In
DDFS
SSB
Select
915 MHz
Local Oscillator
DDFS
PA
10b
Power
Control
Limiter
BPF
LPF
Baseband Data Out
90˚
Limiter
FSK
Detector
Digital
LNA
LPF
Analog
Limiter
BPF
LPF
90˚
Limiter
LPF
LNA
Performance Specifications of Handset
Power Dissipation of Handset 225 mW in receive, 300 mW in transmit
Frequency Band 902-928 MHz (unlicensed ISM band)
Radiated Power 20 mW (max); 20 µW (min)
Data Rate 2 to 160 kb/s (variable)
Duplexing Time Division Duplex between TX and RX
Multiple Access Method Frequency-Hopped Spread-Spectrum CDMA
Coding Rate-½ Convolutional Code (k=6)
Modulation Binary or Quaternary FSK
Power Supply 3 V (max)
IC Technology 1-µm bulk CMOS
Receive Antennas Multiple miniature embedded elements with space and polarization diversity
Direct Sequence
n
Frequency Diversity by making chiprate >> symbol rate
n
Equalization at chip-rate ➭ Highspeed signal processing required
n
Coherent receiver most common
n
Main advantage: SNR gain with
coherent detection, optimum
modulation
n
Limitation: High complexity
○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Spread-Spectrum Systems:
Hardware Implications
Frequency Hopped
n
Covers wide bandwidth with low
hop-rate
n
Equalization at hop-rate only
n
Simple binary FSK modulation may
be used
n
Non-coherent receiver is simple
n
Main advantage: Low-power receiver
n
Limitation: Sub-optimal channel
capacity
Diversity Techniques
e Multiple Antennas
n
Antennas receive uncorrelated signals
n
Use space and polarization diversity
e Frequency Spreading
n
Code-Division Multiple Access (CDMA); Direct Sequence
OR Frequency Hop
n
Time-Division Multiple Access (TDMA); Equalization
e Time Diversity
n
Coding
n
Interleaving
e Power Control
Power Amplifier
3V
3V
3V
75nH
902-928 MHz
from modulator
13nH
8µm
75µm
16µ
m
32µ
m
256
128
µm
µm
64µ
m
1-µH
Choke
DRF
0.7pF
Other half of
quasi-differential
power amplifier
FETs
Selection
Switched
100W
Antenna
• Amplifier attains 42% power conversion efficiency
at +15 dBm output power
• Binary-weighted array of FETs gives 36 dB of
power control (6-b word)
• Inductively-loaded preamp drives FETs above 3-V
supply
• Off-chip matching network filters out harmonics
Frequency-Hopped Synthesizer
Circuits
implemented on
this prototype
SINE
ROM
I
10b
DAC
Anti-alias
Filter
I
915 MHz
Local Osc
Q
COSINE
ROM
Q
10b
DAC
F/H S/S SSB
Phase Accumulator (11b)
Frequency Control Word (11b)
Direct Digital
Frequency Synthesizer
Anti-alias
Filter
Sign Select Control
•
DDFS produces samples of a sinewave at a frequency selected by 11-b word;
instantly agile frequency source
•
DDFS output range is 0➞13 MHz; adding up-converted outputs produces SSB
915➞928 MHz; subtracting them produces 902➞915 MHz
•
8-b matching required between channels for adequate image suppression
10-b, 80 MHz D-A Converter
1b(N)
Pipeline Delay Data
Registers
I & Q DDFS/DAC
27 mA at 3V, 80 MHz
3b (N)
3 bits (Word N)
LSB
MSB
1
φ1
φ2
φ3
0.5 pF
φ3
φ2
LSB
MSB
Charge Redistribution DAC
φ1
φ2
φ3
φ1
CM
φ2
+
+
φ2
φ2
CM
1
Q-to-V Buffer
• Low-power through differential implementation using
quasi-passive charge-redistribution pipelines
• Linearity limited by capacitance mismatch, voltagedependent parasitics
• Glitch free!
Measured DDFS/DAC Spectral Outputs
50 MHz Sample Rate
3 V Supply
50 MHz Sample Rate
3 V Supply
16.715 MHz
•
57 dB
62 dB
•
•
0
5 MHz
0
25 MHz
–57 dBc
• Spurious level as predicted
• set by capacitor mismatch
• Inter-cell capacitance causes
non-linearity at high frequency
Baseband Tone-Select Filter
RF In
Low-Order
Anti-alias
Filter
Fifth-Order Elliptic
Lowpass Filter
To Digital
FSK Detector
Tracking Hopped
Local Oscillator
Downconverted Spectrum
LPF Response
–13 MHz
•
•
+13 MHz
–13 MHz
5th-order Elliptic LPF with 200-kHz cutoff
implemented as SCF; dissipates 15 mW from 3V at 5 MHz sample rate. Operates up to 20 MHz.
60 dB stopband attenuation.
+13 MHz
0
LPF sets noise bandwidth of entire system
-120
0
Frequency, kHz
1000
Lowpass Channel-Select Filter
Downconverted Spectrum
LPF Response
–13 MHz
230 kHz
24dB
50dB at
13 MHz
320 kHz
fRF/64
0dB
2nd-Order Butterworth Prefilter
915 MHz
+13 MHz
620 kHz
fRF/16
>40 dB
Downconvert
+13 MHz
26 MHz
–13 MHz
50 dB
6th-Order Elliptic
Channel Filter
LNA
BQ1
Q = 0.65
Gain = 4
BQ2
Q = 8.1
Gain = 4
BQ3
Q = 1.9
Gain = 1
Measured Filter Performance
· 70 nV/Hz in passband
· 4.6 mA from 3V
· 200 pF total on-chip
capacitance
Digital Tone Detector
I&D
|A|+|B|
coswt
(1b)
Max
Select
I&D
|A|+|B|
I&D
|A|+|B|
sinwt
(1b)
MUX
I&D
|A|+|B|
•
1-bit oversampled correlator (programmable oversample rate)
•
Multipliers are switches, integrators are accumulators
•
1.9 sq mm active area implementation will dissipate 2 mW
MSB
9b
Rationale Underlying UCLA
Low-Power Transceiver
• Radio paging receiver is the most evolved low-energy wireless device
today. Receives 500 to 1000 b/s at 400 MHz to 900 MHz.
• Long battery life obtained through very high level of integration (two
chips) and optimized system design
• UCLA transceiver uses this as a model. Key extensions are:
✓ Two-way communication
✓ Much higher data rate ➭160 kb/s (programmable)
✓ Robust operation in multipath environment ➭ Diversity
✓ Large multi-user capacity ➭ CDMA spread-spectrum
Features ♦ Binary FSK modulation of carrier (like pager)
♦ Frequency-hopped spread-spectrum
♦ Simple demodulation after de-hopping (like pager)
♦ Two-chip transceiver (like paging receiver)
New Technology for Etching Inductors
Need fast etchant in p+ doped substrates
Should minimally etch exposed metallization
Xenon DiFluoride (XeF2) gasphase etchant
• Etches hemispherical pits
anisotropically through array of small
holes in oxide
• Depth of etching may be visually
monitored through semi-transparent
nitride
1 GHz Continuous-Time LNA and Mixer
A demonstration of the fundamental capability of MOSFETs to attain
low noise and wide dynamic range, at low power
1-µm CMOS operating at 3V; matched to 50W at input
Drain 8 mA from 3V
M3
1000µm
VC
960µm
M10
3µm
50nH
IF+
M1
300µm
RF In+
IF–
M2
M6
VG
LO–
M9
LO+
LO+
RF In–
300µm
RF+
M4
80µm
RF–
M5
LNA Design Rationale
Gain= Q2Rs ¥ gm
F
1
50W I F w I
=
ªG
JG J
( w C) R ¥ 50W H R K H w K
2
T
2
0
s
s
0
Measured fT vs VGS-Vt
5
50 nH on-chip inductor load
4
Rs . 50V
3
23 dB gain requires bias at (VGS–Vt)=0.6V
for sufficiently high fT
2
1
LNA + mixer drain 8 mA from 3 V
0.1
0.2
0.3
VGS-Vt, V
0.4
0.5
Channel-Select Filter
2nd-Order Butterworth Prefilter
LNA
6th-Order Elliptic
Channel Filter
0.5dB
230 kHz
620 kHz
>40 dB
12dB
24dB
54dB at
14 MHz
915 MHz
Current drain of active filter ~ 3.5 mA
Input-referred noise ~ 40 nV/!!Hz
Capacitor spread = 108
Input capacitor ~ 0.45 pF
Output compression point ~ 2 V ptp
320 kHz
50 dB
Increasing DDFS/DAC Clock Frequency
1
f5
f2
500µm
CM
f3
f3
100Ω
f4
+
–
–
+
(
Ω
+
–
CM
f2
1
f5
• Eliminate two clock phases, f4 and f5, in buffer driving
on-chip capacitive load
• Rescale DDFS. Carry-select adder in accumulator.
• Use open-loop buffer to drive polyphase filter through
four-FET switch upconversion mixers
• 3rd-order distortion, including buffer < —45 dB
600 µm
100 W
Polyphase Filter for Sideband Selection
I
~180˚
~270˚
600 W
0.3 pF
• Reinforces one sequence of quadrature phases
(clockwise, say), while attenuating the other
~0˚
Q
• Extension of the RC-CR phase-shift network,
with four-phase inputs and outputs
~90˚
• Robust against component mismatches (orderof-magnitude better than single-phase network)
Q
• Similarly selects one sideband after
upconversion (60 dB rejection with 10° phase
error in LO)
I
Image
Desired
90˚
I
LO
O Hz
Q
0˚
Image
LO
LO
+
–
Desired
Transmitter Test Chip
6×3.8 mm active area
65 mA active current
Transmitter Output Spectra
No off-chip filter at power amplifier output
Measurements at mid-range level +5 dBm
Current Drain in Transceiver Parts
0
30 mA
0
8 mA
8 mA
20 mA
+
–
7 mA PD
VCO 13 mA
Filt
÷32
14 mA
7 mA
Limiting Amplifier
Channel Filter
Limiting Amplifier
Channel Filter
2 mA
7 mA
15 mA
Measured Performance of Front-End
0
-2
-4
-6
-8
-10
-12
-14
-16
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Frequency, GHz