a Low Power Mixer 3 V Receiver IF Subsystem AD61009
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a FEATURES Complete Receiver-on-a-Chip: Monoceiver® Mixer –15 dBm 1 dB Compression Point –8 dBm Input Third Order Intercept 500 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB Gain Control Manual Gain Control Quadrature Demodulator On-Board Phase-Locked Quadrature Oscillator Demodulates IFs from 1 MHz to 12 MHz Can Also Demodulate AM, CW, SSB Low Power 25 mW at 3 V CMOS Compatible Power-Down APPLICATIONS GSM and TETRA Receivers Satellite Terminals Battery-Powered Communications Receivers GENERAL DESCRIPTION The AD61009 is a 3 V low power receiver IF subsystem for operation at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and Q demodulators, a phase-locked quadrature oscillator, and a biasing system with external power-down. The AD61009’s low noise, high intercept mixer is a doublybalanced Gilbert cell type. It has a nominal –15 dBm input referred 1 dB compression point and a –8 dBm input referred third-order intercept. The mixer section of the AD61009 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to –16 dBm. Low Power Mixer 3 V Receiver IF Subsystem AD61009 PIN CONFIGURATION 20-Lead SSOP (RS Suffix) FDIN 1 20 VPS1 COM1 2 19 FLTR PRUP 3 18 IOUT LOIP 4 17 QOUT AD61009 16 VPS2 TOP VIEW 15 DMIP (Not to Scale) 14 IFOP GREF 7 RFLO 5 RFHI 6 MXOP 8 13 COM2 VMID 9 12 GAIN IFHI 10 11 IFLO A quadrature VCO phase-locked to the IF drives the I and Q demodulators. The I and Q demodulators can also demodulate AM; when the AD61009’s quadrature VCO is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for AM. The VCO can also be phase-locked to an external beat-frequency oscillator (BFO), and the demodulator serves as a product detector for CW or SSB reception. Finally, the AD61009 can be used to demodulate BPSK using an external Costas Loop for carrier recovery. In MGC operation, the AD61009 accepts an external gaincontrol voltage input from an external AGC detector or a DAC. Monoceiver is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD61009–SPECIFICATIONS (@ T = 25ⴗC, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted) A Model Conditions Min AD61009ARS Typ Max Unit DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency Range Maximum Mixer Input Voltage Input 1 dB Compression Point Input Third-Order Intercept Noise Figure Maximum Output Voltage at MXOP Mixer Output Bandwidth at MXOP LO Drive Level LO Input Impedance Isolation, RF to IF Isolation, LO to IF Isolation, LO to RF Isolation, IF to RF IF AMPLIFIERS Noise Figure Input 1 dB Compression Point Output Third-Order Intercept Maximum IF Output Voltage at IFOP Output Resistance at IFOP Bandwidth GAIN CONTROL Gain Control Range Gain Scaling Gain Scaling Accuracy Bias Current at GAIN Bias Current at GREF Input Resistance at GAIN, GREF I AND Q DEMODULATORS Required DC Bias at DMIP Input Resistance at DMIP Input Bias Current at DMIP Maximum Input Voltage Amplitude Balance Quadrature Error Phase Noise in Degrees Demodulation Gain Maximum Output Voltage Output Offset Voltage Output Bandwidth PLL Required DC Bias at FDIN Input Resistance at FDIN Input Bias Current at FDIN Frequency Range Required Input Drive Level Acquisition Time to ± 3° POWER-DOWN INTERFACE Logical Threshold Input Current for Logical High Turn-On Response Time Standby Current For Conversion Gain > 20 dB For Linear Operation; Between RFHI and RFLO RF Input Terminated in 50 Ω RF Input Terminated in 50 Ω Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz ZIF = 165 Ω, at Input Compression –3 dB, ZIF = 165 Ω Mixer LO Input Terminated in 50 Ω LOIP to VMID RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 500 ± 54 –15 –5 14 12 ± 1.3 45 –16 1 30 20 40 70 MHz mV dBm dBm dB dB V MHz dBm kΩ dB dB dB dB Max Gain, f = 10.7 MHz IF = 10.7 MHz IF = 10.7 MHz ZIF = 600 Ω From IFOP to VMID –3 dB at IFOP, Max Gain 17 –15 18 ± 560 15 45 dB dBm dBm mV Ω MHz 90 20 75/VR ±1 5 1 1 dB mV/dB dB/V dB µA µA MΩ VPOS/2 50 2 ±150 ±75 ± 0.2 –1.2 –100 18 ±1.23 10 1.5 V dc kΩ µA mV mV dB Degrees dBc/Hz dB V mV MHz (See Figures 10 and 11) Mixer + IF Section, GREF to 1.5 V GREF to 1.5 V GREF to General Reference Voltage VR GREF to 1.5 V, 80 dB Span From DMIP to VMID IF > 3 MHz IF ≤ 3 MHz IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz IF = 10.7 MHz, F = 10 kHz Sine Wave Input, Baseband Output RL ≥ 20 kΩ Measured from IOUT, QOUT to VMID Sine Wave Input, Baseband Output 17.4 –100 From FDIN to VMID Sine Wave Input at Pin 1 IF = 10.7 MHz For Power Up on Logical High To PLL Locked POWER SUPPLY Supply Range Supply Current OPERATING TEMPERATURE TMIN to TMAX –3.5 +100 V dc kΩ nA MHz mV µs 2 75 16.5 550 V dc µA µs µA 8.5 –25 –40 18.8 VPOS/2 50 200 1.0 to 12 400 16.5 2.85 Operation to 2.85 V Minimum Supply Voltage Operation to 4.5 V Minimum Supply Voltage +1.5 5.5 12.5 V mA +85 +85 °C °C Specifications subject to change without notice. –2– REV. 0 AD61009 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 20-lead SSOP Package: θJA = 126°C/W. Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . 5.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW 2.7 V to 5.5 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C 4.5 V to 5.5 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD61009 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Description Package Option AD61009ARS –25°C to +85°C for 2.7 V to 5.5 V Operation; –40°C to +85°C for 4.5 V to 5.5 V Operation 20-Lead Plastic SSOP RS-20 REV. 0 –3– AD61009 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Reads Function 1 FDIN Frequency Detector Input 2 3 COM1 PRUP Common #1 Power-Up Input 4 LOIP Local Oscillator Input 5 6 7 8 RFLO RFHI GREF MXOP RF “Low” Input RF “High” Input Gain Reference Input Mixer Output 9 10 11 12 VMID IFHI IFLO GAIN Midsupply Bias Voltage IF “High” Input IF “Low” Voltage Gain Control Input 13 14 COM2 IFOP Common #2 IF Output 15 DMIP Demodulator Input 16 17 VPS2 QOUT VPOS Supply #2 Quadrature Output 18 IOUT In-Phase Output 19 20 FLTR VPS1 PLL Loop Filter VPOS Supply #1 PLL input for I/Q demodulator quadrature oscillator, ± 400 mV drive required from external oscillator. Must be biased at VP/2. Supply common for RF front end and main bias. 3 V/5 V CMOS compatible power-up control; logical high = powered-up; max input level = VPS1 = VPS2. LO input, ac coupled ± 54 mV LO input required (–16 dBm for 50 Ω input termination). Usually connected to ac ground. AC coupled, ± 56 mV, max RF input for linear operation. High impedance input, typically 1.5 V, sets gain scaling. High impedance, single-sided current output, ± 1.3 V max voltage output (± 6 mA max current output). Output of the midsupply bias generator (VMID = VPOS/2). AC coupled IF input, ± 56 mV max input for linear operation. Reference node for IF input; auto-offset null. High impedance input, 0 V–2 V using 3 V supply, max gain at V = 0. Supply common for IF stages and demodulator. Low impedance, single-sided voltage output, 5 dBm (± 560 mV) max. Signal input to I and Q demodulators ± 150 mV max input at IF > 3 MHz for linear operation; ± 75 mV max input at IF < 3 MHz for linear operation. Must be biased at VP/2. Supply to high-level IF, PLL, and demodulators. Low impedance Q baseband output; ± 1.23 V full scale in 20 kΩ min load; ac coupled. Low impedance I baseband output; ± 1.23 V full scale in 20 kΩ min load; ac coupled. Series RC PLL Loop filter, connected to ground. Supply to mixer, low level IF, PLL, and gain control. PIN CONNECTION 20-Lead SSOP (RS-20) FDIN 1 20 VPS1 COM1 2 19 FLTR PRUP 3 18 IOUT LOIP 4 17 QOUT AD61009 16 VPS2 TOP VIEW 15 DMIP (Not to Scale) 14 IFOP GREF 7 RFLO 5 RFHI 6 MXOP 8 13 COM2 VMID 9 12 GAIN IFHI 10 11 IFLO –4– REV. 0 Typical Performance Characteristics–AD61009 50⍀ HP8764B HP8656B IEEE 0 RF_OUT SYNTHESIZER 1 HP8656B 0 S1 RF_OUT IEEE S0 1 50⍀ SYNTHESIZER V RFHI 0 1 0 X R S1 IFHI P6205 TEK1105 OUT IN1 OUT1 FET PROBE IFOP X10 VPOS 0 VNEG IEEE IN2 SPOS DMIP SNEG DCPS FDIN HP34401A VPOS I R5 PRUP 1k⍀ GAIN DP8200 VPOS IEEE HP8765B C S0 V S1 PLL QOUT LO DMM V 1 OUT2 PROBE SUPPLY IOUT HI CPIB 1 50⍀ LOIP HP6633A S0 MXOP L HP8656B RF_OUT IEEE SYNTHESIZER HP8764B 50⍀ CHARACTERIZATION BOARD VNEG SPOS 0 SNEG 1 V REF BIAS HP8765B C S0 V S1 TPC 1. Mixer/Amplifier Test Set HP8720C PORT_1 IEEE_488 PORT_2 NETWORK AN 0 HP346B 28V CHARACTERIZATION BOARD HP8765B HP8765B NOISE SOURCE C RFHI X R S0 V S1 MXOP C 1 S1 V S0 L HP8656B RF_OUT IEEE SYNTHESIZER LOIP IFHI IFOP IOUT DMIP FDIN PLL QOUT HP6633A VPOS IEEE VPOS VNEG PRUP SPOS GAIN BIAS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS V REF SNEG TPC 2. Mixer Noise Figure Test Set REV. 0 0 50⍀ HP8970A NOISE 1 –5– RF_IN 28V_OUT NOISE FIGURE METER HP8594E RF_IN IEEE SPEC AN AD61009 CHARACTERIZATION BOARD RFHI X R MXOP L LOIP HP346B 28V P6205 IFHI NOISE IFOP X10 FET OUT IN1 PROBE TEK1103 OUT1 28V_OUT NOISE FIGURE METER NOISE SOURCE IN2 OUT2 PROBE SUPPLY DMIP FDIN HP8970A RF_IN IOUT PLL QOUT HP6633A VPOS VPOS IEEE VNEG PRUP SPOS GAIN BIAS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS V REF SNEG TPC 3. IF Amp Noise Figure Test Set CHARACTERIZATION BOARD 50⍀ HP8764B RFHI 0 HP8656B IEEE X R MXOP L 1 0 RF_OUT SYNTHESIZER S0 LOIP S1 50⍀ 1 IFHI IFOP DMIP IOUT V HP3326A DCFM OUTPUT_1 IEEE OUTPUT_2 DUAL SYNTHESIZER P6205 FDIN QOUT VPOS IEEE VPOS VNEG PRUP SPOS GAIN BIAS OUT IN1 1103 OUT1 FET PROBE PLL HP6633A X10 P6205 OUT IN2 OUT2 X10 PROBE FET PROBE SUPPLY 0 HP8765B 1 HP8765B 0 C S0 V S1 C HP8694E RF_IN IEEE 1 SPEC AN S1 V S0 HP54120 CH1 SNEG CH2 DCPS CH3 DP8200 CH4 VPOS TRIG VNEG IEEE IEEE_488 DIGITAL OSCILLOSCOPE SPOS SNEG V REF TPC 4. PLL/Demodulator Test Set –6– REV. 0 AD61009 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP6633A VPOS IFHI IFOP VNEG IEEE SPOS SNEG DCPS DP8200 FDIN VNEG IEEE IOUT DMIP VPOS PLL QOUT SPOS SNEG V REF VPOS R1 499k⍀ HP34401A HI GAIN LO I GPIB DMM BIAS PRUP TPC 5. GAIN Pin Bias Test Set CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP6633A VPOS IFHI IFOP DMIP IOUT VNEG IEEE SPOS SNEG DCPS DP8200 VPOS FDIN VNEG IEEE PLL QOUT SPOS SNEG VPOS V REF R1 499k⍀ HP34401A BIAS PRUP HI GPIB DMM GAIN LO I TPC 6. Demodulator Bias Test Set CHARACTERIZATION BOARD HP3325B IEEE RFHI RF_OUT SYNTHESIZER MXOP R X L LOIP HP6633A VPOS HP8594E IFHI VNEG IEEE IFOP SPOS SPEC AN SNEG DCPS HP6633A DMIP VPOS FDIN VNEG IEEE IOUT PLL QOUT SPOS SNEG DCPS VPOS R1 10k⍀ HP34401A GAIN LO DMM BIAS PRUP HI GPIB I TPC 7. Power-Up Threshold Test Set REV. 0 RF_IN –7– IEEE AD61009 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP IFHI FL6082A RF_OUT IEEE MOD_OUT X10 IOUT DMIP FDIN 1103 P6205 IFOP 50⍀ OUT IN1 CH1 CH2 CH3 CH4 TRIG IEEE_488 DIGITAL OSCILLOSCOPE PLL QOUT HP6633A VPOS VPOS IEEE HP54120 OUT1 FET PROBE P6205 OUT IN2 OUT2 X10 PROBE SUPPLY FET PROBE VNEG PRUP SPOS GAIN NOTE: MUST BE 3 RESISTOR POWER DIVIDER BIAS SNEG DCPS DP8200 VPOS VNEG IEEE SPOS V REF SNEG HP8112 IEEE PULSE_OUT PULSE GENERATOR TPC 8. Power-Up Test Set CHARACTERIZATION BOARD RFHI MXOP R X L LOIP HP8656B IEEE RF_OUT IFHI P6205 IFOP X10 R1 1k⍀ SYNTHESIZER HP8594E 1103 OUT IN1 OUT1 FET PROBE RF_IN IEEE SPEC AN IN2 OUT2 PROBE SUPPLY IOUT DMIP FDIN PLL QOUT HP6633A VPOS IEEE VPOS VNEG PRUP SPOS GAIN BIAS SNEG DCPS TPC 9. IF Output Impedance Test Set –8– REV. 0 AD61009 CHARACTERIZATION BOARD RFHI MXOP R X L LOIP IFHI IFOP 20⍀ dB HP54120 P6205 FL6082A DMIP RF_OUT IEEE IOUT FDIN X10 QOUT X10 HP6633A VPOS VPOS IEEE VNEG PRUP SPOS GAIN OUT IN1 OUT1 CH1 CH2 FET PROBE P6205 PLL MOD_OUT 1103 FET PROBE BIAS CH3 OUT IN2 OUT2 CH4 TRIG PROBE SUPPLY IEEE_488 DIGITAL OSCILLOSCOPE SNEG DCPS DP8200 VPOS VNEG IEEE SPOS V REF SNEG TPC 10. PLL Settling Time Test Set CHARACTERIZATION BOARD RFHI HP3325B IEEE MXOP R X L LOIP RF_OUT SYNTHESIZER IFHI IFOP DMIP IOUT HP3326 DCFM OUTPUT_1 IEEE OUTPUT_2 DUAL SYNTHESIZER P6205 FDIN PLL QOUT VPOS VPOS VNEG PRUP SPOS GAIN 1103 OUT IN1 0 OUT IN2 FET PROBE BIAS OUT1 FET PROBE P6205 X10 HP6633A IEEE X10 OUT2 PROBE SUPPLY SNEG DCPS DP8200 VPOS VNEG IEEE SPOS SNEG V REF TPC 11. Quadrature Accuracy Test Set REV. 0 –9– HP8765B HP8694E 1 C S0 V S1 RF_IN IEEE SPEC AN AD61009 VPOS C15 0.1F GND C11 10nF FDIN 4.99k⍀ R10 0.1F C13 0.1F C1 R8 51.1⍀ 0⍀ R12 PRUP C10 1nF LOIP R7 51.1⍀ C9 1nF RFHI MXOP * IFHI C16 1nF R6 51.1⍀ R13 301⍀ 1 FDIN VPS1 20 2 COM1 FLTR 19 3 PRUP IOUT 18 4 LOIP QOUT 17 AD61009 5 RFLO 6 RFHI DMIP 15 7 GREF IFOP 14 8 MXOP COM2 13 9 VMID GAIN 12 10 IFHI R14 54.9⍀ R5 332⍀ R9 51.1⍀ VPS2 16 R1 1k⍀ IOUT 0.1F C2 * QOUT * R2 316⍀ IFOP * IFLO 11 C6 0.1F C7 1nF C3 10nF C8 0.1F C5 1nF GAIN * DMIP * 0.1F NOTE: CONNECTIONS MARKED * ARE DC COUPLED. TPC 12. Characterization Board –10– REV. 0 AD61009 30 20 19 VGAIN = 0.3V 25 18 16 20 CONVERSION GAIN – dB SSB NF – dB 17 VPOS = 5V, IF = 20MHz 15 VPOS = 3V, IF = 20MHz 14 13 VGAIN = 0.6V 15 10 VGAIN = 1.2V 5 VGAIN = 1.8V 0 VGAIN = 2.4V 12 11 10 50 –5 VPOS = 5V, IF = 10MHz 70 90 VPOS = 3V, IF = 10MHz 110 130 150 170 190 RF FREQUENCY – MHz 210 230 –10 0.1 250 4500 4.0 4000 3.5 80 70 CUBIC FIT OF IF_GAIN (TEMP) 60 2.5 2500 2.0 2000 1.5 1500 R SHUNT COMPONENT 1.0 1000 IF AMP GAIN 50 40 GAIN – dB C SHUNT COMPONENT 3000 3.0 CAPACITANCE – pF 3500 30 20 10 CUBIC FIT OF CONV_GAIN (TEMP) MIXER CG 0 0.5 500 0 0 50 100 150 200 250 300 350 400 450 –10 0 500 –20 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TEMPERATURE – ⴗC FREQUENCY – MHz TPC 14. Mixer Input Impedance vs. Frequency, VPOS = 3 V, V GAIN = 0.8 V TPC 17. Mixer Conversion Gain and IF Amplifier Gain vs. Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz 80 30 25 VGAIN = 0.00V 70 VGAIN = 0.54V 20 CUBIC FIT OF IF_GAIN (VPOS) IF AMP GAIN 60 15 10 VGAIN = 1.62V 5 GAIN – dB CONVERSION GAIN – dB 100 10 TPC 16. Mixer Conversion Gain vs. IF, T = 25 °C, VPOS = 3 V, VREF = 1.5 V TPC 13. Mixer Noise Figure vs. Frequency RESISTANCE – ⍀ 1 INTERMEDIATE FREQUENCY – MHz VGAIN = 1.08V 0 –5 50 40 CUBIC FIT OF CONV_GAIN (VPOS) 30 –10 VGAIN = 2.16V –15 20 10 –20 0 REV. 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 SUPPLY – Volts RADIO FREQUENCY – MHz TPC 15. Mixer Conversion Gain vs. Frequency, T = 25 °C, VPOS = 2.7 V, VREF = 1.35 V, IF = 10.7 MHz MIXER CG 2.4 2.6 2.8 50 100 150 200 250 300 350 400 450 500 550 600 TPC 18. Mixer Conversion Gain and IF Amplifier Gain vs. Supply Voltage, T = 25 °C, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz –11– AD61009 –90.00 80 VGAIN = 0.3V 70 –100.00 VGAIN = 0.6V PHASE NOISE – dBc IF AMPLIFIER GAIN – dB 60 50 VGAIN = 1.2V 40 30 VGAIN = 1.8V 20 –110.00 –120.00 –130.00 10 VGAIN = 2.4V –140.00 0 –150.00 –10 0.1 1 10 100 1.00E+02 INTERMEDIATE FREQUENCY – MHz 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 CARRIER FREQUENCY OFFSET, f(fm) – Hz TPC 19. IF Amplifier Gain vs. Frequency, T = 25 °C, VPOS = 3 V, VREF = 1.5 V TPC 22. PLL Phase Noise L (F) vs. Frequency, VPOS = 3 V, C3 = 0.1 µ F, IF = 10.7 MHz 2.5 10 8 FLTR PIN VOLTAGE – Volts 6 IF AMP ERROR – dB 4 2 0 –2 MIXER –4 2 –6 –8 1.5 0.1 –10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 1 10 100 PLL FREQUENCY – MHz GAIN VOLTAGE – Volts TPC 20. Gain Error vs. Gain Control Voltage, Representative Part TPC 23. PLL Loop Voltage at FLTR (KVCO) vs. Frequency 8 7 6 COUNT 5 4 3 2 996.200s 1.00870ms 1.02120ms TIMEBASE = 2.5s/DIV DELAY MEMORY 1 = 100.0mV/DIV OFFSET = 127.3mV TIMEBASE = 2.50s/DIV DELAY MEMORY 2 = 20.00mV/DIV OFFSET = 155.2mV TIMEBASE = 2.50s/DIV DELAY = 1.00870ms STOP = 1.01700ms DELTA T = 16.5199s START = 1.00048ms = 1.00870ms 1 = 1.00870ms 0 85 86 87 88 89 90 91 92 93 QUADRATURE ANGLE – Degrees 94 95 TRIGGER ON EXTERNAL AT POS. EDGE AT 134.0mV TPC 21. PLL Acquisition Time TPC 24. Demodulator Quadrature Angle, Histogram, T = 25 °C, VPOS = 3 V, IF = 10.7 MHz –12– REV. 0 AD61009 20 30 I_GAIN_CORR 19 25 18 17 IGAIN – dB COUNT 20 15 10 CUBIC FIT OF I_GAIN_CORR (TEMP) 16 15 14 13 12 5 11 10 0 –2 –1 0 1 IQ GAIN BALANCE – dB 2.5 2 3.5 3 4 4.5 SUPPLY – Volts 5 5.5 6 TPC 28. Demodulator Gain vs. Supply Voltage TPC 25. Demodulator Gain Balance, Histogram, T = 25 °C, VPOS = 3 V, IF = 10.7 MHz 40 20 19 35 18 30 17 25 16 COUNT IGAIN – dB I_GAIN_CORR 15 QUADRATIC FIT OF I_GAIN_CORR (IFF) 14 20 15 13 10 12 5 11 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 17 17.2 17.4 17.6 BASEBAND FREQUENCY – MHz 17.8 18 18.2 18.4 18.6 18.8 DEMODULATOR GAIN – dB TPC 26. Demodulator Gain vs. Frequency TPC 29. Demodulator Gain Histogram, T = 25 °C, VPOS = 3 V, IF = 10.7 MHz 20 I_GAIN_CORR 19 18 17 IGAIN – dB CUBIC FIT OF I_GAIN_CORR (TEMP) 16 15 14 13 40.2127ms 12 11 10 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 TEMPERATURE – ⴗC 40.2377ms 40.2627ms TIMEBASE = 500s/DIV DELAY MEMORY 1 = 100.0mV/DIV OFFSET = 154.0mV TIMEBASE = 5.00s/DIV DELAY MEMORY 2 = 60.00mV/DIV OFFSET = 209.0mV TIMEBASE = 5.00s/DIV DELAY = 40.2377ms STOP = 40.2485ms DELTA T = 15.7990s START = 40.2327ms = 40.2377ms = 40.2377ms TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV TPC 27. Demodulator Gain vs. Temperature REV. 0 TPC 30. Power-Up Response Time to PLL Stable –13– AD61009 Mixer SUPPLY CURRENT – mA 15 The UHF mixer is an improved Gilbert cell design, and can operate from low frequencies (it is internally dc-coupled) up to an RF input of 500 MHz. The dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of ± 56 mV between RFHI and RFLO up to which the mixer remains linear, and, at the lower end, by the noise level. It is customary to define the linearity of a mixer in terms of the 1 dB gain-compression point and third-order intercept, which for the AD61009 are –15 dBm and –8 dBm, respectively, in a 50 Ω system. 10 The mixer’s RF input port is differential, that is, pin RFLO is functionally identical to RFHI, and these nodes are internally biased; we will generally assume that RFLO is decoupled to ac ground. The RF port can be modeled as a parallel RC circuit as shown in Figure 2. 5 0 0.5 1 1.5 GAIN VOLTAGE – Volts 2 2.5 TPC 31. Power Supply Current vs. Gain Control Voltage, GREF = 1.5 V AD61009 PRODUCT OVERVIEW The AD61009 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne receiver, or most of a double-conversion receiver, at input frequencies up to 500 MHz, and with an IF of from 400 kHz to 12 MHz. The internal I/Q demodulators, and their associated phase locked-loop, which can provide carrier recovery from the IF, support a wide variety of modulation modes, including n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V is required (2.85 V minimum, 5.5 V maximum) at a typical supply current of 8.5 mA at midgain. In the following discussion, VP will be used to denote the power supply voltage, which will be assumed to be 3 V. C1 C2 RFHI CIN L1 RIN RFLO C3 C1, C2, L1: OPTIONAL MATCHING CIRCUIT C3: COUPLES RFLO TO AC GROUND Figure 2. Mixer Port Modeled as a Parallel RC Network; an Optional Matching Network Is also Shown Figure 1 shows the main sections of the AD61009. It consists of a variable-gain UHF mixer and linear four-stage IF strip, which together provide a voltage controlled gain range of more than 90 dB; followed by dual demodulators, each comprising a multiplier followed by a two-pole, 2 MHz low-pass filter; and driven by a phase-locked loop providing the inphase and quadrature clocks. A biasing system with CMOS compatible power-down completes the AD61009. The local oscillator (LO) input is internally biased at VP/2 via a nominal 1000 Ω resistor internally connected from pin LOIP to VMID. The LO interface includes a preamplifier which minimizes the drive requirements, thus simplifying the oscillator design and reducing LO leakage from the RF port. Internally, this single-sided input is actually differential; the noninverting input is referenced to pin VMID. The LO requires a single-sided drive of ± 50 mV, or –16 dBm in a 50 Ω system. LOIP RFHI VMID IOUT IFHI MXOP BPF IFOP RFLO BPF OR LPF FDIN DMIP VQFO FLTR VMID IFLO QOUT MIDPOINT BIAS GENERATOR GAIN VPS1 VPS2 BIAS GENERATOR PTAT VOLTAGE AD61009 GREF PRUP COM1 COM2 Figure 1. Functional Block Diagram –14– REV. 0 AD61009 The mixer’s output passes through both a low-pass filter and a buffer, which provides an internal differential to single-ended signal conversion with a bandwidth of approximately 45 MHz. Its output at pin MXOP is in the form of a single-ended current. This approach eliminates the 6 dB voltage loss of the usual series termination by replacing it with shunt terminations at the both the input and the output of the filter. The nominal conversion gain is specified for operation into a total IF bandpass filter (BPF) load of 165 Ω, that is, a 330 Ω filter, doubly-terminated as shown in Figure 33. Note that these loads are connected to bias point VMID, which is always at the midpoint of the supply (that is, VP/2). The maximum permissible signal level at MXOP is determined by both voltage and current limitations. Using a 3 V supply and VMID at 1.5 V, the maximum swing is about ± 1.3 V. To attain a voltage swing of ± 1 V in the standard IF filter load of 165 Ω load requires a peak drive current of about ± 6 mA, which is well within the linear capability of the mixer. However, these upper limits for voltage and current should not be confused with issues related to the mixer gain, already discussed. In an operational system, the AGC voltage will determine the mixer gain, and hence the signal level at the IF input pin IFHI; it will always be less than ± 56 mV (–15 dBm into 50 Ω), which is the limit of the IF amplifier’s linear range. The conversion gain is measured between the mixer input and the input of this filter, and varies between 1.5 dB and 26.5 dB for a 165 Ω load impedance. Using filters of higher impedance, the conversion gain can always be maintained at its specified value or made even higher; for filters of lower impedance, of say ZO, the conversion gain will be lowered by 10 log10(165/ZO). Thus, the use of a 50 Ω filter will result in a conversion gain that is 5.2 dB lower. Figure 3 shows filter matching networks and Table I lists resistor values. IF Amplifier R2 MXOP 8 1nF BPF R1 VMID 10 IFHI R3 9 11 IFLO 100nF 100nF Most of the gain in the AD61009 arises in the IF amplifier strip, which comprises four stages. The first three are fully differential and each has a gain span of 25 dB for the nominal AGC voltage range. Thus, in conjunction with the mixer’s variable gain, the total gain exceeds 90 dB. The final IF stage has a fixed gain of 20 dB, and it also provides differential to single-ended conversion. The IF input is differential, at IFHI (noninverting relative to the output IFOP) and IFLO (inverting). Figure 4 shows a simplified schematic of the IF interface. The offset voltage of this stage would cause a large dc output error at high gain, so it is nulled by a low-pass feedback path from the IF output, also shown in TPC 25. Unlike the mixer output, the signal at IFOP is a lowimpedance single-sided voltage, centered at VP/2 by the dc feedback loop. It may be loaded by a resistance as low as 50 Ω, which will normally be connected to VMID. AD61009 IFHI Figure 3. Suggested IF Filter Matching Network. The Values of R1 and R2 Are Selected to Keep the Impedance at Pin MXOP at 165 Ω 10k⍀ VMID IFOP IFLO Table I. AD61009 Filter Termination Resistor Values for Common IFs IF 450 kHz 455 kHz 6.5 MHz 10.7 MHz Filter Impedance Filter Termination Resistor Values1 for 24 dB of Mixer Gain 1500 Ω 1500 Ω 1000 Ω 330 Ω R1 174 Ω 174 Ω 215 Ω 330 Ω R2 1330 Ω 1330 Ω 787 Ω 0Ω NOTE 1 Resistor values were calculated such that R1 + R2 = Z FILTER and R1储 (R2 + ZFILTER) = 165 Ω. REV. 0 R3 1500 Ω 1500 Ω 1000 Ω 330 Ω 10k⍀ OFFSET FEEDBACK LOOP Figure 4. Simplified Schematic of the IF Interface The IF’s small-signal bandwidth is approximately 45 MHz from IFHI and IFLO through IFOP. The peak output at IFOP is ± 560 mV at VP = 3 V and ± 400 mV at the minimum VP of 2.7 V. This allows some headroom at the demodulator inputs (pin DMIP), which accept a maximum input of ± 150 mV for IFs > 3 MHz and ± 75 mV for IFs ≤ 3 MHz (at IFs ≤ 3 MHz, the drive to the demodulators must be reduced to avoid saturating the output amplifiers with higher order mixing products that are no longer removed by the onboard low-pass filters). –15– AD61009 Since there is no band-limiting in the IF strip, the outputreferred noise can be quite high; in a typical application and at a gain of 75 dB it is about 100 mV rms, making post-IF filtering desirable. IFOP may be also used as an IF output for driving an A/D converter, external demodulator, or external AGC detector. Figure 5 shows methods of matching the optional second IF filter. VPOS AD61009 2RT RT IFOP BPF 2RT DMIP a. Biasing DMIP from Power Supply (Assumes BPF AC Coupled Internally) AD61009 Alternatively, pin GREF can be tied to an external voltage reference, VR, provided, for example, by an AD1582 (2.5 V) or AD1580 (1.21 V) voltage reference, to provide supplyindependent gain scaling of VR/75 (volts per dB). Since it uses the same reference voltage, the numerical input to this DAC provides an accurate RSSI value in digital form, no longer requiring the reference voltage to have high absolute accuracy. I/Q Demodulators RT IFOP AD61009 features temperature-compensation of the gain scaling. The gain control scaling is proportional to the reference voltage applied to the pin GREF. When this pin is tied to the midpoint of the supply (VMID), the scale is nominally 20 mV/ dB (50 dB/V) for VP = 3 V. Under these conditions, the lower 80 dB of gain range (mixer plus IF) corresponds to a control voltage of 0.4 V ≤ VG ≤ 2.0 V. The final centering of this 1.6 V range depends on the insertion losses of the IF filters used. More generally, the gain scaling using these connections is VP/150 (volts per dB), so becomes 33.3 mV/dB (30 dB/V) using a 5 V supply, with a proportional change in the AGC range, to 0.33 V ≤ VG ≤ 3 V, Table II lists gain control voltages and scale factors for power supply voltages from 3 V to 5.5 V. BPF DMIP RT VMID CBYPASS b. Biasing DMIP from VMID (Assumes BPF AC Coupled Internally) Figure 5. Input and Output Matching of the Optional Second IF Filter Gain Scaling and RSSI The AD61009’s overall gain, expressed in decibels, is linearin-dB with respect to the AGC voltage VG at pin GAIN. The gain of all sections is maximum when VG is zero, and reduces progressively up to VG = 2.2 V (for VP = 3 V; in general, up to a limit VP – 0.8 V). The gain of all stages changes in parallel. The Both demodulators (I and Q) receive their inputs at pin DMIP. Internally, this single-sided input is actually differential; the noninverting input is referenced to pin VMID. Each demodulator comprises a full-wave synchronous detector followed by a 2 MHz, two-pole low-pass filter, producing single-sided outputs at pins IOUT and QOT. Using the I and Q demodulators for IFs above 12 MHz is precluded by the 1 MHz to 12 MHz response of the PLL used in the demodulator section. Pin DMIP requires an external bias source at VP/2; Figure 6 shows suggested methods. Outputs IOUT and QOUT are centered at VP/2 and can swing up to ± 1.23 V even at the low supply voltage of 2.85 V. The conversion gain of the I and Q demodulators is 18 dB (X8), requiring a maximum input amplitude at DMIP of ± 150 mV for IFs > 3 MHz. Table II. AD61009 Gain and Manual Gain Control Voltage vs. Power Supply Voltage Power Supply Voltage (V) GREF (= VMID) (V) Scale Factor (dB/V) Scale Factor (mV/dB) Gain Control Voltage Input Range (V) 3.0 3.5 4.0 4.5 5.0 5.5 1.5 1.75 2.0 2.25 2.5 2.75 50.00 42.86 37.50 33.33 30.00 27.27 20.00 23.33 26.67 30.00 33.33 36.67 0.400–2.000 0.467–2.333 0.533–2.667 0.600–3.000 0.667–3.333 0.733–3.667 NOTE Maximum gain occurs for gain control voltage = 0 V. –16– REV. 0 AD61009 The reference signal may be provided from an external source, in the form of a high-level clock, typically a low level signal (± 400 mV) since there is an input amplifier between FDIN and the loop’s phase detector. For example, the IF output itself can be used by connecting DMIP to FDIN, which will then provide automatic carrier recover for synchronous AM detection and take advantage of any post-IF filtering. Pin FDIN must be biased at VP/2; Figure 9 shows suggested methods. VPOS AD61009 2RT RT IFOP BPF 2RT DMIP a. Biasing DMIP from Power Supply (Assumes BPF AC-Coupled Internally) AD61009 IFOP RT BPF In practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. This is typically 16.5 µs at an IF of 10.7 MHz for a ±100 mV signal at DMIP and FDIN. DMIP RT VMID The VFQO operates from 1 MHz to 12 MHz and is controlled by the voltage between VPOS and FLTR. In normal operation, a series RC network, forming the PLL loop filter, is connected from FLTR to ground. The use of an integral sample-hold system ensures that the frequency-control voltage on pin FLTR remains held during power-down, so reacquisition of the carrier typically occurs in 16.5 µs. CBYPASS Bias System b. Biasing DMIP from VMID (Assumes BPF AC-Coupled Internally) Figure 6. Suggested Methods for Biasing Pin DMIP at VP /2 For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff) do not attenuate the IF or feedthrough products; thus, the maximum input voltage at DMIP must be limited to ± 75 mV to allow sufficient headroom at the I and Q outputs for not only the desired baseband signal but also the unattenuated higherorder demodulation products. These products can be removed by an external low-pass filter. Phase-Locked Loop The demodulators are driven by quadrature signals that are provided by a variable frequency quadrature oscillator (VFQO), phase locked to a reference signal applied to pin FDIN. When this signal is at the IF, inphase and quadrature baseband outputs are generated at IOUT and QOUT, respectively. The quadrature accuracy of this VFQO is typically –1.2° at 10.7 MHz. The PLL uses a sequential-phase detector that comprises low power emitter-coupled logic and a charge pump (Figure 7). The AD61009 operates from a single supply, VP, usually of 3 V, at a typical supply current of 8.5 mA at midgain and T = 27°C, corresponding to a power consumption of 25 mW. Any voltage from 2.85 V to 5.5 V may be used. The bias system includes a fast-acting active-high CMOScompatible power-up switch, allowing the part to idle at 550 µA when disabled. Biasing is proportional-to-absolute-temperature (PTAT) to ensure stable gain with temperature. An independent regulator generates a voltage at the midpoint of the supply (VP/2) which appears at the VMID pin, at a low impedance. This voltage does not shut down, ensuring that the major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators) remain biased at all times, thus minimizing transient disturbances at power-up and allowing the use of substantial decoupling capacitors on this node. The quiescent consumption of this regulator is included in the idling current. VPOS FDIN EXTERNAL FREQUENCY REFERENCE VF R SEQUENTIAL PHASE DETECTOR U D C ID~ 40A 50k⍀ a. Biasing FDIN from Supply when Using External Frequency Reference IU~ 40A F AD61009 50k⍀ R I-CLOCK VARIABLEFREQUENCY QUADRATURE OSCILLATOR AD61009 90ⴗ FDIN EXTERNAL FREQUENCY REFERENCE Q-CLOCK (ECL OUTPUTS) 50k⍀ VMID CBYPASS REFERENCE CARRIER (FDIN AFTER LIMITING) Figure 7. Simplified Schematic of the PLL and Quadrature VCO b. Biasing FDIN from VMID when Using External Frequency Reference Figure 8. Suggested Methods for Biasing Pin FDIN at VP / 2 REV. 0 –17– AD61009 USING THE AD61009 90dB In this section, we will focus on a few areas of special importance and include a few general application tips. As is true of any wideband high gain component, great care is needed in PC board layout. The location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling, particularly from IFOP to RFHI or IFHI or both. 80dB 70dB (67.5dB) 60dB IF GAIN 50dB The high sensitivity of the AD61009 leads to the possibility that unwanted local EM signals may have an effect on the performance. During system development, carefully-shielded test assemblies should be used. The best solution is to use a fully-enclosed box enclosing all components, with the minimum number of needed signal connectors (RF, LO, I and Q outputs) in miniature coax form. 40dB 30dB (21.5dB) 20dB MIXER GAIN 10dB (7.5dB) (1.5dB) 0dB 0.4V 0 The I and Q output leads can include small series resistors (about 100 Ω) inside the shielded box without significant loss of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 kΩ and capacitances of a few picofarads). These help to keep unwanted RF emanations out of the interior. 1.8V 1V NORMAL OPERATING RANGE 2.2V 2V Vg Figure 10. Gain Distribution for GREF = 1.5 V 90dB 80dB 70dB The power supply should be connected via a through-hole capacitor with a ferrite bead on both inside and outside leads. Close to the IC pins, two capacitors of different value should be used to decouple the main supply (VP) and the midpoint supply pin, VMID. Guidance on these matters is also generally included in applications schematics. (67.5dB) 60dB 50dB IF GAIN 40dB 30dB Gain Distribution (21.5dB) 20dB As in all receivers, the most critical decisions in effectively using the AD61009 relate to the partitioning of gain between the various subsections (Mixer, IF Amplifier, Demodulators) and the placement of filters, so as to achieve the highest overall signalto-noise ratio and lowest intermodulation distortion. MIXER GAIN 10dB (7.5dB) (1.5dB) 0dB 0 0.328V 1.64V 1V NORMAL OPERATING RANGE Figure 9 shows the main RF/IF signal path at maximum and minimum signal levels. 2V Vg Figure 11. Gain Distribution for GREF = 1.23 V As noted earlier, the gain in dB is reduced linearly with the voltage VG on the GAIN pin. Figure 10 shows how the mixer and IF strip gains vary with VG when GREF is connected to VMID (1.5 V) and a supply voltage of 3 V is used. Figure 11 shows how these vary when GREF is connected to a 1.23 V reference. I ⴞ54mV MAX INPUT ⴞ1.3V MAX OUTPUT RFHI MXOP ⴞ54mV MAX INPUT ⴞ560mV MAX OUTPUT IFOP IFHI IF BPF LOIP CONSTANT –16dBm (ⴞ50mV) 330⍀ 330⍀ (TYPICAL IMPEDANCE) ⴞ154mV MAX INPUT ⴞ1.23V MAX OUTPUT IOUT DMIP QOUT IF BPF (VMID) Q (LOCATION OF OPTIONAL SECOND IF FILTER) Figure 9. Signal Levels for Minimum and Maximum Gain –18– REV. 0 AD61009 Using the AD61009 with a Fast PRUP Control Signal If the AD61009 is used in a system in which the PRUP signal (Pin 3) is applied with a rise time less than 35 µs, anomalous behavior occasionally occurs. The problem is intermittent, so it will not occur every time the part is powered up under these conditions. It does not occur for any other normal operating conditions when the PRUP signal has a rise time slower than 35 µs. Symptoms of operation with too fast a PRUP signal include low gain, oscillations at the I or Q outputs of the device or no valid data occurring at the output of the AD61009. The problem causes no permanent damage to the AD61009, so it will often operate normally when reset. Fortunately, there is a very simple solution to the fast PRUP problem. If the PRUP signal (Pin 3) is slowed down so that the rise time of the signal edge is greater than 35 µs, the anomalous behavior will not occur. This can be realized by a simple RC circuit connected to the PRUP pin, where R = 4.7 kΩ and C = 1.5 nF. This circuit is shown in Figure 12. FROM PRUP CONTROL SIGNAL AD61009 4.7k⍀ PRUP 1.5nF All designs incorporating the AD61009 should include this circuitry. Note that connecting the PRUP pin to the supply voltage will not eliminate the problem since the supply voltage may have a rise time faster than 35 µs. With this configuration, the 4.7 kΩ series R and 1.5 nF shunt C should be placed between the supply and the PRUP pin as shown in Figure 12. AD61009 EVALUATION BOARD The AD61009 evaluation board (Figures 13 and 14) consists of an AD61009, ground plane, I/O connectors, and a 10.7 MHz bandpass filter. The RF and LO ports are terminated in 50 Ω to provide a broadband match to external signal generators to allow a choice of RF and LO input frequencies. The IF filter is at 10.7 MHz and has 330 Ω input and output terminations; the board is laid out to allow the user to substitute other filters for other IFs. The board provides SMA connectors for the RF and LO port inputs, the demodulated I and Q outputs, the manual gain control (MGC) input, the PLL input, and the power-up input. In addition, the IF output is also available at an SMA connector; this may be connected to the PLL input for carrier recovery to realize synchronous AM and FM detection via the I and Q demodulators, respectively. Table III lists the AD61009 Evaluation Board’s I/O Connectors and their functions. Figure 12. Proper Configuration of AD61009 PRUP Signal REV. 0 –19– AD61009 VPOS C15 0.1F GND JUMPER C11 10nF FDIN R8 51.1⍀ R11 OPEN C12 0.1F C1 0.1F FDIN COM1 R12 4.7k⍀ PRUP C13 0 C10 1nF VPS1 PRUP R7 51.1⍀ C14 0 R6 51.1⍀ 1k⍀ IOUT C17 1.5nF C16 1nF C9 1nF R5 RFLO JUMPER R4 OPEN 332⍀ R3 332⍀ C3 10nF R1 FLTR I QOUT LOIP LO RF R10 4.99k⍀ C20.1F AD61009 VPS2 RFHI DMIP GREF IFOP MXOP COM2 C4 47pF R2 316⍀ IF GAIN VMID IFHI Q C5 1nF IFLO GAIN C6 0.1F C7 1nF C8 0.1F AD607 EVALUATION BOARD (AS RECEIVED) VPOS R15 50k⍀ R13 50k⍀ C18 SHORT FDIN FDIN R14 51.1⍀ C17 10nF R12 OPEN VMID MOD FOR LARGE MAGNITUDE AC-COUPLED INPUT VPOS R17 OPEN R18 OPEN C19 ANYTHING FDIN FDIN R19 RSOURCE C20 SHORT R16 OPEN VMID MOD FOR DC-COUPLED INPUT Figure 13. Evaluation Board –20– REV. 0 AD61009 FDIN C15 J10 R8 PRUP R11 C1 R12 R1 C11 C17 C13 LOIP C12 R10 C10 R7 C16 C14 C9 R6 J9 C3 C3' U1 C2 R2 C4 R4 R5 C6 R3 C8 IFOP C7 RFHI FILT ANALOG DEVICES AD61009 EVALUATION BOARD REV B a. Topside IOUT R9 QOUT C5 GAIN b. Bottom Side Figure 14. Evaluation Board Layout REV. 0 –21– AD61009 Table III. AD61009 Evaluation Board Input and Output Connections Reference Designation Connector Type Description Coupling Approximate Signal Level J1 SMA Frequency Detector Input DC ± 400 mV J2 SMA Power Up DC J3 SMA LO Input AC J4 SMA RF Input AC J5 SMA MGC Input DC J6 SMA IF Output AC CMOS Logic Level Input –16 dBm (± 50 mV) –15 dBm max (± 54 mV) 0.4 V to 2.0 V (3 V Supply) (GREF = VMID) NA J7 SMA Q Output AC NA J8 SMA I Output AC NA J9 Jumper Ties GREF to VMID NA NA J10 Jumper NA NA T1 Terminal Pin DC DC T2 Terminal Pin Ties Power-Up to Positive Supply Power Supply Positive Input (VPS1, VPS2) Power Supply Return (GND) DC 0V –22– Comments This pin needs to be biased at VMID and ac coupled when driven by an external signal generator. Tied to Positive Supply by Jumper J10. Input is terminated in 50 Ω. Input is terminated in 50 Ω. Jumper is set for Manual Gain Control Input; See Table I for Control Voltage Values. This signal level depends on the AD61009’s gain setting. This signal level depends on the AD61009’s gain setting. This signal level depends on the AD61009’s gain setting. Sets gain-control Scale Factor (SF); SF = 75/VMID in dB/V, where VMID = VPOS/2. Remove to test Power-Up/-Down. 2.85 V to 5.5 V Draws 8.5 mA at midgain connection. REV. 0 AD61009 In operation (Figure 15), the AD61009 evaluation board draws about 8.5 mA at midgain (59 dB). Use high impedance probes to monitor signals from the demodulated I and Q outputs and the IF output. The MGC voltage should be set such that the signal level at DMIP does not exceed ± 150 mV; signal levels above this will overload the I and Q demodulators. The insertion loss between IFOP and DMIP is typically 3 dB if a simple low-pass filter (R8 and C2) is used and higher if a reverseterminated bandpass filter is used. HP 6632A PROGRAMMABLE POWER SUPPLY 2.7V–6V FLUKE 6082A SYNTHESIZED SIGNAL GENERATOR 240MHz MCL ZFSC–2–1 COMBINER HP 8656A SYNTHESIZED SIGNAL GENERATOR 240.02MHz HP 9920 IEEE CONTROLLER HP9121 DISK DRIVE HP 3326 SYNTHESIZED SIGNAL GENERATOR 10.710MHz VPOS RF FDIN I OUTPUT AD607 EVALUATION BOARD LO Q OUTPUT TEKTRONIX 11402A OSCILLOSCOPE WITH 11A32 PLUGIN MGC HP 8656A SYNTHESIZED SIGNAL GENERATOR 229.3MHz DATA PRECISION DVC8200 PROGRAMMABLE VOLTAGE SOURCE IEEE–488 BUS Figure 15. Evaluation Board Test Setup REV. 0 –23– AD61009 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic SSOP (RS-20) 11 1 10 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) BSC 8° SEATING 0.009 (0.229) 0° PLANE 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) PRINTED IN U.S.A. 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) C02347–0–1/01 (rev. 0) 20 0.212 (5.38) 0.205 (5.21) 0.311 (7.9) 0.301 (7.64) 0.295 (7.50) 0.271 (6.90) –24– REV. 0
