AN ABSTRACT OF THE THESIS OF
Tsung-Han Chiang for the degree of Master of Science in Electrical & Computer
Engineering presented on March 12, 2015.
Title: Investigation of Ultra-thin In-Ga-Zn-O Thin-Film Transistors
Abstract approved:
John F. Wager
The objective of the work reported herein is to explore the impact of decreasing channel layer thickness on radio-frequency (RF) sputtered amorphous indium gallium zinc
oxide (a-IGZO) thin-film transistors (TFTs) electrical performance through the evaluation of drain current versus gate voltage (ID −VG ) transfer curves. For a fixed set of
OF F
)
process parameters, it is found that the turn-on voltage, VON (off drain current, ID
increases (decreases) with decreasing a-IGZO channel layer thickness (h) for h < 11
nm. The VON − h trend is attributed to a large density (3.5 × 1012 cm−2 ) of backside
surface acceptor-like traps and an enhanced density (3×1018 cm−3 ) of donor-like trap
states within the upper ∼ 11 nm from the backside surface. The precipitous decrease
OF F
observed in ID
− h when h < 11 nm is ascribed to backside surface acceptor-like
traps and the closer physical proximity of the backside surface when the channel layer
is ultra-thin.
By altering the sputtering process gas ratio of Ar/O2 from 9/1 to 10/0 and reducing the anneal temperature from 400 to 150 ◦ C, a h ≈ 5 nm a-IGZO TFT is demonstrated with VON ≈ 0 V, field-effect mobility of µF E = 9 cm−2 V−1 s−1 , subthreshold
ON −OF F
slope of S = 90 mV/dec, and drain current on-to-off ratio of ID
= 2.0 × 105 .
c
Copyright by Tsung-Han Chiang
March 12, 2015
All Rights Reserved
Investigation of Ultra-thin In-Ga-Zn-O Thin-Film Transistors
by
Tsung-Han Chiang
A THESIS
submitted to
Oregon State University
in partial fulfillment of
the requirements for the
degree of
Master of Science
Presented March 12, 2015
Commencement June 2015
Master of Science thesis of Tsung-Han Chiang presented on March 12, 2015.
APPROVED:
Major Professor, representing Electrical & Computer Engineering
Director of the School of Electrical Engineering and Computer Science
Dean of the Graduate School
I understand that my thesis will become part of the permanent collection of Oregon
State University libraries. My signature below authorizes release of my thesis to any
reader upon request.
Tsung-Han Chiang, Author
ACKNOWLEDGEMENTS
I would like to acknowledge and thank my major advisor, Dr. John F. Wager, for
the priceless amount of support and guidance I received under his tutelage, both as
a graduate student and researcher. I am grateful for his patience with my technical
writing inability.
Work presented within this thesis would not have been possible without the
excellent management of the Materials & Devices Characterization Lab in Owen by
Chris Tasker and Rick Presley. Their willingness to listen and offer straight-forward,
simple solutions have always been incredibly useful for advancing research. Many
thanks goes to Rick Presley for training and certification of the many tools utilized
in this thesis.
My sincere thanks goes to everyone from the Wager group, particular acknowledgement goes to Bao Yeh and Fan Zhou. Several discussions with them have enlightened me on the finer aspects of device physics, TCAD simulations, as well as
the opportunity to practice in Mandarin. Additionally, my appreciation goes to the
members of the Conley group for their advice, collaboration, and friendship. You
have all made my time here much more enjoyable, whether it be in the lab, office, or
elsewhere.
Finally, I am forever grateful to my family for their love, support, and their
constant concern for my health. Without them, I would not have had the opportunity
and mental fortitude to be able to continue my graduate education here at Oregon
State University.
TABLE OF CONTENTS
Page
1 Introduction
1
2 Literature Review
3
2.1 Thin-Film Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 TFT Structures . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 TFT Device Operation . . . . . . . . . . . . . . . . . . . . . .
3
3
5
2.2 Transparent Conducting Oxides . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Amorphous Oxide Semiconductors . . . . . . . . . . . . . . . .
9
10
3 Experimental Technique
12
3.1 TFT Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
3.2 Substrate Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.3 Physical Vapor Deposition . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Radio Frequency Sputtering . . . . . . . . . . . . . . . . . . .
3.3.2 Thermal Evaporation . . . . . . . . . . . . . . . . . . . . . . .
14
14
18
3.4 Post-Processing Anneal . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
3.5 Channel Thickness Verification . . . . . . . . . . . . . . . . . . . . . .
20
3.6 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . .
21
4 a-IGZO TFT Channel Layer Thickness Study
26
4.1 Channel Thickness: Experimental Results . . . . . . . . . . . . . . . .
26
4.2 Channel Thickness: Discussion . . . . . . . . . . . .
4.2.1 Subthreshold Swing . . . . . . . . . . . . .
4.2.2 Turn-on Voltage Quantitative Analysis . .
4.2.3 OFF Drain Current Quantitative Analysis
4.2.4 Two-layer Model . . . . . . . . . . . . . .
4.2.5 Oxygen Adsorption Model . . . . . . . . .
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42
4.3 Thin Channel Process Development . . . . . . . . . . . . . . . . . . . .
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5 Conclusion and Recommendations for Future Work
49
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
5.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . .
50
TABLE OF CONTENTS (Continued)
Page
Appendices
52
A
Shadow Mask Specifications . . . . . . . . . . . . . . . . . . . . . . . .
53
B
Mobility Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Bibliography
58
LIST OF FIGURES
Figure
2.1
2.2
2.3
3.1
3.2
3.3
3.4
4.1
4.2
Page
Four thin-film transistor structures: (a) staggered top-gate, (b) staggered bottom-gate, (c) co-planar top-gate, (d) co-planar bottom-gate.
4
Energy band diagrams for a n-type enhancement-mode TFT under (a)
flat-band, (b) accumulation, and (c) depletion conditions. . . . . . . .
5
A simple, n-type, enhancement-mode, staggered bottom-gate TFT.
Due to application of a positive gate bias (VG ), an electron accumulation layer forms, electrically bridging the source and drain. Application
of a positive drain bias (VD ), leads to (a) injection of electrons from
the source to the accumulation layer (b), and extraction of electrons
from the accumulation layer through the drain (c). . . . . . . . . . .
7
Cross-section of a staggered, bottom-gate TFT. Note that TFT’s fabricated in this manner are not isolated from one another due to the
common substrate which acts as the gate. . . . . . . . . . . . . . . .
13
RF sputtering. Ionized Ar atoms diffuse from the (a) glow discharge
region into the (b) cathode sheath, then are accelerated toward the (c)
IGZO target via a large electric field. Ejected IGZO atoms travel from
the target to the (d) substrate surface. . . . . . . . . . . . . . . . . .
15
a-IGZO sputter deposition time (t) versus channel layer thickness (h).
Blue dots are confirmed with profilometry. Deposition time for channel
layer thicknesses less than 10 nm were extrapolated (red circles) from
the linear regression fit of the profilometry-confirmed samples. . . . .
20
Example of a log(ID )-VG transfer curve of an a-IGZO TFT. VON =
ON −OF F
−0.2 V, S = 350 mV/decade, ID
= 1.2 × 105 . . . . . . . . . . .
22
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer curve for an a-IGZO TFT with a channel layer thickness of 50 nm.
ON −OF F
VON = 0 V, S = 410 mV/dec, ID
= 1.9 × 105 . . . . . . . . . . .
27
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer behavior of an a-IGZO TFT with a channel layer thickness of 20
ON −OF F
nm. VON = −0.2 V, S = 220 mV/dec, ID
= 2.9 × 105 . . . . . .
28
LIST OF FIGURES (Continued)
Figure
4.3
Page
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer behavior of an a-IGZO TFT with a channel layer thickness of 10
ON −OF F
nm. VON = 1.9 V, S = 160 mV/dec, ID
= 3.9 × 105 . . . . . . .
29
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer behavior of an a-IGZO TFT with a channel layer thickness of 5 nm.
ON −OF F
VON = 9.9 V, S = 130 mV/dec, ID
= 1.0 × 106 . . . . . . . . . .
30
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer behavior of an a-IGZO TFT with a channel layer thickness of 2 nm.
ON −OF F
VON = 13 V, S = 350 mV/dec, ID
= 1.0 × 105 . . . . . . . . . .
31
Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer curve behavior for an a-IGZO TFT with various channel layer thicknesses. All a-IGZO TFTs are fabricated under identical processing
conditions: Ar/O2 = 9/1, pressure = 5 mTorr, RF power = 75 W, and
an air anneal at 400 ◦ C for 1 hour. . . . . . . . . . . . . . . . . . . . .
32
Extracted a-IGZO TFT log(ID ) − VG transfer curve parameters as a
function of channel layer thickness (h). (a) Subthreshold swing (S)
and state density due to bulk conduction bandtail states (DT A ) and
interface states (traps) (Dit ), i.e., (DT A · h + Dit ) on left and right
axes, respectively, (b) turn-on voltage (VON ), and (c) drain current off
OF F
) @ VG = VON . . . . . . . . . . . . . . . . . . . . . . . .
current (ID
34
4.8
A two-layer model for unpassivated a-IGZO TFTs. . . . . . . . . . .
41
4.9
Energy band diagram depicting oxygen adsorption on an unpassivated
a-IGZO surface. (a) A neutral oxygen molecule (O2 ) is physisorbed on
the surface, creating a empty neutral acceptor-like trap. (b) Thermal
excitation of the physisorbed O2 and free electron capture from the
conduction band, Ec , results in a chemisorbed negatively charged O2 ,
acting as a filled negative acceptor-like trap. (c) Partial depletion or
(d) full depletion is dependent on the thickness of the a-IGZO channel
layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
4.4
4.5
4.6
4.7
LIST OF FIGURES (Continued)
Figure
4.10 Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer behavior of an a-IGZO TFT with a channel layer thickness of 5 nm.
Modifications to the baseline process include pure Ar process gas and a
significantly decreased anneal temperature of 150 ◦ C. Duration of the
anneal and other process parameters remain unchanged. VON = 0.1 V,
ON −OF F
S = 90 mV/dec, ID
= 2.0 × 105 . . . . . . . . . . . . . . . . . .
Page
46
LIST OF TABLES
Table
2.1
Page
An outline of TFT drain current operation with respective gate/drain
voltage ranges and operating regimes. . . . . . . . . . . . . . . . . . .
9
Summary of IGZO sputter target specifications. Target was supplied
by Praxair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
3.2
Summary of mobilities defined TFT and MOSFET devices. . . . . . .
24
4.1
Extracted log(ID ) − VG transfer curve parameters for a-IGZO TFTs
with various channel layer thicknesses (h). All a-IGZO TFTs are fabricated under identical processing conditions: Ar/O2 = 9/1, pressure
= 5 mTorr, RF power = 75 W, and air anneal at 400 ◦ C for 1 hour. .
33
3.1
4.2
Extracted, experimental43 , and theoretical44 estimates of DT A and Dit ,
with corresponding process conditions: channel layer thickness (h),
gate dielectric thickness (tins ), RF power, Ar and O2 process gas ratio,
deposition pressure, and anneal temperature, duration, and environment. 36
4.3
Extracted log(ID ) − VG transfer curve parameters for a-IGZO TFTs
with varied Ar/O2 process gas ratio and anneal temperature (TA ).
Duration of the anneal, sputtering pressure = 5 mTorr and RF power
= 75 W were unchanged. . . . . . . . . . . . . . . . . . . . . . . . . .
47
LIST OF APPENDIX FIGURES
Figure
Page
A.1 ‘Clamping’ mask used in channel set. Mask is composed of 10 mil
thick, laser-cut, stainless steel. . . . . . . . . . . . . . . . . . . . . . .
53
A.2 ‘Patterning’ mask used in channel set. Mask is composed of 2 mil thick,
electroplated Ni. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
A.3 ‘Clamping’ mask used in source/drain contact set. Mask is composed
of 10 mil thick, laser-cut, stainless steel. . . . . . . . . . . . . . . . .
54
A.4 ‘Patterning’ mask used in source/drain contact set. Mask is composed
of 2 mil thick, electroplated Ni. . . . . . . . . . . . . . . . . . . . . .
54
B.1 µF E versus VG plot for 50 nm a-IGZO TFT
. . . . . . . . . . . . . .
55
B.2 µF E versus VG plot for 20 nm a-IGZO TFT
. . . . . . . . . . . . . .
56
B.3 µF E versus VG plot for 10 nm a-IGZO TFT
. . . . . . . . . . . . . .
56
B.4 µF E versus VG plot for 5 nm a-IGZO TFT . . . . . . . . . . . . . . .
57
B.5 µF E versus VG plot for 2 nm a-IGZO TFT . . . . . . . . . . . . . . .
57
Chapter 1: Introduction
Flat-panel displays dominate the commercial display market, constituting a multibillion dollar industry. The current flat-panel display leading technologies are activematrix liquid crystal displays (AMLCDs) and active-matrix organic light- emitting
diode (AMOLED). Ever growing demands for larger displays with higher resolution
has encouraged research into the development of thin-film transistors (TFTs), which
constitutes the backplane circuit logic that operates each pixel in an active-matrix display. State-of-the-art commercial AMLCDs and AMOLEDs use hydrogenated amorphous silicon (a-Si:H) as the TFT semiconductor channel material.
Until recently, the electron mobility and stability of a-Si:H have been adequate
to meet display requirements. This and the fact that a-Si:H could be deposited
uniformly over large area and at a relatively low cost are the reasons why a-Si:H has
been the leading channel material for TFTs in the flat-panel display industry for the
last decade. However, the low mobility and poor stability of a-Si:H TFTs appear to
be inadequate for larger size active-matrix displays with higher resolutions and higher
frame rates [1–4]. Thus, there has recently been a significant push in research toward
finding alternative TFT channel materials.
Amorphous oxide semiconductors (AOS) have recently attracted much attention as a potential alternative to a-Si:H in TFT applications. This is due to the
higher electron mobility, improved on/off current ratio, and superior stability of AOS
2
TFTs. The most popular AOS choice to date, amorphous indium-gallium-zinc-oxide
(a-IGZO), holds great promise as a commercial replacement for a-Si:H. a-IGZO was
first reported as a channel layer material for TFTs in November 2004 [5]. Since then,
many groups have published papers related to IGZO TFTs and it appears that IGZO
is on a fast track to commercialization [6].
The objective of the work reported herein is to explore the impact of decreasing
channel thickness on a-IGZO TFT electrical performance.
This thesis is organized as follows. Chapter 2 provides background information
regarding TFT structures, device operation, and AOS process integration. Chapter
3 overviews device preparation and fabrication techniques employed. Chapter 4 explores the effects of thinner a-IGZO channels on TFT electrical behavior. Chapter 5
contains conclusions and proposes recommendations for future work.
3
Chapter 2: Literature Review
This chapter reviews previously reported work in relation to a-IGZO TFTs. Secondly, TFT structures and device operation are examined.
2.1 Thin-Film Transistors
Transparent conducting oxide (TCO)-like materials have been in use for the last
four to five decades, while the concept of the thin-film transistor (TFT) began as
early as the 1930s [7]. TFTs represent a class of field-effect transistors where the
metal contacts, gate insulator, and active channel layer are deposited in thin layers.
The following subsections focus on TFT structure, operation, and characterization.
2.1.1 TFT Structures
All TFTs contain 3 basic components: a gate insulator, an active channel layer,
and metal contacts. The order in which these components are deposited can result
in different structures. There are four different types of structures that exist for
TFTs, as shown in Fig. 2.1: staggered top-gate, staggered bottom-gate, co-planar
top-gate, and co-planar bottom-gate. Classification of each structure is determined
by the location of the gate contact and the position of the source/drain contacts
relative to the gate contact. For example, if the gate contact rests above the channel
layer, it is known as the top-gate configuration. If the gate contact is positioned
below the channel layer, it is known as the bottom-gate configuration. A TFT is
4
considered co-planar when both the source / drain metal and gate metal reside on
the same side of the channel layer. Conversely, a TFT is considered staggered when
both the source / drain metal and gate metal reside on opposite sides of the channel
layer. There are multiple advantages and disadvantages associated with each of the
four aformentioned structures [8, 9]. Staggered bottom-gate structure are employed
exclusively within this thesis.
Figure 2.1: Four thin-film transistor structures: (a) staggered top-gate, (b) staggered
bottom-gate, (c) co-planar top-gate, (d) co-planar bottom-gate.
5
2.1.2 TFT Device Operation
Thin-film transistors are three-terminal devices which behave functionally as
a voltage-controlled current source. The current flow between the source and the
drain is modulated by application of a bias voltage to the third gate terminal. This
modulation of current is best understood by observing energy band diagrams with
respect to applied gate bias. Energy band diagrams of an n-type enhancement-mode
TFT with respect to various gate bias voltages are illustrated in Fig. 2.2.
Figure 2.2: Energy band diagrams for a n-type enhancement-mode TFT under (a)
flat-band, (b) accumulation, and (c) depletion conditions.
In the case where no gate bias is applied, the semiconductor region is considered
to be at flat-band with no apparent band-bending, as shown in Fig. 2.2(a). When
a positive gate bias is applied, a region of negative charge builds up at the channelinsulator interface. This region of negative charge is known as the accumulation
region, which leads to the negative band-bending as shown in Fig. 2.2(b). Likewise,
when a negative gate bias is applied, positive charge builds up to form a region
known as a depletion region. This build-up of positive charge causes the positive
band-bending as shown in Fig. 2.2(c).
6
The previous example shown in Fig. 2.2 represented an enhancement-mode TFT.
However, a TFT may be classified in as either enhancement-mode or depletion-mode.
The distinguishing feature between these classifications is the required gate voltage to accumulate a channel and essentially turn the device ‘ON.’ In the case of
enhancement-mode, the TFT is normally ‘OFF’ (no current flow between source and
drain when no gate voltage is applied), and only turns on when a positive gate voltage is applied. In contrast, a depletion-mode TFT is ‘ON’ when no gate voltage is
applied, thus requiring a negative applied gate voltage to turn the device ‘OFF.’ The
voltage at which charge begins to accumulate between the semiconductor-insulator
interface is defined as the turn-on voltage (VON ) [10].
While the application of an appropriate gate voltage (VG ) induces an accumulation
layer, TFT device operation is also dependent on the application of a drain voltage
(VD ). In the example of a simple, n-type, enhancement-mode, staggered bottom-gate
TFT, as shown in Fig. 2.3, a positive gate bias creates an electron accumulation layer
at the channel-insulator interface. Whereupon a positive voltage applied across the
drain-source terminals: (a) injects electrons from the source terminal to the accumulation layer, (b) transports electrons across the accumulation layer toward the drain,
and (c) extracts the electrons through the drain terminal.
In general, the operation of a simple, n-type, enhancement-mode TFT can be
subdivided into four regimes: cut-off, subthreshold, pre-saturation, and saturation.
In the cut-off region, there is insufficient VG applied to form an electron accumulation layer at the semiconductor interface, resulting in a fully depleted channel layer.
However, note that some drain current (IOF F ) still flows due to leakage through the
7
Figure 2.3: A simple, n-type, enhancement-mode, staggered bottom-gate TFT. Due
to application of a positive gate bias (VG ), an electron accumulation layer forms,
electrically bridging the source and drain. Application of a positive drain bias (VD ),
leads to (a) injection of electrons from the source to the accumulation layer (b), and
extraction of electrons from the accumulation layer through the drain (c).
gate and/or drain as a constraint of the noise floor of the measurement setup. In
the subthreshold regime, the onset of the drain current (ID ) is apparent as an accumulation layer forms and current flows due to application of a positive VG and VD .
Subthreshold current is notable in that it is derived from carrier diffusion rather than
drift, where ID increases exponentially with respect to VG . The subthreshold swing,
S, can be related by the ratio of the insulator to interface trap capacitances [11].
Thus, for VG ≥ VON under subthreshold operation, ID is typically modeled using by
the following relationship,
W
µCI
ID =
L
kB T
q
2
q (VG −VON ) −qVD
C
1+ IT )kB T
(
CI
e
1 − e kB T .
(2.1)
where W is the gate width, L is the gate length, µ is the average effective mobility
across the channel, and CI & CIT are the insulator and interface trap capacitances,
8
respectively.
In the pre-saturation and saturation regime, ID is determined by the mobile
carrier density and the carrier drift mobility in the accumulation layer along the
channel. In the pre-saturation regime, carriers are accumulated at the semiconductorinsulator interface via a positive gate voltage (VG ≥ VON ) and are then swept from
the source to the drain via the application of a drain voltage (VD ≤ (VG − VON )). In
pre-saturation, ID is expressed as,
VD2
W
µCI (VG − VON ) VD −
.
ID =
L
2
(2.2)
Observe that as VD increases, ID increases in an almost linear manner as long as VD
is much less than the gate overvoltage (VG − VON ). This is due to the fact that, under
this VD constraint, carrier behavior within the channel is dominated by the applied
gate voltage and not by carrier injection and extraction at the source/drain terminals.
Note that as VD approaches VG − VON , the
2
VD
2
term begins to dominate drain current
behavior, leading to a non-linear increase in ID with respect to increasing VD . This
can be attributed to the applied drain voltage encroaching upon the accumulation
layer, such that a uniform accumulation layer between the source and drain terminals
can no longer be assumed. A further increase of VD results in extraction effects
near the drain terminal dominating carrier behavior, leading to a situation known
as saturation, in which an increasing drain voltage no longer results in an increase
in drain current (VD ≥ (VG − VON )). ID in saturation is expressed by the following
9
Operating Regime
Cut-off
Voltage Range
VG < VON
Subthreshold
VG ≥ VON
Pre-saturation
VG ≥ VON
Saturation
VD ≤ (VG − VON )
VG ≥ VON
VD ≥ (VG − VON )
Drain Current Expression
ID ≈ 0 (gate/drain leakage)
−VON ) 2 q(VCGIT
−qVD
kB T
1+
kB T
)
(
W
CI
1 − e kB T
ID = L µCI q
e
ID =
W
µCI
L
ID =
h
(VG − VON ) VD −
W
µCI
2L
2
VD
2
i
(VG − VON )2
Table 2.1: An outline of TFT drain current operation with respective gate/drain
voltage ranges and operating regimes.
equation,
ID =
W
µCI (VG − VON )2 .
2L
(2.3)
All aforementioned operational regimes and respective current-voltage relationships are summarized in Table 2.1. Detailed discussion on TFT electrical parameters
is deferred to Section 3.6.
2.2 Transparent Conducting Oxides
Optical transparency and electrical conductivity within a material was an unheard of phenomenon until it was first observed in the early 1900’s in a cadmium
oxide film. Even so, it wasn’t until the 1940’s, when tin oxide (SnO2 ) became commonly used in electroluminescent panels, that tranparent conducting oxides (TCOs)
began sparking interest. TCOs are a class of materials which have high optical transmission in the visible portion of the electromagnetic spectrum (i.e. transparent) and
have an electrical conductivity approaching that of a metal. A number of important
applications for TCOs have been developed and implemented, such as energy-efficient
10
low-e windows, solar cells, and electrochromic windows [12]. By employing both its
optical and electrical properties, TCOs have also found applications as transparent
electrical contacts in flat-panel displays, optical sensors, and solar cells [13–15]. The
most commonly used TCO is currently indium tin oxide (ITO) and is typically used
in transparent contact applications. Compared to typical metals used in circuit fabrication, such as tungsten, aluminium, and copper, ITO has a order of magnitude
lower conductivity [16, 17]. A discussion of amorphous oxide semiconductors (AOS)
stems naturally from that of TCOs, since AOS materials are often designed using one
or more of the three most common TCOs, i.e. In2 O3 , SnO2 , and ZnO.
2.2.1 Amorphous Oxide Semiconductors
The discovery of hydrogenated amorphous silicon (a-Si:H) in 1975 [18] led to
new innovations where electronic circuits could be fabricated on large area substrates
due to the amorphous nature of a-Si:H. One of the biggest applications of a-Si:H has
been in the display industry, where a-Si:H is used as a channel material for TFTs,
fabricated on large glass substrates, in active-matrix flat-panel displays. However,
limitations in the mobility of a-Si:H prompted study into the research of alternative
material replacements.
Before the first documented use of amorphous oxide semiconductors (AOSs) in
TFTs, Hosono et al. published a paper discussing various AOS materials and the overall promise of AOSs in manufacturing and application [19,20]. AOSs can be deposited
with low-temperature processes such as pulsed-laser deposition (PLD) and sputtering,
whereas a-Si:H has deposition processes of up to 250 ◦ C. With low-temperature pro-
11
cesses, fabrication of devices on plastic substrates such as polyethylene terephthalate
(PET) allow a whole new realm of applications. Various prototypes of applications in
e-paper and flexible AMOLED displays have proven viable, with a path to commercialization seemingly on the way. One of the reasons why the development of AOSs
has come up so quickly is due to the amorphous nature of AOSs, which allows for
ease of manufacturing due to lack of grain boundaries, atomically smooth surfaces,
and low temperature processibility. The first reported use of amorphous oxide semiconductors in a TFT application was based on research done by Nomura et. al. in
2004 [5].
12
Chapter 3: Experimental Technique
This chapter is intended to review background information involving preparation,
fabrication processes, and testing methods of TFTs. Detailed discussion of process
optimization and characterization results can be found in Chapter 4.
3.1 TFT Fabrication
As discussed in Section 2.2.1, staggered, bottom-gate TFTs are employed exclusively in this work. The TFT fabrication order is as follows: gate metal deposition, gate insulator deposition, channel deposition, post-deposition anneal, and
source/drain contact deposition. This structure was chosen such that only the channel and source/drain regions require patterning, which can be done via shadow mask,
allowing for relatively rapid throughput from device fabrication to device testing and
characterization. A cross-section example of a staggered, bottom-gate structure is
seen in Fig. 3.1. Boron-doped, p-type Si is used as the substrate.
Shadow masks used in patterning the channel and source/drain contacts were ordered from Photo Stencil from Colorado Springs, CO. Both channel and source/drain
contacts utilize a set of two shadow masks each. Within a set, there is a ‘patterning’ mask, which defines the final regions of channel and source/drain. Note that
this particular mask should be as thin as possible, in order to mimimize shadowing
(i.e., non-uniform deposition of material near the edge of the defined regions). The
second mask is the ‘clamping’ mask, its only purpose being to hold the ‘patterning’
13
mask flush to the surface of the substrate during deposition. Because it is desirable
to apply uniform pressure on the ‘patterning’ mask, the ‘clamping’ mask is designed
to be more resistant to flexing by utilizing a thicker, sturdier material compared to
the ‘patterning’ mask. The ‘patterning’ mask is a 2 mil thick electroformed Ni sheet,
whereas the ‘clamping’ mask is a 10 mil thick, laser-cut stainless steel plate. Aperture
dimensions of each mask set can be found in Appendix A.
A Ta/Au alloy and SiO2 are used as the gate metal and gate dielectric, respectively.
The TFT channel consists of an In-Ga-Zn-O (IGZO) amorphous oxide semiconductor (AOS) deposited through sputtering, discussed in greater detail in Section 3.3.1.
Aluminum is deposited via thermal evaporation to form the source and drain contact
metal; detailed discussion can be found in Section 3.3.2.
Figure 3.1: Cross-section of a staggered, bottom-gate TFT. Note that TFT’s fabricated in this manner are not isolated from one another due to the common substrate
which acts as the gate.
14
3.2 Substrate Preparation
Fabrication of TFTs presented in this work begins using a p-type Si substrate with
100 nm of SiO2 and a Ta/Au back contact provided by the Hewlett-Packard Company. Surface cleaning is accomplished using a modified AMD (acetone, methanol, DI
water) cleaning process in which isopropyl alcohol (IPA) is substituted for methanol.
It should be noted that allowing acetone to evaporate prior to IPA dissolution leaves
organic residue on the substrate, negatively impacting device characteristics. Therefore, it is necessary to maintain a constant surface wetting of acetone in between the
acetone and IPA wash. Following the AMD clean, substrates are dried with high
pressure N2 and dehydrated at 200 ◦ C for a minimum of 30 minutes.
3.3 Physical Vapor Deposition
Most methods of thin film deposition can be catergorized as physical vapor deposition (PVD) or chemical vapor deposition (CVD). Sputtering is a commonly used
PVD method. The basic PVD concept is simple. Initially, the desired material is
converted from a solid into a vapor phase. The vapor is then transported from where
the material is sourced to a substrate through a region of low pressure or vacuum.
The vapor condenses onto a substrate, thereby depositing the desired material as a
thin film [21].
3.3.1 Radio Frequency Sputtering
The physical mechanism by which atoms are ejected from the surface of a material
(target) when that surface is struck by sufficiently energetic particles is described
as sputtering [21, 22]. These energetic particles can be sourced from a variety of
15
noble elements such as Ne, Ar, Kr, and Xe, which are introduced into the sputtering
chamber as process gases as a neutral species. In this thesis, Ar was chosen as the
primary process gas due to its availability and relative atomic size compared to the
target elements: In, Ga, & Zn, allowing for better atomic transfer. A characteristic
feature of sputtering is the glow discharge cloud which appears between the target
and substrate, as depicted in Fig. 3.2.
Figure 3.2: RF sputtering. Ionized Ar atoms diffuse from the (a) glow discharge region
into the (b) cathode sheath, then are accelerated toward the (c) IGZO target via a
large electric field. Ejected IGZO atoms travel from the target to the (d) substrate
surface.
The cause of this glow discharge can be attributed to the relaxation of excited Ar
atoms, where a photon is emitted as excess energy. The dark space between the target
and the glow discharge cloud is known as the cathode sheath. During sputtering, a
negative potential is applied to the target. The electric field created by this potential
extends into the cathode sheath. Any Ar ions diffusing from the glow discharge to the
cathode sheath experience a strong electric field which accelerate these ions toward
16
the surface of the target, ejecting target atoms which then travel across the sheath
and glow discharge regions to settle onto the exposed substrate surface. Two concerns
that need to be addressed are the method in which the negative potential is applied
to the target and the physics of ejected atoms from target to substrate.
There are two methods for applying the negative potential to the sputtering target: direct current (DC) or radio frequency (RF), the choice of which depends on
whether the target is conductive or insulating. RF sputtering can be used with both
conductive and insulating targets. DC sputtering is only applicable to conductive targets. The goal of both DC and RF potentials is to create a strong electric field in the
sheath in order to induce Ar-ion bombardment of the target surface. The mechanism
of applying a negative potential to the target is the distinguishing factor between DC
and RF sputtering, via the application of direct-current (DC) and alternate-current
(AC) voltage, respectively. Typical RF frequencies are 13.56 MHz [21]. DC sputtering of an insulating target is not possible because the insulating behavior of the target
leads to charge build-up of electrons on the surface of the target and prevents the
formation of a stable plasma. Thus, it is necessary to prevent electrons from building
up on the surface of the target through the use of an RF bias in which the voltage
polarity rapidly alternates. Due to the difference in atomic mass, smaller electrons
more readily respond and oscillate in phase with the applied AC signal. In contrast,
larger Ar+ ions are more sluggish so that they can react only to the average voltage
established, in this case, the DC self-bias potential. The self-bias potential arises as
a consequence of the rectifying nature of the plasma. Once the self-bias potential
is developed, Ar+ ions are extracted from the plasma and are accelerated across the
17
cathode sheath in the same manner as previously described.
RF sputtering of IGZO thin-films is accomplished in an AJA Orion 5 system, a
compact version of the CTE system offered by AJA International, Inc. The system
itself is composed of a stainless steel vacuum chamber in addition to a load-lock. The
main chamber supports five 2-inch sputtering guns fashioned in a sputter-up, confocal
configuration, with manual shutter control via a pneumatic valve. Four of the five
sputter guns are powered with an RF power supply (AJA 100/300 / Seren Industrial
Power Systems R301) and an automatic RF matching network (Seren Industrial Power
Systems MC2). The last sputter gun is powered with the same RF power supply (AJA
100/300 / Seren Industrial Power Systems R301), but utilizes a manual RF power
matching network instead (AJA 100/300 MM3X / Seren Industrial Power Systems
MM-Series). The process pressure is controlled through the use of two mass-flow
controllers (MKS Type M100B) to establish the flow rates of the two process gases,
Ar and O2 . Two high-vacuum turbomolecular pumps are utilized in pumping both the
vacuum chamber and the load-lock (Pfeiffer HiPace 700 and Pfeiffer TMH1000MP
respectively). Both turbomolecular pumps are backed by mechanical dry pumps
(Alcatel Adixen Pascal 2010 50 and Edwards RV12). Typical background pressure of
the AJA Orion 5 system is < 4 × 10−8 Torr.
The IGZO sputter target was ordered from Praxiar by Kent Millard from Intel.
Specifications include a 2” target of In:Ga:Zn = 1:1:1 atomic ratio (i.e., 1:1:2% mol
ratio) with a purity and density of 99.99% and >90% respectively. Target material
was bonded to a copper backplate with silver adhesive and centered to within 0.00500 .
Target parameters are summarized in Table 3.1.
18
Target Parameter
Stoichiometry
Purity
Density
Diameter
Target Material Thickness
Bonding Material thickness
Target Centering Margin
Specification
In2 O3 :Ga2 O3 :ZnO=1 : 1 : 2 in mol%
99.99%
> 90%
00
2.00 + 0.00300 − 0.00700
0.18800 ± 0.00500
0.01500
0.00500
Table 3.1: Summary of IGZO sputter target specifications. Target was supplied by
Praxair.
3.3.2 Thermal Evaporation
Thermal evaporation falls under the category of physical vapor deposition (PVD)
and is one of the more common processes for depositing metal layers. The physical
mechanism of ejecting source atoms is a much simpler process to implement with
thermal evaporation in contrast to sputtering. Sublimation of the source atoms is
accomplished by bringing a metal pellet to its respective melting point with the
application of a large current to a resistive thermal coil. Similar to sputtering, when
thermal evaporation is accomplished is a vacuum environment, atoms evaporated
from the pellet will travel on a ballistic trajectory from the source to the nearest
surface.
Aluminum metal layers are deposited via thermal evaporation in a Polaron model
E6100 bench-top vacuum evaporator. A 250 mm thick, 10 inch diameter glass cover
constitutes the main chamber, with a basket-shaped tungsten filament as a holder.
Base pressure of the Polaron system is roughly 5×10−5 mbar, equivalent to 3.75×10−5
Torr. Prior to Al evaporation, the main chamber is pumped down to < 2 × 10−5
mbar (< 1.5 × 10−5 Torr) via high vacuum oil diffusion pump. In order to expedite Al
19
deposition, a fast ramp up to 30 A of current is run through the tungsten filament. The
purpose behind performing a fast deposition is to minimize contaminant incorporation
and maintain a good interface between the semiconductor and metal.
3.4 Post-Processing Anneal
Following IGZO deposition, samples are exposed to a high temperature environment for an extended period of time, otherwise known as a anneal. It is generally
known that fabrication of a-IGZO TFTs without the use of an annealing process leads
to unstable and poor electrical performance. Many groups have determined that an
anneal performed at greater than 300 ◦ C results in an improvement in TFT device
performance [23–30]. The general concept is that the anneal removes physical defects,
such as sputter damage, and stabilizes the oxygen concentration, although this has
not been explicitly confirmed. In addition to a simple anneal in air, moderate success
has been achieved by annealing a-IGZO TFTs under various environments, such as,
nitrogen atmosphere [28], wet atmosphere [29], and high-pressure hydrogen annealing
[30]. It has also been reported that annealing at a temperature above 600 ◦ C leads
to subsequent degradation of device behavior due to crystallization of the a-IGZO
channel layer.
Samples prepared in this thesis undergo an anneal in air at temperatures (TA ) of
100 ◦ C < TA < 400 ◦ C. Anneals are performed in a Neytech Centurion Qex vacuum
furnace.
20
3.5 Channel Thickness Verification
Channel thickness of a-IGZO TFTs was controlled by increasing/decreasing sputter deposition time. The relationship between channel thickness and sputter deposition time is shown in Fig. 3.3. It was found that samples deposited with a 25,
10, and 5 minute deposition time (blue dots) had average channel layer thicknesses
of 47.5, 20, and 8.8 nm, respectively. Samples with 25, 10, and 5 minute deposition
time were verified via profilometry. Measurements done on samples with less than
2.5 minute deposition time were inconclusive due to lack of signal-to-noise contrast.
Thicknesses of these samples were extrapolated from the linear regression fit of the
thicker samples. Extrapolated thicknesses for 2.5 and 1 minute deposition times (red
circles) were 4.7 and 1.85 nm, respectively.
Figure 3.3: a-IGZO sputter deposition time (t) versus channel layer thickness (h).
Blue dots are confirmed with profilometry. Deposition time for channel layer thicknesses less than 10 nm were extrapolated (red circles) from the linear regression fit of
the profilometry-confirmed samples.
21
3.6 Electrical Characterization
Basic TFT operation was previously discussed in Section 2.1.2. The standard
method of testing TFT electrical behavior is to simply probe the source, drain, and
gate contacts of the TFT. By applying a constant and variable voltage across the
source/drain and gate contact, respectively, one can plot drain current (ID ) as a
function of gate voltage (VG ), which is refered to as the transfer curve, as depicted in
Fig. 3.4. Conversely, if the constant and variable voltage are switched such that the
source/drain is variable and the gate is held constant, an output curve is generated,
where ID is a function of drain voltage (VD ). ID is typically plotted on a log (linear)
scale for a transfer (output) curve. Discussion of TFT electrical behavior in this thesis
will focus on transfer curve measurements.
From the transfer curve, there are four figures of merit that can be extracted in
order to determine the TFT’s electrical performance: turn-on voltage (VON ), drain
ON −OF F
current on-to-off ratio (ID
), subthreshold swing (S), and mobility (µ).
VON represents the gate voltage at which the onset of drain current becomes
apparent [10, 31]. At this point, the gate accumulation layer forms at the insulator/
semiconductor interface, allowing electrons injected from the source to have a path
to travel towards the drain .
OF F
ID
is defined as the magnitude of drain current when the gate voltage is
less than the turn-on voltage (VG < VON ). Conversely, when the gate voltage is
greater than the turn-on voltage (VG > VON ), the magnitude of the drain current is
ON
ON
labeled as ID
. In this thesis, ID
values are taken at gate voltages of 20 V (i.e.,
ON
OF F
ID
= ID |VG =20V ). ID
is taken to be the drain current where the gate voltage
22
Figure 3.4: Example of a log(ID )-VG transfer curve of an a-IGZO TFT. VON = −0.2
ON −OF F
V, S = 350 mV/decade, ID
= 1.2 × 105 .
OF F
is near VON (i.e., ID
= ID |VG =V − ). The difference between the TFT’s maximum
ON
ON −OF F
ON −OF F
ON
OF F
and minimum current is expressed as ID
. In this thesis, ID
= ID
/ID
can be calculated by
ON −OF F
ID
=
ID |VG =20V
,
ID |VG =V −
(3.1)
ON
Subthreshold swing, S, is defined as the value of gate voltage required to obtain
a 10 times larger drain current in the subthreshold region. The importance of S is
that it can determine the minimum VG operational voltage range required to switch a
TFT from the ‘OFF’ state to the ‘ON’ state. Based on the standard diffusion model,
S can be described as
kB T
S = ln(10)
q
q(DT A · h + Dit )
1+
.
CG
(3.2)
23
where DT A is the volume density of traps in the bulk of the channel, Dit is the area
density of traps at the channel-gate oxide interface, h is the channel layer thickness,
CG is the gate oxide capacitance per area, kB is the Boltzmann constant, and T is
the absolute temperature in Kelvin [32, 33]. Note that due to the dependence on
kB T /q, if one were to assume a defect-free film (i.e., DT A = 0 cm−3 eV−1 and Dit =
0 cm−2 eV−1 ), the theoretical minimum of S at 273 K would be 59.2 mV/dec.
Subthreshold swing is determined empirically by
S=
∂log10 ID
|VG ≈VON
∂VG
−1
.
(3.3)
Mobility is a measure of the effectiveness of carrier transport. More precisely,
mobility is the proportionality constant relating carrier velocity to applied electric
field when the electric field is small enough that linear transport prevails. Mobility
is extracted from a transfer curve with a low applied drain voltage to ensure linear
operation (i.e., VD << VDSAT << VG − VON ). The four types of mobility commonly
employed are incremental (µIN C ), average (µAV G ) [10], field-effect (µF E ), and effective
mobilities (µEF F ).
µIN C corresponds to the incremental mobility of carriers that are injected into
the channel as the gate bias incrementally increases, giving insight into carrier transport. Incremental mobility can be extracted from a transfer curve via the following
expression,
µF E (VG ) = µIN C (VG ) =
∂Gd (VG )
∂VG
W
C
L G
|VDS →0 .
(3.4)
where Gd (VG ) = ID /VD is the channel conductance and CG is the gate insulator
24
Model
Mobility
TFT [10]
µIN C
TFT [10]
µAV G
MOSFET
µF E
MOSFET
µEF F
Equation
∂Gd (VG )
∂VG
W
C
L G
VD →0
Gd (VG )
W
C (V −VON ) L G G
VD →0
∂gm (VGS ) W
C V
L G DS
VDS →0
∂gm (VGS )
W
C (V −VT ) L G GS
VDS →0
Table 3.2: Summary of mobilities defined TFT and MOSFET devices.
capacitance density (34.5 nF/cm2 for 100 nm SiO2 ).
µAV G represents the average mobility of all carriers in the channel and is derived
as,
µAV G (VG ) =
Gd (VG )
|V →0
W
C (V − VON ) DS
L G G
.
(3.5)
Incremental and average mobilities were derived by Hoffman [10] in order to account
for accumulation-mode TFT operation. Table 3.2 summarizes mobilities derived by
Hoffman and other conventional mobilities found in literature. Note that the only
major differences between the Hoffman mobilities and conventional MOSFET µF E
and µEF F is that VON replaces VT . Otherwise, µIN C (µAV G ) is directly analagous to
µF E (µEF F ).
Field effect mobilities reported in this thesis were extracted from the transfer
curve via Eq. 3.4 and taken at a gate overvoltage (Vov = 5 V) above VON (i.e.,
25
µF E |VG ≈VON +Vov ). This is implemented in order to maintain a consistent measurement
to all samples with varying VON .
Transfer curve electrical characterization was carried out on the Alessi probestation located in Owen 333. 100 micron Tungsten probe tips were used to contact the
Al source/drain contacts of the a-IGZO TFT. Contact to the Au/Ta bottom gate was
accomplished via gold-plated chuck. Both probe tips and chuck were connected with
coax-cable to an Agilent 4155C semiconductor parameter analyzer (SPA). All measurements were carried out in the dark in a darkbox. All transfer curve measurements
were repeated thrice in order to insure steady-state operation.
26
Chapter 4: a-IGZO TFT Channel Layer Thickness Study
Experimental results relating to a-IGZO TFTs with ultra-thin channel layers are
presented in this chapter.
4.1 Channel Thickness: Experimental Results
A primary objective of this thesis was to discover how thin the channel of an aIGZO TFT could be made and yet obtain reasonable TFT performance. Preliminary
studies of processing conditions (Ar/O2 process gas ratio, sputtering pressure, RF
power to target, and post-deposition annealing temperature) revealed that an optimal
process for a TFT with a 50 nm thick a-IGZO channel required an Ar/O2 ratio of 9/1,
a sputtering pressure of 5 mTorr, RF power of 75 W, and a post-deposition annealing
temperature of 400 ◦ C for 1 hour. Transfer curves extracted from an a-IGZO TFT
fabricated under these ‘baseline’ conditions are depicted in Fig. 4.1. The resulting
ON
= 7.8 × 10−6 A,
transfer curve parameters were: VON = 0 V, S = 410 mV/dec, ID
ON −OF F
OF F
= 1.5 × 10−11 A, and ID
ID
= 1.9 × 105 .
Once an optimal 50 nm process was established, a channel layer thickness study
could begin. Batches of a-IGZO TFTs were fabricated using the baseline processing
conditions previously mentioned, except that deposition time, and therefore channel
layer thickness, was varied. a-IGZO TFTs with channel layer thicknesses of 20, 10,
5, and 2 nm were fabricated. Verification of channel layer thickness is discussed in
Section 3.5.
27
Figure 4.1: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
curve for an a-IGZO TFT with a channel layer thickness of 50 nm. VON = 0 V,
ON −OF F
S = 410 mV/dec, ID
= 1.9 × 105 .
In thinning the channel to 20 nm, the resulting transfer curve (Fig. 4.2) exhibits
an improvement in subthreshold swing, i.e., S(20 nm) = 220 mV/dec compared
ON −OF F
to S(50 nm) = 410 mV/dec, and ID
ratio, whereas VON remains relatively
ON −OF F
constant. The slight improvement in ID
is primarily due to the decrease in
OF F
OF F
ID
(20 nm) = 12 pA from ID
(50 nm) = 15 pA. When the channel layer thickness
is decreased to 10 nm (Fig. 4.3), VON increases to 1.9 V in contrast to the near-zero
VON for both the 50 nm and 20 nm TFT. However, for the 10 nm a-IGZO TFT, both
OF F
OF F
S and ID
improve, decreasing to S = 160 mV/dec and ID
= 10 pA, respectively.
The a-IGZO channel layers being explored are quite thin. Assuming an interatomic spacing of 0.2 nm [34], the 20, 10, 5, and 2 nm channel layers are approximately
100, 50, 25, and 10 atoms thick, respectively. Thus, from a thickness perspective, it
28
Figure 4.2: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
behavior of an a-IGZO TFT with a channel layer thickness of 20 nm. VON = −0.2
ON −OF F
V, S = 220 mV/dec, ID
= 2.9 × 105 .
is remarkable that these thin channel layer a-IGZO TFTs exhibit respectable performance.
The 5 nm thick a-IGZO TFT, whose transfer curve is shown in Fig. 4.4, reveals
ON −OF F
OF F
excellent switching behavior with S = 130 mV/dec, ID
= 106 , and ID
= 4.6
pA. However, the turn-on voltage is undesirably large, i.e., VON = 9.9 V.
VON continues to shift to a large positive voltage of 13 V when the a-IGZO channel layer thickness is reduced to 2 nm, as given in Fig. 4.5. Other aspects of TFT
performance also show significant degradation. Specifically, the subthreshold swing
increases, i.e., S = 350 mV/dec, the on current decreases significantly, resulting in
ON −OF F
a decrease in ID
by an order of magnitude to 105 , and a significant amount
of clockwise hysteresis appears in the transfer curve. Indeed, the only property im-
29
Figure 4.3: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
behavior of an a-IGZO TFT with a channel layer thickness of 10 nm. VON = 1.9 V,
ON −OF F
S = 160 mV/dec, ID
= 3.9 × 105 .
OF F
= 0.75 pA, the
provement witnessed in the 2 nm thick transfer curve is that ID
lowest of all the various thicknesses investigated.
The hysteresis in both the 5 nm and 2 nm a-IGZO TFTs is curious since it is
counter-clockwise. Counter-clockwise (clockwise) hysteresis is usually ascribed to ion
migration (electron trapping) [35–40]. When hysteresis is observed in the 50, 20,
and 10 nm thick a-IGZO TFTs, the hysteresis is clockwise, consistent with electron
trapping. It is not clear whether the counter-clockwise hysteresis observed for the 5
nm and 2 nm a-IGZO TFTs is due to ion migration (of surface adsorbed gas species,
most likely) or is a measurement artifact associated with the choice of +20 V as the
voltage for initiating the gate voltage sweep. The fact that hysteresis occurs near +20
V, rather than near the subthreshold portion of the transfer curve, where it is normally
30
Figure 4.4: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
behavior of an a-IGZO TFT with a channel layer thickness of 5 nm. VON = 9.9 V,
ON −OF F
S = 130 mV/dec, ID
= 1.0 × 106 .
observed, suggests it to be a measurement artifact. In subsequent measurements
(not shown), the voltage sweep is initiated from -10 V and the hysteresis vanishes,
supporting the view that this counter-clockwise hysteresis is a measurement arifact.
However, this -10 V initiated measurement was performed 15 months after the +20
V inititated measurement and yielded VON = 2 V instead of VON = 9.9 V. +20 V
initiated measurements were also performed at this time, with transfer curve behavior
closely matching the -10 V initiated measurements. Thus, the nature of this counterclockwise hysteresis could not be conclusively resolved.
Transfer curves shown in Figs. 4.1 - 4.5 are overlaid in Fig. 4.6. Four trends
are observed as a function of decreasing channel layer thickness: 1) a positive shift
OF F
of VON , 2) a decrease in ID
, 3) a decrease in subthreshold slope, and 4) a decrease
31
Figure 4.5: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
behavior of an a-IGZO TFT with a channel layer thickness of 2 nm. VON = 13 V,
ON −OF F
S = 350 mV/dec, ID
= 1.0 × 105 .
ON
in ID
which occurs for channel layer thicknesses less than 10 nm. These trends
are emphasized in Fig. 4.6 by corresponding arrows, depicting how these parameters
shift in the direction of decreasing channel layer thickness (h). VON is shown to shift
from an initial starting value of 0 V at 50 nm, with no significant change until 10 nm,
when VON = 1.9 V. Below a channel layer thickness of 10 nm, large positive shifts
in VON are observed, i.e., VON (5 nm) = 9.9 V and VON (2 nm) = 13 V. Subthreshold
behavior is more difficult to observe in a transfer curve plot. However, extracted
values show that S decreases linearly from S(50 nm) = 410 mV/dec to S(5 nm) =
OF F
OF F
OF F
130 mV/dec. By following ID
, one can observe that ID
decreases from ID
(50
OF F
nm) = 15 pA to ID
(2 nm) = 0.75 pA. Additionally, thinning the a-IGZO channel to
ON
2 nm appears to substantially degrade ID
and S, yielding 190 pA and 350 mV/dec,
32
Figure 4.6: Logarithm of the drain current versus gate voltage (log(ID ) − VG ) transfer
curve behavior for an a-IGZO TFT with various channel layer thicknesses. All a-IGZO
TFTs are fabricated under identical processing conditions: Ar/O2 = 9/1, pressure =
5 mTorr, RF power = 75 W, and an air anneal at 400 ◦ C for 1 hour.
OF F
ON
, and
, ID
respectively. A summary of extracted transfer parameters (VON , S, ID
ON −OF F
ID
) is listed in Table 4.1.
In Fig. 4.7(a), a linear regression fit is shown between subthreshold swing (S)
and channel layer thickness (h) for thicknesses between 5 - 50 nm,
S ≈ 6.3 · h [nm] + 92 [mV/dec].
(4.1)
Note that the regession fit is inapplicable for a channel layer thickness of 2 nm since
a sharp increase to 350 mV/dec in S is observed.
In Fig. 4.7(b), VON is near zero for channel layer thickness greater than ∼ 11 nm
and increases linearly with decreasing channel layer thickness below
∼
11 nm. The
33
h (nm) µF E (cm2 V−1 s−1 )
50
7.5
20
12
10
12
5
11
2
1
ON
VON (V) S (mV/dec)
ID
(A)
0
410
7.8 × 10−6
- 0.2
220
1.0 × 10−5
1.9
160
9.0 × 10−6
9.9
130
5.3 × 10−6
13
350
1.9 × 10−7
OF F
ID
(A)
1.5 × 10−11
1.2 × 10−11
10 × 10−11
4.6 × 10−12
0.75 × 10−12
ON −OF F
ID
1.9 × 105
2.9 × 105
3.9 × 105
1.0 × 106
1.0 × 105
Table 4.1: Extracted log(ID ) − VG transfer curve parameters for a-IGZO TFTs with
various channel layer thicknesses (h). All a-IGZO TFTs are fabricated under identical
processing conditions: Ar/O2 = 9/1, pressure = 5 mTorr, RF power = 75 W, and air
anneal at 400 ◦ C for 1 hour.
regression fit of VON as a function of channel layer thickness (h) is equal to
VON ≈ −1.4 · h [nm] + 16.3 [V],
(4.2)
for h ≤ 20 nm.
OF F
appears to exhibit two types of behavior with respect to h.
In Fig. 4.7(c), ID
OF F
- h relationship yields
From 10 - 50 nm, a linear regression of ID
OF F
ID
≈ 0.12 · h [nm] + 9.2 [pA],
(4.3)
OF F
- h can be fit to
while below 10 nm ID
OF F
ID
≈ 1.1 · h [nm] − 1.4 [pA].
(4.4)
34
Figure 4.7: Extracted a-IGZO TFT log(ID ) − VG transfer curve parameters as a
function of channel layer thickness (h). (a) Subthreshold swing (S) and state density
due to bulk conduction bandtail states (DT A ) and interface states (traps) (Dit ), i.e.,
(DT A · h + Dit ) on left and right axes, respectively, (b) turn-on voltage (VON ), and
OF F
(c) drain current off current (ID
) @ VG = VON .
35
4.2 Channel Thickness: Discussion
The experimental trends shown in Fig. 4.7 and summarized in Table 4.1 are
OF F
quantitatively analyzed. A quantitative model is discussed for VON and ID
trends
and potential physical mechanisms are proposed.
4.2.1 Subthreshold Swing
As evident from Fig. 4.7(a), a linear relationship appears to exist between S
and h over the channel layer thickness range of 5 - 50 nm. A linear regression fit,
as shown in Eq. 4.1, leads to an estimated slope and intercept of 6.3 mV/(dec ·
nm) and 92 mV/dec, respectively. By redefining the y-axis of S, these two values
can be correlated to a volume trap density in the bulk a-IGZO film (DT A ) and an
area density of traps at the a-IGZO/SiO2 interface (Dit ) [32, 33], as discussed in the
following.
Recall from Eq. 3.2 [32,33,41] that the subthreshold swing (S) may be expressed
as
kB T
S = ln(10)
q
q(DT A · h + Dit )
1+
,
CG
(3.2)
where CG is the gate insulator capacitance density (34.5 nF/cm2 for 100 nm of SiO2 ).
Further algebraic manipulation results in
⇒
S·q
CG
−1
= DT A · h + Dit .
ln(10) · kB T
q
(4.5)
Plotting S as prescribed by the left side of Eq. 4.5 results in the DT A · h + Dit curve
36
Source
Eq. 4.6
Eq. 4.7
[42]
[43]
h (nm)
5 - 50
2
5 - 30
-
SiO2 tins (nm)
100
100
180
-
RF power (W)
75
75
70
-
Ar/O2 (sccms)
9/1
9/1
19.4/0.6
-
Pressure (mTorr)
5
5
4.1
-
Anneal
400 ◦ C 1 hour air
◦
400 C 1 hour air
No anneal
-
S (V/dec) DT A (cm−3 eV−1 )
0.13 - 0.41
2.3 × 1017
0.35
0.4 - 0.52
1.3 × 1018
-
Dit (cm−2 eV−1 )
1.2 × 1011
1.1 × 1012
2.8 × 1012
4.3 × 1012
Table 4.2: Extracted, experimental43 , and theoretical44 estimates of DT A and Dit ,
with corresponding process conditions: channel layer thickness (h), gate dielectric
thickness (tins ), RF power, Ar and O2 process gas ratio, deposition pressure, and
anneal temperature, duration, and environment.
shown in Fig. 4.7(a). The linear regression fit associated with this curve is given by
DT A · h + Dit = 2.3 × 1017 cm−3 eV−1 · h [nm] + 1.18 × 1011 cm−2 eV−1 ,
(4.6)
with a correlation coefficient of R2 = 0.99. These estimates of DT A and Dit are
approximately one order of magnitude smaller than the DT A = 1.3 × 1018 cm−3 eV−1
and Dit = 2.8 × 1012 cm−2 eV−1 experimental values reported previously [42] and the
Dit = 4.3 × 1012 cm−2 eV−1 estimate of Wager et al. obtained via induced gap state
modeling of the a-IGZO/SiO2 interface [43–46].
The lower values of DT A and Dit estimated in this thesis, compared to those
reported in reference [42], are indicative of a lower defect density within the bulk and
at the a-IGZO/SiO2 interface. The two major processing differences between a-IGZO
films deposited in this thesis and in reference [42] involve the Ar/O2 process gas ratio
and the post-deposition anneal temperature. Since no post-deposition anneal was
used in reference [42], it is likely that the use of a post-deposition anneal (400 ◦ C) in
this work is the dominant effect. Other groups have shown that an anneal performed
at a temperature greater than 300 ◦ C reduces trap formation in a-IGZO films [23, 24,
47]. While the process used in reference [42] was claimed to be optimized with an
37
Ar/O2 ratio of 19.4/0.6, thus removing the need for an anneal, it appears that the
lack of a post-deposition anneal resulted in a higher trap concentration within the
layer and at the a-IGZO/SiO2 interface compared to a-IGZO films reported herein
which were annealed at 400 ◦ C.
The above estimated values for DT A and Dit in Eq. 4.6 do not apply for an
a-IGZO film with h = 2 nm, as the S behavior at this point deviates significantly
from the linear regression fit. Estimating Dit separately for S(2 nm) = 0.35 V/dec
using
Dit =
CG
S · log(e)
−1
,
kB T /q
q
(4.7)
results in Dit = 1.1 × 1012 cm−2 eV−1 , indicating an order of magnitude increase
in interface state density for this 2 nm thick a-IGZO film. A 2 nm thick a-IGZO
channel layer is so thin that the accumulation layer formed likely extends throughout
the entirety of the a-IGZO channel layer thickness [48]. Therefore, the increase in
the extracted Dit is likely due to an overestimation, since it may be account for traps
located in the ‘bulk’, at the backside surface, in addition to the interface.
4.2.2 Turn-on Voltage Quantitative Analysis
In Fig. 4.7(b), there appear to be two separate regimes of VON behavior with
respect to h. In the first regime, VON remains near zero volts for 11 < h < 50 nm.
For the second regime, in which h < 11 nm, VON increases in an approximately linear
fashion with respect to decreasing h. This increasing trend is described by the linear
regression fit specified in Eq. 4.2.
38
Quantitative analysis of VON begins with use of the discrete acecptor-like trap
model [40]
VON =
−q
(nco + nto ) ,
CG
(4.8)
where nco is the equilibrium (zero-bias) conduction band density (cm−2 ) and nto is the
equilibrium density of occupied acceptor-like traps (cm−2 ). Since all TFTs reported
in this thesis have demonstrated enhancement-mode behavior, it can be assumed that
nco is negligibly small. Solving for nto yields
nto = −
VON CG
,
q
(4.9)
where substituting VON with the linear regression fit from Eq. 4.2 leads to
nto =
1.4 · CG
16.3 · CG
h−
,
q
q
−2
+
−
nto = ND,channel
[cm−3 ] · h − NA,surf
ace [cm ].
(4.10)
(4.11)
The units and polarity of the slope term (1.4CG /q) and intercept term (16.3CG /q) in
Eq. 4.10 imply that the slope corresponds to a donor-like trap in the bulk portion of
+
the channel (ND,channel
) while the intercept corresponds to a sheet density of acceptor−
like traps at the backside surface (NA,surf
ace ) of the a-IGZO film. Evaluation of
+
−
Eqs. 4.10 and 4.11 results in ND,channel
= 3.1 × 1018 cm−3 and NA,surf
ace = −3.5 ×
1012 cm−2 . Discussion of these trap values is deferred to Section 4.2.4.
39
4.2.3 OFF Drain Current Quantitative Analysis
Similar to the VON − h trend observed in the last section, there appears to be two
OF F
separate regimes of ID
behavior with respect to h (Fig. 4.7 (c)). As h decreases
OF F
below 11 nm, ID
decreases more precipitiously than when h is larger. These two
trends are described by the linear regression fits specified in Eq. 4.3 and 4.4.
OF F
ID
can be described quantitatively as [49]:
OF F
ID
=
σW h
VD ,
L
(4.12)
where σ is the conductivity of the a-IGZO channel layer (σ = qµn n, where µn is
the electron mobility and n is the free electron concentration), W , L, and VD are
the width and length of the channel layer, and applied drain voltage, respectively.
Substituting σ into Eq. 4.12 and solving for n gives
n=
OF F
L
ID
,
W hVD qµn
(4.13)
OF F
= mh + b) results in
and substitution of the linear regression fit (ID
n=
Lm
Lb
+
.
W VD qµn hW VD qµn
(4.14)
Furthermore, the free electron concentration (n) can be expressed in terms of the
charge neutrality relationship, which dictates that positive and negative charge must
P
P
be equal (i.e., + = − ). In the context of this analysis, only free electrons (n),
+
−
donor-like (ND,channel
) and acceptor-like backside surface (NA,surf
ace ) traps are con-
40
sidered, so that charge neutrality considerations leads to
−3
n (cm ) =
+
ND,channel
−
NA,surf
ace
(cm−3 ),
(cm ) −
−7
h(10 cm)
−3
(4.15)
Equating Eq. 4.14 and 4.15 results in
+
ND,channel
(cm−3 ) =
Lm
,
W VD qµn
(4.16)
−2
−
NA,surf
ace (cm ) =
Lb
.
W VD qµn
(4.17)
and
Using Eqs. 4.16 and 4.17 in conjunction with the slopes (m) and intercepts
(b) extracted from linear regression in Fig. 4.7(c), it is found that for h > 11 nm,
+
−
11
ND,channel
= 3.8 × 1016 cm−3 and NA,surf
cm−2 . For h < 11 nm,
ace = 2.9 × 10
+
−
11
ND,channel
= 2.3 × 1018 cm−3 and NA,surf
cm−2 .
ace = 2.9 × 10
+
Note that the field effect mobilities (µF E ) used in calculating ND,channel
and
−
NA,surf
ace are not the same mobilities reported in Table 4.1. It is known that mobility
is degraded as VG decreases, since a less accumulated channel exposes more empty
trap states, hindering electron transport. Since the values of µF E reported in Table
4.1 are taken at a gate overvoltage of 5 V above VON , these mobilities would not
OF F
calculations taken at a gate voltage just below VON . Thus,
be consistent with ID
+
−
µF E values used in the calculation of ND,channel
and NA,surf
ace must correspond to a
gate voltage of VG = VON (i.e., µF E |VG ≈VON ). For h > 11 nm and h < 11 nm, the
µF E |VG ≈VON values are 2 × 10−4 cm2 /V−1 s−1 and 3 × 10−5 cm2 /V−1 s−1 , respectively.
41
4.2.4 Two-layer Model
A two-layer model for unpassivated a-IGZO TFTs is proposed in Fig. 4.8. This
+
−
model is based upon the trap values estimated for ND,channel
and NA,surf
ace as obtained
OF F
from the experimental VON −h and ID
−h trends for a-IGZO TFTs with 2 < h < 50
+
−
OF F
nm. ND,channel
and NA,surf
−h trends is discussed
ace estimation from VON −h and ID
OF F
in detail in Section 4.2.2 and 4.2.3, respectively. Both the VON − h and the ID
−h
trend shown in Fig. 4.7 show a distinct change in behavior for a channel thickness
of ∼ 11 nm. This abrupt change in behavior at h ≈ 11 nm shown in Fig. 4.7(b) for
OF F
− h is the experimental impetus for development
VON − h and in Fig. 4.7(c) for ID
of the two-layer model.
Figure 4.8: A two-layer model for unpassivated a-IGZO TFTs.
As shown in Fig. 4.8, the two-layer model asserts that the ∼ 11 nm thick nearbackside-surface portion of the a-IGZO channel layer is different than that of the
remaining near-gate-insulator-interface portion of the channel layer (typically ∼ 39 nm,
for a baseline h ≈ 50 nm) since the empty donor-like trap density is approximately
42
two orders of magnitude larger here.
+
Note that the ND,channel
= 3.8 × 1016 cm−3 estimate for the near-gate-insulator-
interface portion of the a-IGZO channel is similar to the 6.5 × 1016 cm−3 value using
in Silvaco TCAD simulations of a-IGZO TFTs [50]. As discussed in Section 4.2.3,
+
these values are approximately two orders of magnitude lower than the ND,channel
=
+
3 × 1018 cm−3 and ND,channel
= 2.3 × 1018 cm−3 estimates for the near-backside-
surface portion of the a-IGZO channel as obtained from the VON − h trend of Fig.
OF F
4.7(b) and the ID
− h trend of Fig. 4.7(c). As indicated in Fig. 4.8, the other
component of the two-layer model is a filled acceptor-like surface trap whose density
−
12
is estimated as NA,surf
cm−2 from the VON − h trend of Fig. 4.7(b) or
ace = 3.5 × 10
−
11
OF F
as NA,surf
− h trend of Fig. 4.7(c). It is suspected
cm−2 from the ID
ace = 2.9 × 10
that the VON − h trend is the more accurate estimate, given the uncertainty of the
µF E estimate for a small gate voltage near VON .
+
−
Although atomic identification of ND,channel
and NA,surf
ace cannot unambiguously
be established at this time, the obvious candidates would be an oxygen vacancy within
the a-IGZO channel and oxygen adsorption at the backside surface, as discussed in
the next subsection.
4.2.5 Oxygen Adsorption Model
In the two-layer trap model discussed previously, there is a significant concentration of acceptor-like traps at the a-IGZO back surface. Since a-IGZO TFTs presented
in this thesis are unpassivated (i.e., exposed to ambient atmosphere), the origin of
these acceptor-like backside surface traps most likely involves oxygen adsorption at
43
the a-IGZO backside surface. The process of oxygen adsorption is depicted in the
following energy band diagrams (Fig. 4.9). Initially, (a) an O2 molecule comes to
rest (physisorbed) on the back surface of an intrinsic, bulk a-IGZO layer, creating an
empty neutral acceptor-like trap. Secondly, (b) the O2 molecule is thermally activated
(EA ≈ 0.72 eV [51]) and a free electron from the conduction band (Ec ) is captured
by the O2 molecule (chemisorption), creating a filled negatively charged acceptor-like
trap. As a result of this capture, a depletion layer of electrons is formed at the aIGZO backside surface, represented by upward band bending. If it is assumed that
the depletion of the backside does not change, it can seen that a (c) thicker channel
layer will not be as depleted compared to (d) a ultra-thin channel layer.
Relating to the increasing VON − h trend as h is thinned down below 11 nm, the
close proximity of the backside depletion to the insulator/semiconductor interface
can result in emptying of trap states at/near the interface. These empty trap states
must be filled before the formation of an accumulation layer is possible. Therefore,
a positive gate bias (i.e. positive VON ) is necessary in order fill exposed trap states
and form an accumulation layer. As h decreases further, the amount of exposed trap
states can increase, necessitating an even larger positive gate bias in order to fill those
traps prior to forming an accumulation layer.
It is proposed that O2 adsorption at the backside surface also contributes to
OF F
the overall decreasing trend observed in ID
− h. Chemisorbed O2 will deplete the
OF F
a-IGZO backside surface, decreasing the conductivity of the film, and hence, ID
.
OF F
For h < 11 nm, the more precipitous decrease in ID
compared to thicker channel
layers is attributed to the fact that the depletion from the backside surface extends
44
Figure 4.9: Energy band diagram depicting oxygen adsorption on an unpassivated
a-IGZO surface. (a) A neutral oxygen molecule (O2 ) is physisorbed on the surface,
creating a empty neutral acceptor-like trap. (b) Thermal excitation of the physisorbed
O2 and free electron capture from the conduction band, Ec , results in a chemisorbed
negatively charged O2 , acting as a filled negative acceptor-like trap. (c) Partial depletion or (d) full depletion is dependent on the thickness of the a-IGZO channel
layer.
throughout the entirety of the thin a-IGZO layer. For thicker a-IGZO films (h > 11
nm), the effect of this backside surface depletion is less influential due to the partial
depletion of the channel.
45
4.3 Thin Channel Process Development
In Section 4.1, it is shown that decreasing the channel layer thickness in an aOF F
IGZO TFT resulted in an improvement in the S, ID
, and µF E . However, a-IGZO
TFTs thinner than 11 nm also exhibit a large undesirable positive shift in VON . This
section presents results of 5 nm thick a-IGZO TFTs where the positive shift in VON
is eliminated
Splits of 5 nm thick a-IGZO TFTs were fabricated in the same manner as TFTs
fabricated under the channel layer thickness study. Fabrication began using a p-type
Si substrate with 100 nm of SiO2 as gate dielectric and Ta/Au as a back contact. 5 nm
thick a-IGZO deposition conditions match baseline (i.e., 5 mTorr sputtering pressure,
75 W RF Power), with the exception of Ar/O2 process gas ratio and post-deposition
annealing temperature. Source and drain electrodes are defined by shadow mask,
using thermally evaporated Al. Final TFT dimensions are W/L = 2000 µm /200 µm.
Figure 4.10 shows the transfer curves measured for h = 5 nm thick a-IGZO TFTs
fabricated under varied Ar/O2 process gas ratio and TA . A baseline 5 nm thick aIGZO TFT fabricated with Ar/O2 = 9/1 and a TA = 400 ◦ C exhibits enhancementmode behavior with VON = 9.9 V. While maintaining the same TA = 400 ◦ C, the
second split was deposited in a pure-Ar ambient (Ar/O2 = 10/0), which resulted in a
negative shift in VON to 3.9 V. Finally, 5 nm a-IGZO TFTs deposited with pure-Ar
ambient and a lowered annealing temperature (TA = 150 ◦ C) exhibited VON = 0 V.
Table 4.3 shows a summary of the observed transfer curve performance and relevant
process parameters for the various 5 nm thick a-IGZO TFTs.
The goal of process development for 5 nm thick a-IGZO TFTs was to shift VON
46
Figure 4.10: Logarithm of the drain current versus gate voltage (log(ID )−VG ) transfer
behavior of an a-IGZO TFT with a channel layer thickness of 5 nm. Modifications to
the baseline process include pure Ar process gas and a significantly decreased anneal
temperature of 150 ◦ C. Duration of the anneal and other process parameters remain
ON −OF F
unchanged. VON = 0.1 V, S = 90 mV/dec, ID
= 2.0 × 105 .
to 0 V, effectively making it independent of h. In Section 4.2.4, the two-layer model
suggests that the positive trend observed in VON − h was determined by donor-like
trap states in the bulk and acceptor-like trap states at the backside surface. This
suggests two routes for making VON independent of h, (1) an increase in the density
of donor-like bulk trap states and (2) a decrease in the sheet density of acceptor-like
back surface trap states.
It is hypothesized that an increase in the density of donor-like bulk trap states
can be accomplished by reducing or eliminating the oxygen partial pressure (Ar/O2
= 10/0) during sputter deposition. There have been many studies reporting that
47
h (nm) Ar/O2
5
9/1
5
10/0
5
10/0
TA (◦ C) VON (V) µF E (cm2 V−1 s−1 )
400
9.9
11
400
3.9
11
150
0
9
ON −OF F
S (mV/dec) ID
(A)
130
1.0 × 106
170
1.0 × 106
90
6.6 × 105
Table 4.3: Extracted log(ID ) − VG transfer curve parameters for a-IGZO TFTs with
varied Ar/O2 process gas ratio and anneal temperature (TA ). Duration of the anneal,
sputtering pressure = 5 mTorr and RF power = 75 W were unchanged.
a reduction of oxygen partial pressure induces oxygen vacancies (Vo ) in ZnO-based
films [52–54]. The presence of oxygen vacancies can act as shallow donor-like traps,
contributing free electrons to the conduction band, as represented by the following
reaction [27, 55]
1
Oox = O2 (g) + Vo·· + 2e− ,
2
(4.15)
where Vo·· and 2e− represent a double positive oxygen vacancy and 2 free electrons,
respectively. In the context of an a-IGZO channel layer, it is thought that reducing
oxygen partial pressure increases donor-like trap states within the a-IGZO bulk (i.e.,
oxygen vacancies), resulting in a decrease in VON , as is shown in Fig. 4.10.
It is found that further decrease in VON is obtained by decreasing the anneal
temperature. It is hypothesized that this decrease in VON with decreasing TA may
be related to a decrease in the sheet density of acceptor-like backside surface traps,
as identified by the two-layer model, where the physical mechanism of acceptor-like
trap formation was due to chemisorbed O2 molecules at the exposed a-IGZO backside
surface (Fig. 4.9).
In conclusion, by altering the sputtering process gas ratio of Ar/O2 from 9/1 to
10/0 and reducing the anneal temperature from 400 to 150 ◦ C, a h = 5 nm a-IGZO
48
TFT is demonstrated with VON ≈ 0 V, field-effect mobility of µF E = 9 cm−2 V−1 s−1 ,
ON −OF F
subthreshold slope of S = 90 mV/dec, and drain current on-to-off ratio of ID
=
2.0 × 105 . Improvement in VON performance compared to samples fabricated using
baseline process conditions is attributed to an increase (decrease) in the density of
donor-like bulk trap states (acceptor-like back surface trap states) obtained by reducing the oxygen partial pressure during sputtering and a reduction in the postdeposition anneal temperature.
49
Chapter 5: Conclusion and Recommendations for Future Work
5.1 Conclusions
The objective of the research reported in this thesis was to explore the effect
of decreasing channel layer thickness (h) on a-IGZO TFT transfer curve (ID − VG )
characteristics. Initial baseline process conditions for a-IGZO deposition were as
follows: process gas ratio of Ar/O2 = 9/1, deposition pressure of 5 mTorr, RF power
of 75 W, and post-deposition anneal of 400 ◦ C for 1 hour in air. The resulting 50 nm
thick a-IGZO TFTs exhibited VON = 0 V, µF E = 7.5 cm2 V−1 s−1 , S = 410 mV/dec,
ON −OF F
and ID
= 1.9 × 105 .
Using the aforementioned baseline process conditions, multiple a-IGZO TFTs
with varying channel thickness (2 < h < 50 nm) were fabricated. It was found that
good quality transfer curve performance could be maintained in unpassivated a-IGZO
TFTs with a channel layer thickness as thin as ∼ 2 nm. Below a channel layer thickness
of 11 nm, an approximately linear increase in VON was observed. This VON − h trend
was attributed to a large density (3.5 × 1012 cm−2 ) of backside surface acceptor-like
traps and an enhanced density (3 × 1018 cm−3 ) of donor-like bulk trap states within
the upper
∼
11 nm portion of the a-IGZO channel from the backside surface. As
OF F
h < 11 nm, ID
decreases more precipitously than when h > 11 nm. This more
OF F
precipitous decrease in ID
when h < 11 nm was ascribed to the backside surface
acceptor-like traps and the closer physical proximity of the backside surface when the
50
channel layer is ultra-thin. A two-layer model was proposed based on quantitative
OF F
analysis of trap densities extracted from the VON − h and ID
trends for a-IGZO
TFTs with 2 < h < 50 nm.
Process development of 5 nm thick a-IGZO TFTs was demonstrated. By altering
the process parameters of gas ratio of Ar/O2 from 9/1 to 10/0 and reducing the
post-deposition anneal temperature from 400 to 150 ◦ C, a h = 5 nm a-IGZO TFT is
obtained which exhibits transfer curve parameters of VON ≈ 0 V, field-effect mobility
ON −OF F
of µF E = 9 cm−2 V−1 s−1 , subthreshold slope of S = 90 mV/dec, and ID
=
2.0 × 105 . Insight from the two-layer model reveals that the negative shift in VON can
be attributed to an increase (decrease) in the density of donor-like bulk trap states
(acceptor-like back surface trap states).
5.2 Recommendations for Future Work
Clearly, the influence of gas adsorption at the exposed a-IGZO backside surface
is shown to have both positive and negative effects on a-IGZO TFT behavior. If the
application of a-IGZO TFTs for backplane logic is to become feasible, exploration
must be done on potential passivation layers. A critically important requirement
of this passivation layer is that it must be gas impermeable, in order to protect
the a-IGZO channel layer. Work done on induced-gap state modeling has proposed
SiO2 and Zn-Sn-Si-O (ZTSO) as two potentially promising candidates for a-IGZO
passivation [43]. Additionally, work done by Ken Hoshino and Eric Sundholm have
shown that a ZTSO passivation layer does suppress negative-bias-illumination-stress
(NBIS) induced instabilities in a-IGZO TFTs [56,57]. It is mentioned that the process
51
is unoptimized, as the yield of working a-IGZO TFTs suffers. Further work with
ZTSO could involve process optimization of the sputtering power, target-substrate
throw distance, sputtering process gas and deposition pressure, etc. Other groups
have also published work on passivation of a-IGZO TFTs [58, 59].
It is known that one can increase the mobility of a-IGZO by increasing the indium
content. However, doing so typically results in strongly depletion-mode TFTs due to a
significant increase in electron concentration in the channel. As demonstrated in this
work, the VON − h trend for ultra-thin TFTs shifts positively with decreasing channel
layer thickness. Thus one could exploit this trend and fabricate TFTs with ultrathin indium-rich channel layers in order to gain higher mobility while maintaining
near-zero VON .
52
APPENDICES
53
Appendix A: Shadow Mask Specifications
Specifications of shadow masks used in defining the channel and source/drain
contacts of TFTs presented in this thesis.
Figure A.1: ‘Clamping’ mask used in channel set. Mask is composed of 10 mil thick,
laser-cut, stainless steel.
Figure A.2: ‘Patterning’ mask used in channel set. Mask is composed of 2 mil thick,
electroplated Ni.
54
Figure A.3: ‘Clamping’ mask used in source/drain contact set. Mask is composed of
10 mil thick, laser-cut, stainless steel.
Figure A.4: ‘Patterning’ mask used in source/drain contact set. Mask is composed
of 2 mil thick, electroplated Ni.
55
Appendix B: Mobility Extraction
µF E versus VG plots, µF E values reported in Table 4.1 were taken at VG = VON + 5
V.
Figure B.1: µF E versus VG plot for 50 nm a-IGZO TFT
56
Figure B.2: µF E versus VG plot for 20 nm a-IGZO TFT
Figure B.3: µF E versus VG plot for 10 nm a-IGZO TFT
57
Figure B.4: µF E versus VG plot for 5 nm a-IGZO TFT
Figure B.5: µF E versus VG plot for 2 nm a-IGZO TFT
58
Bibliography
[1] W. den Boer, Active Matrix Liquid Crystal Displays. Elsevier Inc.
[2] Y. Kaneko, A. Sasano, and T. Tsukada, “Characterization of instability in amorphous silicon thin-film transistors,” J Appl Phys, vol. 69, no. 10, pp. 7301–7305,
1991.
[3] M. Stutzmann, W. Jackson, and C. Tsai, “Light-induced metastable defects in
hydrogenated amorphous silicon: a systematic study,” Phys Rev B, vol. 32, no. 1,
pp. 23–47, 1985.
[4] K. Karim, A. Nathan, M. Hack, and W. Milne, “Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs,” IEEE Electron Device Lett,
vol. 25, no. 4, pp. 188–190, 2004.
[5] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Roomtemperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488–492, 2004.
[6] H. Hosono, “Ionic amorphous oxide semiconductors: Material design, carrier
transport, and device application,” Journal of Non-Crystalline Solids, vol. 352,
pp. 851–858, June 2006.
[7] J. Lilienfield, “Method and apparatus for controlling electric currents.” U.S.
Patent 1,745,175, 1930.
[8] J.-H. Lee, D. Liu, and S.-T. Wu, Introduction to Flat Panel Displays. West
Sussex, U.K.: John Wiley & Sons Ltd., 2008.
[9] H. Q. Chiang, “Development of zinc tin oxide based thin-film transistors,” M.S.
thesis, Oregon State University, 2003.
[10] R. Hoffman, “ZnO-channel thin-film transistors: Channel mobility,” J. Appl.
Phys., vol. 95, no. 10, p. 5813, 2004.
[11] J. Wager and B. Yeh, “Oxide thin-film transistors – device physics,”
59
[12] C. Granqvist and A. Hultker, “Transparent and conducting ITO films: new
developments and applications,” Thin Solid Films, vol. 411, no. 1, pp. 1 – 5,
2002. Proceedings of the 2nd International Symposium on Transparent Oxide
Thin Films for Electronics and Optics.
[13] T. Chou, K. Y. Cheng, T. L. Chang, C. J. Ting, H. C. Hsu, C. J. Wu, J. H.
Tsai, and T. Y. Huang, “Fabrication of antireflection structures of TCO film
for reflective liquid crystal display,” Microelectron Engineering, vol. 86, no. 4-6,
p. 628, 2009.
[14] C. G. Granqvist, “Transparent conductive electrodes for electrochromic devices:
A review,” Appl. Phys., vol. 57, no. 1, p. 19, 1993.
[15] W. J. Jeong, S. K. Kim, and G. C. Park, “Preparation and characteristic of ZnO
thin film with high and low resistivity for an application of solar cell,” Thin Solid
Films, vol. 0, no. 180, pp. 506–507, 2006.
[16] D. C. Giancoli, Physics: Principles with Applications. London: Prentice Hall,
4th ed., 1995.
[17] H. Kim, C. M. Gilmore, A. Piqu, J. S. Horwitz, H. Mattoussi, H. Murata, Z. H.
Kafafi, and D. B. Chrisey, “Electrical, optical, and structural properties of indiumtinoxide thin films for organic light-emitting devices,” Journal of Applied
Physics, vol. 86, no. 11, 1999.
[18] W. E. Spear and P. G. Le Comber, “Substitutional doping of amorphous silicon,”
Solid State Communications, vol. 17, pp. 1193–1196, Nov. 1975.
[19] H. Hosono, M. Yasukawa, and H. Kawazoe, “Novel oxide amorphous semiconductors: transparent conducting amorphous oxides,” Journal of Non-Crystalline
Solids, vol. 203, pp. 334–344, Aug. 1996.
[20] T. Kamiya, K. Nomura, and H. Hosono, “Recent progress in amorphous oxide
semiconductors and thin film transistors,” Meeting Abstracts, vol. MA2006-02,
pp. 1598–1598, June 2006.
[21] M. Ohring, The Materials Science of Thin Films. San Diego, California: Academic Press, 1st ed., 1992.
[22] S. Wolf, Silicon Processing for the VLSI Era, vol. 2. Sunset Beach, California:
Lattice Press, 1990.
60
[23] H. Q. Chiang, B. R. McFarlane, D. Hong, R. E. Presley, and J. F. Wager,
“Processing effects on the stability of amorphous indium gallium zinc oxide thinfilm transistors,” Journal of Non-Crystalline Solids, vol. 354, pp. 2826–2830,
May 2008.
[24] K. Nomura, T. Kamiya, M. Hirano, and H. Hosono, “Origins of threshold voltage
shifts in room-temperature deposited and annealed a-InGaZnO thin-film transistors,” Applied Physics Letters, vol. 95, p. 013502, July 2009.
[25] K. H. Ji, J.-I. Kim, H. Y. Jung, S. Y. Park, R. Choi, U. K. Kim, C. S. Hwang,
D. Lee, H. Hwang, and J. K. Jeong, “Effect of high-pressure oxygen annealing
on negative bias illumination stress-induced instability of InGaZnO thin film
transistors,” Applied Physics Letters, vol. 98, p. 103509, Mar. 2011.
[26] X. Li, E. Xin, L. Chen, J. Shi, C. Li, and J. Zhang, “Dependence of annealing
on stability of transparent amorphous InGaZnO thin film transistor,” Materials Science in Semiconductor Processing, vol. 16, pp. 1292–1296, Oct. 2013.
WOS:000322054200015.
[27] S. Hwang, J. H. Lee, C. H. Woo, J. Y. Lee, and H. K. Cho, “Effect of annealing
temperature on the electrical performances of solution-processed InGaZnO thin
film transistors,” Thin Solid Films, vol. 519, pp. 5146–5149, May 2011.
[28] K.-S. Kim, S.-W. Lee, S.-M. Oh, and W.-J. Cho, “Development of annealing
process for solution-derived high performance InGaZnO thin-film transistors,”
Materials Science and Engineering B-Advanced Functional Solid-State Materials,
vol. 178, pp. 811–815, July 2013. WOS:000320414800001.
[29] K. Nomura, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, “Defect passivation and homogenization of amorphous oxide thin-film transistor by wet o2
annealing,” Applied Physics Letters, vol. 93, p. 192107, Nov. 2008.
[30] S.-I. Oh, G. Choi, H. Hwang, W. Lu, and J.-H. Jang, “Hydrogenated IGZO thinfilm transistors using high-pressure hydrogen annealing,” IEEE Transactions on
Electron Devices, vol. 60, pp. 2537–2541, Aug. 2013. WOS:000322124100016.
[31] R. Hoffman, “Effects of channel stoichiometry and processing temperature on
the electrical characteristics of zinc tin oxide thin-film transistors,” Solid-State
Electronics, vol. 50, no. 5, pp. 784 – 787, 2006.
61
[32] D. W. Greve, Field Effect Devices and Applications: Devices for Portable, Lowpower, and Imaging Systems. Upper Saddle River, NJ, USA: Prentice-Hall, Inc.,
1998.
[33] C. R. Kagan and P. Andry, Thin-Film Transistors. New York, U.S.A: Marcel
Dekker, 2003.
[34] D.-Y. Cho, J. Song, K. D. Na, C. S. Hwang, J. H. Jeong, J. K. Jeong, and Y.-G.
Mo, “Local structure and conduction mechanism in amorphous InGaZnO films,”
Applied Physics Letters, vol. 94, no. 11, pp. –, 2009.
[35] P. Gorrn, P. Holzer, T. Riedl, W. Kowalsky, J. Wang, T. Weimann, P. Hinze, and
S. Kipp, “Stability of transparent zinc tin oxide transistors under bias stress,”
Applied Physics Letters, vol. 90, p. 063502, Feb. 2007.
[36] R. B. M. Cross, M. De Souza, S. Deane, and N. Young, “A comparison of the
performance and stability of ZnO-TFTs with silicon dioxide and nitride as gate
insulators,” IEEE Transactions on Electron Devices, vol. 55, pp. 1109–1115, May
2008.
[37] J.-M. Lee, I.-T. Cho, J.-H. Lee, and H.-I. Kwon, “Bias-stress-induced stretchedexponential time dependence of threshold voltage shift in InGaZnO thin film
transistors,” Applied Physics Letters, vol. 93, p. 093504, Sept. 2008.
[38] A. Suresh and J. F. Muth, “Bias stress stability of indium gallium zinc oxide
channel based transparent thin film transistors,” Applied Physics Letters, vol. 92,
p. 033502, Jan. 2008.
[39] K. Hoshino, D. Hong, H. Q. Chiang, and J. F. Wager, “Constant-voltage-bias
stress testing of a-IGZO thin-film transistors,” IEEE Transactions on Electron
Devices, vol. 56, pp. 1365–1370, July 2009.
[40] J. F. Wager, D. A. Keszler, and R. E. Presley, Transparent Electronics. New
York: Springer, 2008.
[41] A. Rolland, J. Richard, J. Kleider, and D. Mencaraglia, “Electrical properties
of amorphous silicon transistors and mis-devices: comparative study of top nitride and bottom nitride configurations,” Journal of the Electrochemical Society,
vol. 140, no. 12, pp. 3679–3683, 1993.
62
[42] L. Shao, K. Nomura, T. Kamiya, and H. Hosono, “Operation characteristics of
thin-film transistors using very thin amorphous ingazno channels,” Electrochemical and Solid-State Letters, vol. 14, pp. H197–H200, May 2011.
[43] J. F. Wager, K. Hoshino, E. S. Sundholm, R. E. Presley, R. Ravichandran,
C. C. Knutson, D. A. Keszler, R. L. Hoffman, D. A. Mourey, and J. Robertson,
“A framework for assessing amorphous oxide semiconductor thin-film transistor
passivation,” Journal of the Society for Information Display, vol. 20, no. 10,
pp. 589–595, 2012.
[44] J. Wager, “Transparent electronics: Schottky barrier and heterojunction considerations,” Thin Solid Films, vol. 516, no. 8, pp. 1755 – 1764, 2008.
[45] J. Spies, R. Schafer, J. Wager, P. Hersh, H. Platt, D. Keszler, G. Schneider,
R. Kykyneshi, J. Tate, X. Liu, A. Compaan, and W. Shafarman, “pin doubleheterojunction thin-film solar cell p-layer assessment,” Solar Energy Materials
and Solar Cells, vol. 93, no. 8, pp. 1296 – 1308, 2009.
[46] J. F. Wager and J. Robertson, “Metal-induced gap states modeling of metal-ge
contacts with and without a silicon nitride ultrathin interfacial layer,” Journal
of Applied Physics, vol. 109, no. 9, pp. –, 2011.
[47] T. T. Trinh, V. D. Nguyen, K. Ryu, K. Jang, W. Lee, S. Baek, J. Raja, and
J. Yi, “Improvement in the performance of an ingazno thin-film transistor by
controlling interface trap densities between the insulator and active layer,” Semiconductor Science and Technology, vol. 26, no. 8, p. 085012, 2011.
[48] G. Yaron, A. Many, and Y. Goldstein, “Quantized electron accumulation layers
on ZnO surfaces produced by low-energy hydrogen-ion implantation,” Journal
of Applied Physics, vol. 58, no. 9, p. 3508, 1985.
[49] S. Bang, S. Lee, J. Park, S. Park, W. Jeong, and H. Jeon, “Investigation of the
effects of interface carrier concentration on ZnO thin film transistors fabricated
by atomic layer deposition,” Journal of Physics D: Applied Physics, vol. 42,
p. 235102, Dec. 2009.
[50] B. Yeh, “Modeling and characerization of amorphous oxide semiconductor thinfilm transistors,” Ph. D. thesis, Oregon State University, 2015.
63
[51] J. Lagowski, E. S. S. Jr, and H. C. Gatos, “Quantitative study of the charge
transfer in chemisorption; oxygen chemisorption on ZnO,” Journal of Applied
Physics, vol. 48, pp. 3566–3575, Aug. 1977.
[52] H. Yabuta, M. Sano, K. Abe, T. Aiba, T. Den, H. Kumomi, K. Nomura,
T. Kamiya, and H. Hosono, “High-mobility thin-film transistor with amorphous
InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering,”
Applied Physics Letters, vol. 89, p. 112123, Sept. 2006.
[53] A. Suresh, P. Gollakota, P. Wellenius, A. Dhawan, and J. F. Muth, “Transparent,
high mobility InGaZnO thin films deposited by PLD,” Thin Solid Films, vol. 516,
pp. 1326–1329, Feb. 2008.
[54] M. Furuta, Y. Kamada, M. Kimura, T. Hiramatsu, T. Matsuda, H. Furuta,
C. Li, S. Fujita, and T. Hirao, “Analysis of Hump Characteristics in Thin-Film
Transistors With ZnO Channels Deposited by Sputtering at Various Oxygen
Partial Pressures,” IEEE Electron Device Letters, vol. 31, pp. 1257–1259, Nov.
2010.
[55] T. Kamiya, K. Nomura, M. Hirano, and H. Hosono, “Electronic structure of
oxygen deficient amorphous oxide semiconductor a-InGaZnO4x: Optical analyses
and first-principle calculations,” physica status solidi (c), vol. 5, no. 9, pp. 3098–
3100, 2008.
[56] K. Hoshino, “Fabrication process assessment and negative bias illumination stress
study of igzo and zto tfts,” Ph. D. thesis, Oregon State University, 2012.
[57] E. Sundholm, R. Presley, K. Hoshino, C. Knutson, R. Hoffman, D. Mourey,
D. Keszler, and J. Wager, “Passivation of Amorphous Oxide Semiconductors
Utilizing a Zinc #x2013;Tin #x2013;Silicon #x2013;Oxide Barrier Layer,” IEEE
Electron Device Letters, vol. 33, pp. 836–838, June 2012.
[58] M. Kim, J. H. Jeong, H. J. Lee, T. K. Ahn, H. S. Shin, J.-S. Park, J. K. Jeong, Y.G. Mo, and H. D. Kim, “High mobility bottom gate ingazno thin film transistors
with sio x etch stopper,” Applied Physics Letters, vol. 90, no. 21, pp. 212114–
212114, 2007.
[59] K. Nomura, T. Kamiya, and H. Hosono, “Stability and high-frequency operation
of amorphous InGaZnO thin-film transistors with various passivation layers,”
Thin Solid Films, vol. 520, pp. 3778–3782, Mar. 2012.