AN ABSTRACT OF THE DISSERTATION OF
Andrew R. Tabalujan for the degree of Master of Science in
Electrical and Computer Engineering presented on September 14, 2007.
Title: Test Fixture Characterization for High-Frequency
Silicon Substrate Parasitic Extraction
Abstract approved:
Dr. Terri Fiez
Dr. Karti Mayaram
At frequencies exceeding 1-2 GHz, the reactive nature of a silicon substrate
must be accounted in the substrate network models used in substrate coupling
simulation. High-frequency substrate models, containing reactive components,
must be validated through high-frequency network analyzer measurements.
Prior fabricated test fixtures have been modified to enable high-frequency
(up to 20 GHz) network parameter measurements of a 0.35 µm CMOS heavilydoped silicon substrate through an off-chip probing scheme. The performance of
the test fixture and the measurement deembedding procedure has been evaluated,
and suggestions for future improvements are presented.
A new probing scheme is proposed to enable high-frequency network parameter measurements of a silicon substrate. The design of the test structures
and the deembedding procedure has been validated through extensive simulations
in HFSS.
© Copyright by Andrew R. Tabalujan
September 14, 2007
All Rights Reserved
Test Fixture Characterization for High-Frequency Silicon Substrate Parasitic
Extraction
by
Andrew R. Tabalujan
A THESIS
submitted to
Oregon State University
in partial fulfillment of
the requirements for the
degree of
Master of Science
Presented September 14, 2007
Commencement June 2008
Master of Science
thesis
of
Andrew R. Tabalujan
presented
on
September 14, 2007
APPROVED:
Co-Major Professor, representing Electrical and Computer Engineering
Co-Major Professor, representing Electrical and Computer Engineering
Director of the School of Electrical Engineering and Computer Science
Dean of the Graduate School
I understand that my thesis will become part of the permanent collection of
Oregon State University libraries. My signature below authorizes release of my
thesis to any reader upon request.
Andrew R. Tabalujan, Author
ACKNOWLEDGMENTS
The work presented in this thesis could not have happened without the help
and support of many people. First and foremost, I am indebted to my advisors,
Professor Karti Mayaram and Professor Terri Fiez, for giving me the opportunity
of being part of their substrate noise coupling group. Prof. Karti Mayaram
introduced me to radio frequency circuit design. He was supportive and showed
unlimited patience in my efforts tackling the challenges in this research. Prof.
Terri Fiez provided guidance throughout this research; she believed in me from
the beginning of this work, and has been a source of encouragement throughout
its duration.
The people at Cascade Microtech, among them are Leonard Hayden and
Randy Fenton, provided guidance on high frequency measurement issues; their
insights overcame many mysteries in that field. Laudie Doubrava from Tektronix
provided insight of practical issues related to microwave, and helped me identify
problems that only experience can warn you about.
Jim Shaver, Yoshi Uematsu and Toni Hoodenpyl from Kyocera did an
amazing job of bonding the die. Much thanks also to Ed Swenson from ESI and
Steve Etringer from ONAMI for their support in modifying the test fixtures. I
would like to acknowledge SRC (Semiconductor Research Corporation), Intel Corporation and DARPA (Defense Advanced Research Projects Agency) for providing
the financial support for my research.
My colleagues at Oregon State University provided a great deal of technical assistance, and also enriched my experience with their friendships. Matthew
MacClary taught me many things about UNIX. Chris Hanken provided framework
setup to run Cadence platform. Bob Shreeve also provided practical insight, especially with respect to measurement validation. Sasidhar Lingam came to my aid
when I encountered problems with analog circuit issues. Peter Kurahashi helped
me through setting the links with GPIB box in the lab.
I would also like to thank Arthi Sundaresan, Brett Peterson, Chenggang
Xu, Dave Gubbins, Erik Geissenhainer, Jackie Wong, James Ayers, Jim Le, Josh
Carnes, Kavitha Srinivasan, Kye Hyung, Kyle Webb, Martin Held, Napong Panitantum, Robert Batten, Robert Gregoire, Sunwoo Kwon, Tawfiq Musah, Wai
Leng Cheong and all the other graduate students in the analog/mixed signal
group whom I did not previously mention.
Ferne Simendinger helped me through many administrative matters in the
EECS Department and did an excellent job as EECS Graduate Coordinator. Clara
Knutson guided me through the paperwork involved in my purchases.
Finally, I would like to thank my parents, Thomas and Grace, and my
brother, Jeffrey, for their love, support, and encouragement through these years
of graduate school. I thank God for bringing me through this experience; to Him
be the glory.
TABLE OF CONTENTS
Page
1
2
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1
Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Thesis Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
AN OVERVIEW OF PRIOR WORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.1
Off-Chip Probing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.2
Isolation Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
TEST FIXTURE MODIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
MEASUREMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Test Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Test Setup for Stable Calibration and Optimum SNR . . . . . . . . . . . . . . 17
4.3
Initial Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Shielding Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.2 On Chip Through Trace Deembedding . . . . . . . . . . . . . . . . . 20
4.3.3 Four Step Deembedding Result . . . . . . . . . . . . . . . . . . . . . . . 29
5
6
VALIDATION AND REVISED SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1
Resonance in Signal Return Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2
Lack of Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3
Incorrect Deembedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
NEW PROBING SCHEME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1
Probing Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.2
Probing Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
TABLE OF CONTENTS (Continued)
Page
7
CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
APPENDICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
APPENDIX A Test Fixture Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . 76
APPENDIX B EPIC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
APPENDIX C Deembedding on Rational Fitted Measurement Data . . . . . 82
APPENDIX D Matlab Deembedding Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
LIST OF FIGURES
Figure
Page
1.1 The substrate as a two-port network. . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2 Low-frequency resistive substrate network model. . . . . . . . . . . . . . . . .
3
1.3 High-frequency substrate network model. . . . . . . . . . . . . . . . . . . . . . .
4
2.1 Test fixture assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.2 Characterization structure of (a) chip mounted on test fixture,
(b) transmission lines, and (c) bondwires. . . . . . . . . . . . . . . . . . . . . .
8
2.3 Test fixture model used for deembedding. . . . . . . . . . . . . . . . . . . . . . .
9
2.4 Photograph of the test chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 S-parameters from the initial measurements, showing the failure of
the measurement and deembedding procedure. (a) S11 , (b) S21 . . . . . . 11
2.6 S-parameters from the initial simulations, revised simulations, and
measurements for the outer-most bondwire of the bondwire characterization structure from [8]. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . 12
3.1 Configurations of modified test fixtures for (a) on-chip through trace,
(b) on-chip empty contacts, (c) 10µm x 10µm contact, and (d) 10µm
x 60µm contact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Photomicrograph of the modified transmission line characterization
structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Side view of the high frequency measurement setup. . . . . . . . . . . . . . . 19
4.2 S-parameters from measurements and simulations of the on-chip
through trace structure for different spacing heights. (a) S11 , (b) S21 ,
(c) S12 , and (d) S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Simulated and measured S-parameters for the on-chip through trace
structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Simulated and measured S-parameters for the microstrip structure.
(a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5 Simulated and measured S-parameters for the bondwire characterization structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LIST OF FIGURES (Continued)
Figure
Page
4.6 Simulated and measured S-parameters for the bondwire characterization structure following the first deembedding step. (a) S11 after step
1, (b) S21 after step 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Simulated and measured S-parameters for the on-chip through trace
structure following the first deembedding step. (a) S11 after step 1,
(b) S21 after step 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.8 Simulated and measured S-parameters for the on-chip through trace
structure following the second deembedding step. (a) S11 after step
2, (b) S21 after step 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.9 Simulated and measured S-parameter data for the 10µm x 10µm substrate contacts at 20µm separation. (a) S11 , (b) S21 . . . . . . . . . . . . . . . 30
4.10 Simulated and measured S-parameter data for the 10µm x 10µm substrate contacts at 20µm separation following the first deembedding
step. (a) S11 after step 1, (b) S21 after step 1. . . . . . . . . . . . . . . . . . . . 31
4.11 Simulated and measured S-parameter data for the 10µm x 10µm substrate contacts at 20µm separation following the second deembedding
step. (a) S11 after step 2, (b) S21 after step 2. . . . . . . . . . . . . . . . . . . . 32
4.12 Simulated and measured S-parameter data for the 10µm x 10µm substrate contacts at 20µm separation following the third deembedding
step. (a) S11 after step 3, (b) S21 after step 3. . . . . . . . . . . . . . . . . . . . 34
4.13 Simulated and measured S-parameter data for the 10µm x 10µm substrate contacts at 20µm separation following the final deembedding
step. (a) S11 after step 4, (b) S21 after step 4. . . . . . . . . . . . . . . . . . . . 35
5.1 Signal return path of the on-chip through trace structure forming
(a) a long resonance loop, and (b) a parallel resonance loop. . . . . . . . 37
5.2 A transmission line terminated in (a) a short circuit, and (b) an open
circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3 Impedance variation along (a) a short circuited transmission line, and
(b) an open circuited transmission line. . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4 Quarter wavelength as a function of frequency. . . . . . . . . . . . . . . . . . . 40
5.5 S-parameters from simulation of the structure shown in Figure 5.1(b).
(a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LIST OF FIGURES (Continued)
Figure
Page
5.6 S-parameters from simulation of the structure shown in Figure 5.1(b)
with and without finite termination. (a) S11 , (b) S21 . . . . . . . . . . . . . . 42
5.7 Top view of on-chip through trace for modified probe structure. . . . . 43
5.8 Photomicrograph of the modified probe structure. . . . . . . . . . . . . . . . . 44
5.9 S-parameters from measurements of the on-chip through trace for
actual structure and modified probe structure. (a) S11 , (b) S21 , (c) S12 ,
and (d) S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.10 S-parameters from simulations and measurements of the on-chip
through trace for modified probe structure. (a) S11 , (b) S21 , (c) S12 ,
and (d) S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.11 S-parameters from simulations of the on-chip through trace for actual
structure and modified probe structure. (a) S11 , (b) S21 , (c) S12 , and
(d) S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.12 Half wavelength transmission line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.13 Half wavelength as a function of frequency. . . . . . . . . . . . . . . . . . . . . . 49
5.14 HFSS structure top view of on-chip through trace for (a) revised structure, (b) removed side ground metals, and (c) removed side ground
vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.15 S-parameters from simulation of structures shown in Figure 5.14.
(a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.16 HFSS structure of on-chip through trace (a) including probe pads and
vias, and (b) excluding probe pads and vias. . . . . . . . . . . . . . . . . . . . 52
5.17 Time domain response of the on-chip through trace structure.
(a) Time domain reflection. (b) Time domain transmission. . . . . . . . . 54
5.18 HFSS structure for simulation of discontinuity in the probe pad. . . . . 55
5.19 Time domain response of HFSS simulation for validating the discontinuity in the probe pad. (a) Time domain reflection. (b) Time domain
transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.20 HFSS simulation structure for simulation of a resistor embedded in
test fixture with no probe pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LIST OF FIGURES (Continued)
Figure
Page
5.21 HFSS simulation structure for simulation of a resistor embedded in a
test fixture with probe pads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.22 Simulated deembedded self and mutual admittances for the 1 kΩ resistor embedded in the structure shown in Figures 5.20 and 5.21.
(a) Self conductance, (b) self susceptance, (c) mutual conductance,
and (d) mutual susceptance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 New model used for deembedding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2 Vialess CPW-microstrip transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3 HFSS structure for simulation of a resistor embedded in the test structure suggested for future work. Structure for simulation of (a) resistor,
(b) on-chip empty structure, (c) on-chip through trace, and (d) open
dummy pad structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.4 Simulated S-parameters for a 1 kΩ resistor embedded in the on-chip
test structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.5 Simulated S-parameters for a 1 kΩ resistor following the first deembedding step. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.6 Simulated S-parameters for a 1 kΩ resistor following the second deembedding step. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.7 Simulated S-parameters for a 1 kΩ resistor following the final deembedding step. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.8 Simulated deembedded self and mutual admittances for the 1 kΩ resistor. (a) Self conductance, (b) self susceptance, (c) mutual conductance, and (d) mutual susceptance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.9 Simulated deembedded self and mutual admittances for the 10 kΩ
resistor. (a) Self conductance, (b) self susceptance, (c) mutual conductance, and (d) mutual susceptance. . . . . . . . . . . . . . . . . . . . . . . . . 70
B-1 Three-layer substrate used for simulation. . . . . . . . . . . . . . . . . . . . . . . 78
B-2 Simulated deembedded self and mutual admittances for a pair of
10µm x 10µm substrate contacts. (a) Conductance, and (b) susceptance to ground. Mutual (c) conductance, and (d) susceptance. . . 80
LIST OF FIGURES (Continued)
Figure
Page
B-3 Simulated deembedded self and mutual admittances for a pair of
10µm x 60µm substrate contacts. (a) Conductance, and (b) susceptance to ground. Mutual (c) conductance, and (d) susceptance. . . 81
C-4 Simulated and rational polynomial fit of measurement data for the
on-chip through trace structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . 83
C-5 Simulated and rational polynomial fit of measurement data for the
microstrip structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
C-6 Simulated and rational polynomial fit of measurement data for the
bondwire characterization structure. (a) S11 , (b) S21 . . . . . . . . . . . . . . 85
C-7 Simulated and rational polynomial fit of measurement data for the
bondwire characterization structure following the first deembedding
step. (a) S11 after step 1, (b) S21 after step 1. . . . . . . . . . . . . . . . . . . . 86
C-8 Simulated and rational polynomial fit of measurement data for the
on-chip through trace structure following the first deembedding step.
(a) S11 after step 1, (b) S21 after step 1. . . . . . . . . . . . . . . . . . . . . . . . 87
C-9 Simulated and rational polynomial fit of measurement data for the
on-chip through trace structure following the second deembedding
step. (a) S11 after step 2, (b) S21 after step 2. . . . . . . . . . . . . . . . . . . . 88
LIST OF TABLES
Table
Page
3.1 Dimensions of the modified two contacts test structures. . . . . . . . . . . . 14
TEST FIXTURE CHARACTERIZATION FOR
HIGH-FREQUENCY
SILICON SUBSTRATE PARASITIC EXTRACTION
1. INTRODUCTION
1.1. Background and Motivation
Due to a constant demand for portable electronics such as laptop computers, PDAs, cell phones and digital music players, the market for smaller, less expensive and more power efficient systems is soaring. This demand can be achieved
by higher levels of integration because of the numerous advantages in terms of reduced cost and size. As Moore’s law continues to predict integrated circuit (IC)
scaling, many systems that were previously realized on circuit boards are now
being integrated into a single die referred to as a system on chip (SoC). These
systems often require a combination of sensitive analog (including RF) circuitry
with a high-speed, noisy digital signal processing block, all integrated on a single
IC.
Many concerns arise when integrating analog, RF and digital electronic
building blocks on a common silicon substrate. One of these concerns is the noise
coupling from the digital circuitry to the analog and RF circuitry. This coupling
can occur through several interdependent paths, including power supplies, interconnect and package parasitics, and through the silicon substrate itself [1] [2].
Until recently, IC designers were forced to use rule-of-thumb guidelines in
an effort to minimize substrate noise coupling. However, rule-of-thumb guidelines
2
often led to either under or over engineered designs. A tool that solves substrate
noise coupling issues leads not only to better designs, but also reduces the time to
market. Silencer! is one such tool [3] developed at Oregon State University that
allows analysis and optimization of substrate noise coupling at different stages of
design. It enables IC designers to predict, through simulation, the coupling that
will occur between analog and digital blocks in a circuit [3].
p+
p+
-
+
Port 2
Port 1
+
p-type substrate
-
FIGURE 1.1. The substrate as a two-port network.
Since Silencer! does a noise coupling simulation based on an extracted substrate network, two-port network models for a given IC process are used in order
to accomplish the extraction of a substrate network from an IC layout. The twoport network itself comprises the silicon substrate surrounding two p+ contacts as
shown in Figure 1.1. The backside serves as a common reference node for both
ports. Based on the geometries of the substrate contacts under consideration,
these models are used to compute the network component values. It is essential
to have the means to validate the models through physical measurements.
At lower frequencies the models can be validated through DC resistance
measurements made on test structures laid out on a die, which consist of pairs of
p+ substrate contacts of various dimensions and spacings. The DC measurements
3
are valid since the substrate can be modeled as a purely resistive network at lower
frequencies, below 1-2 GHz as shown in [4].
The resistive substrate network connecting two p+ substrate contacts is
shown in Figure 1.2. In this π-network, Rmut represents the mutual resistance
between the two substrate contacts, while Rgnd,1 and Rgnd,2 represent the self
resistances of each contact to the back side of the die. DC resistance measurements
can then be made whereby the values of Rgnd and Rmut can be determined.
FIGURE 1.2. Low-frequency resistive substrate network model.
While the resistive network is adequate at lower frequencies, at higher
frequencies, in excess of 2 GHz, it becomes necessary to account for the dielectric
nature of the substrate. At these higher frequencies, a more accurate equivalent
substrate network would include both resistive and reactive components [5], [6].
A π-network for the high frequency model is shown in Figure 1.3 [7], with self and
mutual resistances being replaced by self and mutual admittances.
DC measurements no longer suffice, at frequencies exceeding 2 GHz, where
the two-port network begins to look reactive. It becomes necessary to characterize the two-port substrate network as a function of frequency. At higher frequencies, which are of interest here, the two-port network is best characterized
with scattering parameters (S-parameters). Based on its reference impedance,
4
the S-parameters are then converted back to short-circuit admittance parameters
(Y-parameters) for validating the developed models.
1
2
p+
p+
Ymut
Ygnd,1
Ygnd,2
p-type substrate
FIGURE 1.3. High-frequency substrate network model.
Substrate noise coupling at high frequencies, above 1-2 GHz, requires a
substrate network model that accounts for the reactive nature of the substrate.
At frequencies below 1 GHz or so, where the substrate can adequately be treated
as purely resistive, models can be validated with DC resistance measurements.
To enable accurate simulation of high-frequency substrate coupling effects in ICs,
model validation and development at higher frequencies requires the ability to
accurately measure, using a network analyzer, the two-port network parameters
between pairs of substrate contacts.
1.2. Thesis Outline
This thesis details the measurement and simulation of modified work designs for the characterization of the two-port substrate network, corresponding to
a pair of p+ substrate contacts for frequencies up to 20 GHz. Chapter 2 provides
an overview of the prior work in high-frequency substrate coupling measurements
and the basic measurement methodology that enables data extraction from mea-
5
surements. This data extraction process is known as deembedding. Also discussed
in Chapter 2 are the issues related to the prior design before any modifications.
Chapter 3 describes the modification of the test fixtures for the high frequency
parameter measurements of the substrate network, based on the suggestions proposed in [8]. Initial measurement results are presented in Chapter 4 and revised
simulations results to explain and validate the imperfections found in the initial
measurements are detailed in Chapter 5. A new probing scheme for high frequency
substrate characterization is the topic of Chapter 6 and finally, conclusions are
presented in Chapter 7.
6
2. AN OVERVIEW OF PRIOR WORK
In prior works [6], [8], measurements were made by probing on chip. The
problem with on-chip probing for these measurements is that the probe grounds,
which define the reference node for the two-port substrate network under test,
are connected either only to each other through metal traces, or to the surface of
the substrate with p+ substrate contacts. The most meaningful and convenient
reference node for the two-port substrate networks is the back side of the die, so
it is desirable to have the probe grounds make contact to the back side of the
die. Moving the probe points off-chip provides the ability to make this connection
between the probe grounds and the back side of the die. Similar work through
off-chip probing was also done in [9], where the test chip was mounted in a socket.
The parasitics of the socket were accounted for as part of the measurements.
2.1. Off-Chip Probing
A test fixture was previously designed to enable network analyzer measurements of the substrate networks between pairs of substrate contacts up to 20
GHz. This test fixture, which is shown in Figure 2.1, comprises a chip, a thin
ceramic substrate, and a solid copper block. The 0.010” thick alumina substrate
has thin-film circuitry patterned on the top side, and a solid metal ground plane
on the back side, which is soldered to the copper block. The ceramic substrate
and test fixture were fabricated and assembled by Kyocera [10].
The chip is bonded to the copper block inside a cavity formed by a cutout
in the ceramic substrate, as shown in Figure 2.1. The probe ground pads connect
through vias to the ground provided by the copper block, to which the ceramic
substrate is soldered, and to which the die is bonded. The chip was fabricated in a
7
FIGURE 2.1. Test fixture assembly.
0.35µm TSMC heavily-doped process. It contains four substrate test structures,
as well as two other structures used for measurement deembedding. The chip
was fabricated through MOSIS as a block of four sub-die, each containing four
distinct test structures comprising pairs of substrate contacts of various sizes and
spacings, yielding a total of 16 unique test structures. As shown in Figure 2.2(a),
the on-chip test structures connect, via bond wires, to transmission lines on the
ceramic substrate. The transmission lines are placed between the die and the
probe pads, where they are interdigitated with probe ground pads. The probe
ground pads connect through the ceramic by vias to the back side ground plane.
The transmission lines are probed with 50 Ω, 150 µm-pitch, G-S-G micro-probes
connected to a network analyzer.
Moving the probe points off-chip has the disadvantage that a significant
amount of test fixture, with its associated parasitics, has been introduced between
the network analyzer reference plane at the 50 Ω probe tips and the two-port
substrate networks being measured. A four-step de-embedding procedure has
been developed which allows the network parameters for the substrate network
8
(a)
(b)
(c)
FIGURE 2.2. Characterization structure of (a) chip mounted on test fixture,
(b) transmission lines, and (c) bondwires.
9
Ym
On−Chip
Trace
A B
C D
A B
C D
A B
C D
Substrate
Network
On−Chip
Trace
Bond−
Wire
Trans.
Line
A B
C D
A B
C D
A B
C D
Yg
Bond−
Wire
Yg
Trans.
Line
FIGURE 2.3. Test fixture model used for deembedding.
alone to be extracted from measurements that may be dominated by the effects of
the test fixture parasitics. The four step de-embedding procedure assumes [8] the
equivalent circuit model for the test fixture shown in Figure 2.3. Once the network
parameters characterizing each block of the model in Figure 2.3 are known, the
effects of those blocks can be stripped from the measurement, one at a time. The
network parameters for each block of the test fixture model are obtained through
a series of measurements of test structures, both on- and off-chip, which have been
dedicated for deembedding.
The chip (Figure 2.4) includes two deembedding structures, a through trace
and an empty structure, which allow characterization of the on-chip sections of
trace, and the admittances that shunt the substrate network, respectively. Characterization of the off-chip portions of the test fixture is enabled by measurements
taken on deembedding structures on the ceramic substrate.
Figure 2.2(b) shows the structures which allow characterization of the
transmission lines that provide the connections between the 50 Ω probes and
the bondwires that make contact with the chip. The bond wires of the characterization structure shown in Figure 2.2(c) span a trench that is sized to be equal in
width to the space that surrounds the die in the cavity (Figure 2.2(a)), allowing
them to be nearly identical to the bond wires that make contact with the chip.
10
FIGURE 2.4. Photograph of the test chip.
2.2. Isolation Issue
Extensive simulations have been performed in Ansoft’s High Frequency
Structure Simulator, a 3-D electromagnetic simulator, also referred as HFSS [11].
These simulations have been used for the design and validation of the test fixture
and the deembedding procedure.
Deembedded S-parameters for a pair of 10µm x 10µm contacts from initial
measurements revealed the shortcomings of the test fixtures due to significant
amount of coupling between adjacent transmission lines and bondwires, which
violates the deembedding procedure assumption of isolated two port networks.
This is indicated by deembedded S-parameters greater than 0 dB as shown in
Figure 2.5.
In order to achieve some degree of correlation between simulations and
measurements, the structures shown in Figure 2.2 were simulated in their entirety
(Figure 2.6) and they can be used as guidelines to best modify or redesign the test
fixtures [8]. Simulations showed that in order to resemble the isolated model, the
coupling between adjacent traces and bondwires must be reduced by removing all
11
|S11| (dB)
20
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
|S21| (dB)
20
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 2.5. S-parameters from the initial measurements, showing the failure of
the measurement and deembedding procedure. (a) S11 , (b) S21 .
12
0
|S11| (dB)
−10
−20
−30
Simulation of Isolated Structure
Revised Simulation
Measurement
−40
−50
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(a)
|S21| (dB)
0
−2
−4
Simulation of Isolated Structure
−6
Revised Simulation
Measurement
−8
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(b)
FIGURE 2.6. S-parameters from the initial simulations, revised simulations, and
measurements for the outer-most bondwire of the bondwire characterization structure from [8]. (a) S11 , (b) S21 .
but the outer two transmission lines and bondwires of each structure, or all but
any one set of transmission lines and bondwires [8].
13
3. TEST FIXTURE MODIFICATION
Once it was verified that the original test fixtures had significant traceto-trace and bondwire-to-bondwire coupling, the test fixtures were modified to
resemble the isolated model. The coupling was reduced by removing all of the
bondwires and transmission lines adjacent to the structure being measured.
The proposed modification of the test fixtures for 10µm x 10µm contacts
and 10µm x 60µm contacts, suggested in this work, are shown in Figure 3.1. In
this scheme, three test fixtures are used for one substrate measurement.
Obtaining measurements of both the on-chip deembedding structures,
along with a single substrate test structure, would require three test chips mounted
in three separate test fixtures. The three first test fixtures would have all transmission line traces and bondwires removed except those connecting to the on-chip
through trace, on-chip empty contacts, and the on-chip contacts. The corresponding bondwire and transmission line characterization structures are also modified
appropriately.
Since all the sub-die test structures have a similar through on-chip trace
deembedding structure, only one particular test fixture was modified according
to Figure 3.1(a). In order to take into account the different shunt admittances
parasitic for all four different contact spacings, four test fixtures were modified
according to Figure 3.1(b)
In addition to that, another four test fixtures were modified according to
Figure 3.1(c) to characterize the 10µm x 10µm contact pairs for four different spacings. Finally the last four test fixtures were modified according to Figure 3.1(d)
to characterize the 10µm x 60µm contact pairs for four different spacings.
Since there were only 13 unassembled test fixtures left, and at least 3
test fixtures were needed to characterize a particular substrate network, all 16
14
TABLE 3.1. Dimensions of the modified two contacts test structures.
Test Structure Contact Size Spacing
1
10 µm x 10 µm 20 µm
2
10 µm x 10 µm 50 µm
3
10 µm x 10 µm 100 µm
4
10 µm x 10 µm 200 µm
5
10 µm x 60 µm 20 µm
6
10 µm x 60 µm 50 µm
7
10 µm x 60 µm 100 µm
8
10 µm x 60 µm 200 µm
different substrate test structures could not be characterized, without taping out
an additional 8 test fixtures. A total of 8 different two contact test structures
were salvaged from the original 16 test structures. These are shown in Table 3.1.
The 13 original test fixtures were sent to ESI (Electro Scientific Industries) [12] for removal of the microstrip transmission lines using laser trimming.
The modified test fixtures were then sent to Kyocera along with the chips to be
mounted and assembled with bondwires. Figure 3.2 shows a photomicrograph of
a laser trimmed transmission line characterization structure following the modifications made by ESI.
15
(a)
(c)
(b)
(d)
FIGURE 3.1. Configurations of modified test fixtures for (a) on-chip through
trace, (b) on-chip empty contacts, (c) 10µm x 10µm contact, and (d) 10µm x
60µm contact.
16
FIGURE 3.2. Photomicrograph of the modified transmission line characterization
structure.
17
4. MEASUREMENT
4.1. Test Equipment
The modified and assembled test fixtures were placed on a Cascade Microtech RF-1 probe station chuck, and were probed with 150 µm-pitch Cascade
Microtech G-S-G RF wafer probes [13]. S-parameter measurements of the deembedding test structures were taken using an Agilent 8720ES vector network analyzer (VNA) [14] and through WinCal 3.0, a Cascade Microtech calibration software that enhanced measurement productivity and accuracy by providing VNA
calibration support. An impedance standard substrate (ISS) 101-190 from Cascade Microtech provided the short, open, 50 Ω load and through necessary for
calibration.
4.2. Test Setup for Stable Calibration and Optimum SNR
In order to achieve stable calibration for accurate measurements, the VNA
was warmed up for a couple of hours until it reached its steady state temperature,
prior to calibration. This minimizes system drift due to temperature variation
during calibration. The signal-to-noise ratio of a vector network analyzer can be
described as:
µ
SNR[dB] = 10 · log10
P·N
L·K·T·B·F
¶
(4.1)
where P is the transmit power of the VNA ports, N is the number of averages for
VNA averaging, L is the loss of the device under test (DUT), K is the Boltzmann’s
constant, T is the room temperature (◦ K), B is the VNA intermediate frequency
(IF) bandwidth and F is the VNA noise figure. The losses associated with the
18
DUT, Boltzmann’s constant, room temperature and VNA noise figure were given
parameters that could not be changed to achieve higher signal-to-noise ratio. The
parameters left for optimization were the transmit power of the VNA, number of
waveforms for averaging and the IF bandwidth.
WinCal 3.0 did not support averaging as it is not normally used with
Agilent 8720ES VNA. The Agilent 8720ES VNA instead used IF bandwidth as a
more efficient method for repeatability improvement than provided by averaging.
The Agilent 8720ES VNA averaging is for successive sweeps and is, therefore, very
slow and much less useful. By default, the Agilent 8720ES VNA’s IF bandwidth
is 3000 Hz and its minimum value can be set to as low as 10 Hz. The default
signal-to-noise ratio of the VNA can be increased by 25dB by manually setting
the IF bandwidth of the VNA to its minimum value. The transmit power of
the VNA was also increased from its default power range [-20dBm to 0dBm] to
a higher input power range [-15dBm to +5dBm]. Hence an overall 32dB SNR
improvement was achieved from the VNA which resulted in cleaner S-parameter
measurements.
4.3. Initial Measurements
4.3.1. Shielding Validation
S-parameters measurements in some previous high frequency test structures at Oregon State University were swamped by interactions with the probe
station chuck on which the die being tested was situated. The interactions with
the chuck were aggravated by the fact that the back side of the die was exposed
and no connection to the probe ground leads, which defines the measurement
system ground, was provided [8]. Previous high frequency test structures relied
19
on coplanar waveguide signal propagation and the signal propagation in the test
structures was not properly shielded from interaction with the chuck probe station. This effect dominated the measurements although sufficient spacings were
provided by separating the die from the chuck with a thick piece of glass.
To tackle this issue, an off-chip probing scheme was used by including a
copper block on the bottom of the test structures. This copper block is attached
to the probe ground leads through vias as shown in Figure 4.1. The copper block
acts like a ground plane that shields the forward and return signal path in the
test structures from interaction with the probe station chuck.
FIGURE 4.1. Side view of the high frequency measurement setup.
In order to validate the shielding method for interaction with the probe
station chuck, the on-chip through trace structure was measured for different
heights above the probe station chuck. S-parameters measurements of the on-chip
through trace structure showed repeatable measurements in most of the frequency
range as shown in Figure 4.2. These results suggest that interaction with the probe
station chuck is sufficiently suppressed and the signal returns through the back side
of the die and distributes mainly through the copper block. Minor discrepancies in
the S-parameter measurements beyond 16 GHz are due to temperature variation,
which is difficult to stabilize throughout the measurement sequence and causes
random errors in measurements.
20
In order to correlate measurements with simulation, the on-chip through
trace structure comprising the cavity-mounted test chip (Figure 3.1(a)), the transmission lines and bondwires that connect to it, and the side ground structures are
simulated in entirety in HFSS.
Although the trend of the S-parameters measurements show reasonable
correlation with simulation, the insertion loss (S21 and S12 ) beyond 12 GHz, however showed artifacts that are not present in simulation. Moreover, a coupling
mechanism instigates a sudden drop in the return loss (S11 and S22 ) at 5 GHz in
measurements, which correlates with the return loss (S11 and S22 ) at ∼ 4 GHz in
simulation. These imperfections in measurements that are observed in the high
frequency measurement are investigated in Chapter 5 with revised simulations.
4.3.2. On Chip Through Trace Deembedding
The deembedding procedure of the on-chip through trace is described in
this subsection. The measured return loss and insertion loss of the on-chip through
trace structure is shown by the plots in Figure 4.3 along with its corresponding
simulated data. The measurement of this structure was taken with no spacer
separating the device under test and the probe station chuck, since the test fixture
shielded the test structures from probe station chuck interaction as validated in
the previous subsection.
To deembed the microstrip parasitic from the on-chip through trace structure measurement, as part of the first step of the deembedding procedure, the corresponding microstrip characterization structure was measured and the measured
S-parameter data is shown by the plot in Figure 4.4 along with its corresponding
S-parameter simulated data. The measured and simulated data correlate rela-
21
0
|S11| (dB)
−10
−20
No Spacer
1 Spacer
2 Spacers
Simulation
−30
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
16
18
20
(a)
0
21
|S | (dB)
−2
−4
−6
No Spacer
1 Spacer
2 Spacers
Simulation
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
(b)
0
12
|S | (dB)
−2
−4
−6
No Spacer
1 Spacer
2 Spacers
Simulation
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
(c)
0
|S22| (dB)
−10
−20
No Spacer
1 Spacer
2 Spacers
Simulation
−30
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 4.2. S-parameters from measurements and simulations of the on-chip
through trace structure for different spacing heights. (a) S11 , (b) S21 , (c) S12 , and
(d) S22 .
22
0
|S | (dB)
−10
11
−20
−30
Measurement Data
Simulation Data
−40
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(a)
0
Measurement Data
Simulation Data
21
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(b)
FIGURE 4.3. Simulated and measured S-parameters for the on-chip through
trace structure. (a) S11 , (b) S21 .
23
11
|S | (dB)
−5
−10
−15
−20
−25
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
|S21| (dB)
0
−0.5
−1
Measurement Data
Simulation Data
−1.5
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.4. Simulated and measured S-parameters for the microstrip structure.
(a) S11 , (b) S21 .
tively well below 10 GHz. Although the performance of the measured return loss
and insertion loss were slightly worse than the performance of the simulated return loss and insertion loss, the measured data still captured the same trend as
expected from the simulated data.
The second deembedding step in the deembedding procedure is to deembed the bondwire parasitic from the on-chip through trace structure measurement.
In order to characterize this bondwire parasitic, another measurement was taken
on the bondwire characterization structure and the measured S-parameters along
with its simulated S-parameters are shown by the plots in Figure 4.5. The measured return loss and insertion loss of the bondwire characterization structure
correlate relatively well below 16 GHz. The measured data showed a better re-
24
−20
11
|S | (dB)
0
−40
Measurement Data
Simulation Data
−60
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
0
|S21| (dB)
Measurement Data
Simulation Data
−0.5
−1
−1.5
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.5. Simulated and measured S-parameters for the bondwire characterization structure. (a) S11 , (b) S21 .
turn loss of ∼ 20 dB at ∼ 17GHz than the simulated data, on the other hand, the
measured insertion loss showed artifacts at
∼
18 GHz which are not present in
the simulated insertion loss. The consequence of these artifacts are discussed in
the upcoming deembedding step, but for the most part the measured data still
captured the same trend as expected from the simulated data.
Part of the second deembedding step in the deembedding procedure is to
deembed the microstrip parasitic from the bondwire characterization structure
measurement. The inverted cascade parameters of the microstrip structure obtained from measurement were multiplied to both sides of the inverted cascade
parameters of the bondwire characterization structure to obtain the deembedded
bondwire parasitic. The S-parameter of the deembedded bondwire parasitic is
25
−10
11
|S | (dB)
0
−20
Measurement Data
Simulation Data
−30
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
|S21| (dB)
0
−0.5
−1
−1.5
−2
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.6. Simulated and measured S-parameters for the bondwire characterization structure following the first deembedding step. (a) S11 after step 1, (b) S21
after step 1.
shown by the plots in Figure 4.6, along with its simulated S-parameter data. The
measured return loss of the deembedded bondwire parasitic correlates well with
the simulated return loss of the deembedded bondwire parasitic. In contrast, the
measured insertion loss of the deembedded bondwire parasitic showed artifacts at
∼
18 GHz, which are due to the artifacts present in the measured insertion loss of
the bondwire characterization structure shown in Figure 4.5(b). The consequence
of these artifacts shall be discussed in upcoming deembedded results of the on-chip
through trace structure following the second deembedding step.
The deembedded return loss and insertion loss of the on-chip through trace
structure following the first deembedding step are shown by the plots in Figure 4.7.
26
The microstrip parasitics were deembedded from the on-chip through trace structure measurement following the first deembedding step. Since the measured return loss and insertion loss of the microstrip structure contained no artifacts, the
deembedded results following the first deembedding step should not yield any
added artifacts. This is shown by the deembedded result in Figure 4.7, where the
artifacts are contributed only by the artifacts that were already present in the
measured insertion loss of the on-chip through trace structure beyond 12 GHz.
Moreover, there are also artifacts present in the deembedded return loss, shown
as a small peak at 5 GHz, which are due to the sharp dip in the measured return
loss of the on-chip through trace structure at 5 GHz as well. The consequence
of these artifacts shall be discussed in the upcoming deembedded results of the
on-chip through trace structure following the second deembedding step.
The deembedded return loss and insertion loss of the on-chip through trace
structure following the second deembedding step are shown by the plots in Figure 4.8. The bondwire parasitics were deembedded following the second deembedding step. The artifacts contained in the insertion loss of the bondwire parasitics,
as mentioned earlier, were present in the deembedded insertion loss of the on-chip
through trace. In other words, the artifacts at ∼ 18 GHz in the insertion loss of the
bondwire parasitics were the cause of the artifacts at ∼ 18 GHz in the deembedded
insertion loss of the on-chip through trace. The artifacts in the bondwire parasitics are shown as a sharp dip in the insertion loss at ∼ 18 GHz. These artifacts
caused a peak in the deembedded insertion loss of the on-chip through trace at
∼
18 GHz.
In essence, there are three main artifacts present in the deembedded S-
parameter data of the on-chip through trace, which are identified as a peak in the
deembedded return loss at 5 GHz due to the sharp dip in the measured return
27
0
11
|S | (dB)
−20
−40
Measurement Data
Simulation Data
−60
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
−5
21
|S | (dB)
0
−10
Measurement Data
Simulation Data
−15
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.7. Simulated and measured S-parameters for the on-chip through
trace structure following the first deembedding step. (a) S11 after step 1, (b) S21
after step 1.
28
0
11
|S | (dB)
−10
−20
Measurement Data
Simulation Data
−30
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
0
21
|S | (dB)
−2
−4
−6
Measurement Data
Simulation Data
−8
−10
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.8. Simulated and measured S-parameters for the on-chip through trace
structure following the second deembedding step. (a) S11 after step 2, (b) S21 after
step 2.
29
loss of the on-chip through trace structure, a dip in the deembedded insertion loss
at 12 GHz due to the dip in the measured insertion loss of the on-chip through
trace structure, and finally the artifacts beyond ∼ 18 GHz are due to the sharp dip
in the measured insertion loss of the bondwire characterization structure. In this
work, the first two main artifacts were investigated and the causes of these two
artifacts were identified.
4.3.3. Four Step Deembedding Result
The procedure of deembedding a pair of 10µm x 10µm contact at 20µm
separation is described in this subsection. The measured return loss and insertion
loss of the pair of 10µm x 10µm contact are shown by the plots in Figure 4.9.
Also shown in the figure is the reference data of the 10µm x 10µm contact pair at
20µm separation extracted from the parasitic simulation tool [7] and it represents
the end goal of the four step deembedding procedure. The measured S-parameter
of this contact pair structure showed parasitics that swamped the embedded two
port substrate network of the contact pair.
The deembedded return loss and insertion loss of the 10µm x 10µm contact pair structure following the first deembedding procedure are shown by the
plots in Figure 4.10. The measured S-parameters of the microstrip characterization structure corresponding to this 10µm x 10µm contact pair structure were
used to deembed the microstrip parasitics from the 10µm x 10µm contact pair
structure. The measured S-parameters of the microstrip characterization structure correponding to this contact pair structure showed no artifacts and they are
similar to the measured S-parameters of the on-chip through trace structure presented in the previous subsection. As mentioned earlier in the previous subsection,
30
20
Measured Data
Reference Data
11
|S | (dB)
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
21
|S | (dB)
20
Measured Data
Reference Data
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.9. Simulated and measured S-parameter data for the 10µm x 10µm
substrate contacts at 20µm separation. (a) S11 , (b) S21 .
31
20
Step 1 Data
Reference Data
11
|S | (dB)
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
21
|S | (dB)
20
Step 1 Data
Reference Data
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.10. Simulated and measured S-parameter data for the 10µm x 10µm
substrate contacts at 20µm separation following the first deembedding step.
(a) S11 after step 1, (b) S21 after step 1.
since the measured S-parameters of the microstrip parasitics showed no artifacts,
the deembedded results following the first deembedding step should not yield any
added artifacts. The deembedded S-parameters following the first deembedding
step shown in Figure 4.10 confirmed this, since the trend of both the deembedded
return loss and insertion loss are similar to the measured return loss and insertion
loss before following the first deembedding step.
The deembedded return loss and insertion loss of the 10µm x 10µm contact
pair structure following the second deembedding procedure are shown by the plots
in Figure 4.11. The second deembedding step in the deembedding procedure is
to deembed the bondwire parasitic from the 10µm x 10µm contact pair structure
32
20
Step 2 Data
Reference Data
11
|S | (dB)
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
21
|S | (dB)
20
Step 2 Data
Reference Data
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.11. Simulated and measured S-parameter data for the 10µm x 10µm
substrate contacts at 20µm separation following the second deembedding step.
(a) S11 after step 2, (b) S21 after step 2.
measurement. Part of the second deembedding step is to deembed the bondwire
parasitics from the bondwire characterization structure corresponding to this contact pair structure. The deembedded bondwire parasitics also contained artifacts
beyond 18 GHz in the insertion loss, as in the case of the deembedded bondwire
parasitics of the on-chip through trace structure in the previous subsection. Artifacts in the deembedded bondwire parasitics were the main cause of the artifacts
seen in the deembedded return loss of the 10µm x 10µm contact pair structure
following the second deembedding step. These artifacts in the deembedded return
loss of the 10µm x 10µm contact pair structure are shown as a peak close to 0 dB
at ∼ 18.5 GHz.
33
The deembedded return loss and insertion loss of the 10µm x 10µm contact
pair structure following the third deembedding procedure is shown by the plots
in Figure 4.12. The third deembedding step in the deembedding procedure is to
deembed the chain factorized on-chip through trace [8] from the 10µm x 10µm
contact pair structure measurement. Part of the third deembedding step is to
deembed the on-chip through trace parasitics from the on-chip through trace
characterization structure. Since the deembedding of the on-chip through trace
parasitics were already discussed in the previous subsection, their deembedded
on-chip through trace parasitics following the necessary chain factorization [8]
are readily used in this third deembedding step. The deembedded return loss of
this contact pair structure following the third deembedding step showed artifacts
at 12 GHz represented as a peak above 0 dB. This indicates the errors in the
deembedded return loss of this contact pair structure, since the return loss of a
device under test should never exceed 0 dB. Similar errors were are also present in
the deembedded return loss of this contact pair structure beyond 18 GHz, showing
peaks exceeding 0 dB. These artifacts at 12 GHz were caused by the sharp dip at
12 GHz in the deembedded insertion loss of the on-chip through trace parasitics.
Similarly, the artifacts beyond 18 GHz were also caused by the artifacts in the
deembedded return loss and insertion loss of the on-chip through trace parasitics
beyond 18 GHz as well. As mentioned earlier, the artifacts in the on-chip through
trace were caused by the artifacts in the deembedded insertion loss of the bondwire
parasitics corresponding to the on-chip through trace structure.
The deembedded S-parameters for a pair of 10µm x 10µm contact following
the final deembedding step is shown by the plots of Figure 4.13. The deembedded
return loss greater than 0 dB at 15 GHz and 18.5 GHz indicate the shortcoming
of the measurement and the deembedding procedure. Moreover, the deembedded
34
20
Step 3 Data
Reference Data
11
|S | (dB)
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
21
|S | (dB)
20
Step 3 Data
Reference Data
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.12. Simulated and measured S-parameter data for the 10µm x 10µm
substrate contacts at 20µm separation following the third deembedding step.
(a) S11 after step 3, (b) S21 after step 3.
35
20
Deembedded Data
Reference Data
11
|S | (dB)
10
0
−10
−20
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
21
|S | (dB)
20
Deembedded Data
Reference Data
0
−20
−40
−60
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE 4.13. Simulated and measured S-parameter data for the 10µm x 10µm
substrate contacts at 20µm separation following the final deembedding step.
(a) S11 after step 4, (b) S21 after step 4.
insertion loss S-parameters showed many sharp dips at multiple frequencies, which
does not represent the substrate coupling between two contact pair. For this
reason, the substrate network between a two contact pair could not be extracted
for model development.
The source of the two main artifacts at 12 GHz and beyond 18 GHz following the third deembedding step needed to be identified and understood before
moving to identifying the artifacts following the final deembedding step. The focus of this work is to identify the artifacts at 12 GHz and other minor artifacts
that were present in the on-chip through trace structure and the test fixture design
itself.
36
5. VALIDATION AND REVISED SIMULATION
The goal of this chapter is to validate the imperfections observed in the
high frequency measurements through revised simulations in HFSS. The key idea
is to get reasonable correlations of simulations with measurements in order to
identify the problems. Once the problems are identified, they can be used as
guidelines to best modify or redesign the probing scheme for high frequency substrate measurements.
5.1. Resonance in Signal Return Path
It was determined that measurement artifacts in the insertion loss beyond
12 GHz were caused by poor via connections which resulted in resonance in the
path for the signal to return to the ground probe leads on the probe pads. Figure 5.1(a) shows a scenario where the only path for the signal to return to the
ground probe leads is through a via that is farthest from where the signal was
originally launched from the signal probe leads.
The signal return path shown in Figure 5.1 shows a resonance loop characteristic similar to a transmission line terminated in a short circuit. A representation of a short terminated transmission is shown in Figure 5.2(a). The input
impedance of a transmission line terminated in a short circuit is seen to be purely
imaginary for any length, L, and can take any values between +j∞ and -j∞ at
multiple quarter wavelength sections, as shown in Figure 5.3(a). The same case
applies to a transmission line terminated in an open circuit (Figure 5.2(b)) at
multiple half wavelength sections as shown in Figure 5.3(b). A simple calculation
of the quarter and half wavelength frequencies is
37
(a)
(b)
FIGURE 5.1. Signal return path of the on-chip through trace structure forming
(a) a long resonance loop, and (b) a parallel resonance loop.
fλ/4 =
fλ/2 =
4·l·
2·l·
co
√
co
√
²r,ef f
²r,ef f
(5.1)
(5.2)
where co is the speed of light, l is length, and ²r,ef f is the effective permittivity of
the alumina ceramic. The quarter wavelength as a function of frequency is shown
in Figure 5.4.
Figure 5.1(b) shows all possible combinations of resonance loops forming the signal return path, which depends on the connectivity of the vias and,
hence the termination of the loops. At multiple quarter wavelength frequencies,
short circuit terminated transmission lines act like a line with an infinite input
impedance whereas open circuit terminated transmission lines act like a line with
a zero input impedance. Each via can form either an open or a short circuit
terminated transmission line and the actual signal return path in measurements
would be dependent on the connectivity of the vias.
A worst case scenario is replicated in a HFSS simulation structure by disconnecting all other vias except the ones that are farthest from the positions
38
(a)
(b)
FIGURE 5.2. A transmission line terminated in (a) a short circuit, and (b) an
open circuit.
where the probes are placed. This case will form a resonance loop of length 2
mm that will intersect with the quarter wavelength plot at 12 GHz as shown in
Figure 5.4. Apparently at a certain frequency, only a small amount of energy can
propagate or insert through the on-chip through trace structure. A revised HFSS
simulation result illustrates this increase of insertion loss at ∼ 10.5 GHz as shown
in Figure 5.5. This simulation result showing a sharp dip in insertion loss at ∼ 10.5
GHz correlates with the small dip in insertion loss at 12 GHz in measurement as
shown in Figure 4.2.
Another worst case scenario is performed in HFSS simulation by adding
another via that is second farthest from the position where the probes are placed.
In this case, the resonance loop of length 1.5 mm will intersect with the quarter
wavelength plot at ∼ 16.5 GHz. In general, the sharp dip in insertion loss would
be pushed to higher frequencies, as one would expect for quarter wavelength resonance in the signal return path loop. This second scenario is validated by the plot
shown in Figure 5.5, where the sharp dip in insertion loss is pushed to a higher
frequency at ∼ 15 GHz.
In an effort to closely mimic the amount of insertion loss present in measurements, another scenario is replicated in a revised HFSS simulation with a
finite termination in the farthest via. The simulation result of this case reduces
39
0
0
Im (Z ) / Z
5
in
10
−5
−10
−5
−4
−3
λ/4
−2
−1
0
−2
−1
0
(a)
0
0
Im (Z ) / Z
5
in
10
−5
−10
−5
−4
−3
λ/4
(b)
FIGURE 5.3. Impedance variation along (a) a short circuited transmission line,
and (b) an open circuited transmission line.
40
4
Quarter wavelength
Length to farthest via
Length to 2nd farthest via
3.5
Length (mm)
3
2.5
2
1.5
1
6
8
10
12
14
Frequency (GHz)
16
18
20
FIGURE 5.4. Quarter wavelength as a function of frequency.
the sharp dip in the previous farthest via simulation by ∼ 10 dB and mimics the
insertion loss artifacts in measurements. The simulation result is shown in Figure 5.6.
The probe structure of the on-chip through trace was modified by cutting
the gold trace that connects to the adjacent vias. The top view of the modified
structure is shown in Figure 5.7 and a photomicrograph of the cut on the gold
trace is shown in Figure 5.8. By cutting the connection to the adjacent vias, the
signal is forced to return through the via under the probe pad. This modification eliminates the formation of signal return loop through the farthest via. The
elimination of signal return loop through the farthest via should eliminate the
sharp dip in insertion loss at 12 GHz in the measurements of the modified structure. The measurement results of this modified structure are compared against
the measurement results of the actual structure and they are shown in the plot
of Figure 5.9. The sharp dip eliminated in the insertion loss measurements of the
41
0
11
|S | (dB)
−10
−20
Farthest placed via
Two farthest placed vias
−30
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
21
|S | (dB)
0
−10
−20
Farthest placed via
Two farthest placed vias
−30
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 5.5. S-parameters from simulation of the structure shown in Figure 5.1(b). (a) S11 , (b) S21 .
42
0
11
|S | (dB)
−10
−20
Farthest placed via
Farthest placed via (finite termination)
−30
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
21
|S | (dB)
0
−10
−20
−30
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 5.6. S-parameters from simulation of the structure shown in Figure 5.1(b) with and without finite termination. (a) S11 , (b) S21 .
43
FIGURE 5.7. Top view of on-chip through trace for modified probe structure.
modified structure confirmed the elimination of the signal return loop through the
farthest via.
The comparison of the measured and simulated S-parameters of the on-chip
through trace for the modified probe structure is shown by the plots in Figure 5.10.
The modification of the probe structure, not only eliminates the dips that were
present in the insertion losses (S21 and S12 ) in the measurements of the actual
probe structure, but also eliminates the small dip in the return loss of port 2 (S22 )
in the measurements of the actual probe structure. This modification allows the
return loss and insertion loss from both ports of the test structure to be more
symmetric and closely satisfies the symmetric assumption in the deembedding
procedure.
These three worst case scenarios replicated in the revised HFSS simulations
and the measurement of the modified structure suggest that measurement artifacts
in the insertion loss beyond 12 GHz were caused by resonance in the signal return
path due to parallel combinations of various terminations in the signal return
loops, hence the first shortcoming of the test fixture design.
44
FIGURE 5.8. Photomicrograph of the modified probe structure.
5.2. Lack of Isolation
In this validation, the via structures were simplified by eliminating the adjacent vias next to the position where the probes landed. Resonance signal return
path problem should not exist in this simplified structure, as it was validated by
the measurements of the structure shown in Figure 5.7, where adjacent vias were
disconnected from the probe pad. This allows the signal to return only through
the via under the probe pad.
The structure of Figure 5.7 with perfect via connections to the copper block
was simulated in HFSS. The S-parameter simulation of this modified structure is
compared against the simulation of the actual structure, as shown in Figure 5.11,
and both simulation results show little to no difference, in terms of their return
loss and insertion loss responses. This validation also reveals that in the actual
structure, the shortest signal return path dominates the signal return, as long as
perfect via connections under the probe pads are provided.
45
0
|S11| (dB)
−10
−20
−30
Actual probe structure
Modified probe structure
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(a)
0
Actual probe structure
Modified probe structure
21
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(b)
0
Actual probe structure
Modified probe structure
12
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(c)
0
|S22| (dB)
−10
−20
−30
Actual probe structure
Modified probe structure
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 5.9. S-parameters from measurements of the on-chip through trace for
actual structure and modified probe structure. (a) S11 , (b) S21 , (c) S12 , and (d) S22 .
46
0
|S11| (dB)
−10
−20
−30
Measurement Data
Simulation Data
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(a)
0
Measurement Data
Simulation Data
21
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(b)
0
Measurement Data
Simulation Data
12
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(c)
0
|S22| (dB)
−10
−20
−30
Measurement Data
Simulation Data
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 5.10. S-parameters from simulations and measurements of the on-chip
through trace for modified probe structure. (a) S11 , (b) S21 , (c) S12 , and (d) S22 .
47
0
|S11| (dB)
−10
−20
−30
Actual probe structure
Modified probe structure
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(a)
0
Actual probe structure
Modified probe structure
21
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(b)
0
Actual probe structure
Modified probe structure
12
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(c)
0
|S22| (dB)
−10
−20
−30
Actual probe structure
Modified probe structure
−40
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 5.11. S-parameters from simulations of the on-chip through trace for
actual structure and modified probe structure. (a) S11 , (b) S21 , (c) S12 , and (d) S22 .
48
FIGURE 5.12. Half wavelength transmission line.
The input impedance of a half wavelength transmission line is a repeat
of the termination at the distant end as shown in Figure 5.12. When the input
impedance of a transmission line is equal to the reference termination, which in
this case is 50 Ω, a match termination is satisfied. In such a case, the energy
transmitted into the transmission line will be fully absorbed and the return loss
of the transmission line will be very small.
Sharp drops in the return loss of the on-chip through trace structure look
very much like a matched termination in both S11 and S22 at 5 GHz in measurement, which correlates with the drops at 4 GHz shown in the simulation.
Figure 5.13 shows a plot of half wavelength as a function of frequency along with
lines showing the actual length of the on-chip through trace structure and the
length of the revised structure shown in Figure 5.14(a). A matched termination
is shown at the intersection of the half wavelength plot and the actual length of
the on-chip through trace occurring at ∼ 5 GHz.
Since simulation results correlate well with measurements, a series of revised simulations is performed by modifying and incrementally removing adjacent
parts in HFSS simulations to identify the major component contributing to the
sharp drops in the return loss. In order to validate a matched termination in
the on-chip through trace, a revised HFSS simulation structure is simulated with
shorter transmission line lengths as shown in Figure 5.14(a).
49
25
Half wavelength
Length of actual structure
Length of revised structure
Length (mm)
20
15
10
5
0
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
FIGURE 5.13. Half wavelength as a function of frequency.
The return loss simulation plot in Figure 5.15(a) shows the sharp drops
in return loss occur at lower frequencies of
∼
3 GHz, as one would not expect
for a matched termination, where the revised structure length intersects with the
half wave length plot at a higher frequency in Figure 5.13. The plot shown in
Figure 5.15 for the revised structure rules out the case of matched termination
as the cause for the sharp drops in the return loss of the on-chip through trace
structure.
The sharp drops at
∼
3 GHz suggests that other structures perturb the
return loss behavior of the device under test. The side ground structures that are
meant to bias the heavily doped substrate to ground are apparently coupling with
the device under test. This was determined through a method of elimination in
a series of revised simulations in HFSS. Incrementally parts of the side ground
structures were removed. The top metal part of the side ground structures were
eliminated as shown in Figure 5.14(b) and finally all the side ground structures
50
(a)
(b)
(c)
FIGURE 5.14. HFSS structure top view of on-chip through trace for (a) revised
structure, (b) removed side ground metals, and (c) removed side ground vias.
were completely eliminated including the vias to the copper block as shown in
Figure 5.14(c). It is observed that the return loss behavior at ∼ 3GHz changes as
the side ground structures are incrementally eliminated and the sharp drop in the
return loss of the on-chip through trace disappears as the side ground structures
were completely eliminated as shown in Figure 5.15(a).
The position of the test structures on the die was also contributing to the
sharp drops in the return loss response. Simulations have shown that when a
test structure is placed in the center of the die, the sharp drops will reappear
in the return loss. The cause of this particular behavior was never resolved in
this work. The validation in this section reveals another shortcoming of the test
fixture design, since the isolated two-port network assumption is violated in the
deembedding procedure.
51
0
|S | (dB)
−10
11
−20
−30
(a) Revised Structure
(b) Removed Side Metals
(c) Removed Side Vias
−40
−50
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
21
|S | (dB)
0
−5
−10
(a) Revised Structure
(b) Removed Side Metals
(d) Removed Side Vias
−15
−20
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 5.15. S-parameters from simulation of structures shown in Figure 5.14.
(a) S11 , (b) S21 .
52
(a)
(b)
FIGURE 5.16. HFSS structure of on-chip through trace (a) including probe pads
and vias, and (b) excluding probe pads and vias.
5.3. Incorrect Deembedding
Many different kinds of electrical networks and devices can be characterized
and identified by measurements in the time domain. These include both Time
Domain Reflection (TDR) and Time Domain Transmission (TDT) measurements.
By observing the attributes of the waveforms, one can identify the nature of the
device under test. A pulse generator is typically used for time domain testing
and the most popular test signal is the step function. The TDR waveforms are
used to evaluate the impedance quality of a transmission line, whereas the TDT
waveforms are used to determine the effect a network has on the transmission
of a pulse signal through it. The time domain reflection waveform is of most
interest here to determine the location of any impedance discontinuity present in
the two-port device under test.
S-parameter data can be converted to the time domain in order to obtain
the TDR and TDT waveforms. The TDR and TDT waveforms were generated
53
by rational fitting of S-parameter data to rational transfer functions [15]. This
method is beneficial since phase extrapolation to DC is inherently zero and once
the S-parameters were fit to a rational transfer function, a step response is applied
to the return loss and insertion loss transfer functions to obtain the time domain
reflection and time domain transmission responses, respectively. Figure 5.17 shows
the TDR and TDT responses obtained from measurement of the on-chip through
trace.
Time domain waveforms obtained from HFSS simulation structure shown
in Figure 5.16(a) (includes the probe pads and vias connected to the copper block)
were included to validate the TDR and TDT waveforms obtained from measurement. Both time domain waveforms from measurement and this simulation structure showed reasonable correlations. Another HFSS simulation structure shown
in Figure 5.16(b) (excludes their probe pads and vias) was also simulated and the
time domain waveforms are also shown.
The TDR simulation waveform from the structure shown in Figure 5.16(a)
reveals that the probe pads and vias result in an excess length for the device
under test. This excess length, due to the addition of the probe pads and vias,
is detected by a ∼ 5 ps delay that is observed in the TDR waveform. Figure 5.19
shows the TDR falling edge delay from 45 ps to 50 ps when the probe pads and
vias are added to the simulation. A lower peak at 10 ps in the TDR waveform
generated from simulation excluding the probe pads and vias raises a further need
to validate the major component contributing to this impedance discontinuity,
which is suspected to be the probe pad.
Hence, another simulation is performed isolating the probe pad structure
and the transmission line themselves as shown in Figure 5.18. The time domain
response from this simulation is plotted in Figure 5.19. The TDR waveform from
54
Amplitude (V)
0.4
0.2
0
Measurement
Simulation (pads & vias included)
Simulation (pads & vias excluded)
−0.2
−0.4
0
50
100
Time (ps)
150
200
(a)
Amplitude (V)
1.5
1
0.5
Measurement
Simulation (pads & vias included)
Simulation (pads & vias excluded)
0
−0.5
0
50
100
Time (ps)
150
200
(b)
FIGURE 5.17. Time domain response of the on-chip through trace structure.
(a) Time domain reflection. (b) Time domain transmission.
55
FIGURE 5.18. HFSS structure for simulation of discontinuity in the probe pad.
the probe pad side shows a higher peak at 10 ps than the peak from the side
with no probe pad. The higher peak at 10 ps in the TDR waveform confirms
the impedance discontinuity contributed by the probe pad. Since all of the other
deembedding characterization structures have probe pads and vias, excess lengths
and impedance discontinuities would also be present in those structures as well.
These excess lengths and impedance discontinuities from the probe pads
and vias could potentially cause an incorrect parameter deembedding. Take a
simple scenario of deembedding the bondwire characterization structure, where
the inverted cascade matrices of the microstrip transmission line structures with
excess lengths and impedance discontinuity are multiplied on both sides of the
cascade matrix of the bondwire characterization structure. Excess lengths and
impedance discontinuities present in both sides of the bondwire characterization
cascade matrix would cause errors in deembedding for the bondwire. This incorrectly deembedded bondwire along with the microstrip transmission lines with
excess length and impedance discontinuities is used in the rest of the deembedding procedure. This affects the final deembedded results. HFSS structures,
shown in Figure 5.20 and 5.21, are simulated and their deembedded results were
56
Amplitude (V)
0.3
Probe pad side
No probe pad side
0.2
0.1
0
−0.1
0
50
100
Time (ps)
150
200
(a)
Amplitude (V)
1.5
1
0.5
0
−0.5
Probe pad side
No probe pad side
0
50
100
Time (ps)
150
200
(b)
FIGURE 5.19. Time domain response of HFSS simulation for validating the
discontinuity in the probe pad. (a) Time domain reflection. (b) Time domain
transmission.
57
FIGURE 5.20. HFSS simulation structure for simulation of a resistor embedded
in test fixture with no probe pads.
compared following the exact deembedding procedure for both structures, in order
to validate this potential deembedding problem. The HFSS structure shown in
Figure 5.20 excludes the probe pad structures along with their vias, whereas the
HFSS structure shown in Figure 5.21 includes the probe pad structures and their
vias.
Deembedded simulation results of both structures following the same deembedding procedure, in terms of admittances to ground and mutual admittances,
are shown in Figure 5.22. The deembedding procedure unsuccessfully deembeds
the 1 kΩ resistor embedded in the simulation having probe pads and vias, with
a discrepancy of 4 fF in self susceptance (Bgnd ), in Figure 5.22. In contrast, the
deembedding procedure successfully deembeds the 1 kΩ resistor embedded in the
simulation of Figure 5.20, with smaller discrepancies in the self susceptance (Bgnd )
and mutual susceptance (Bmut ) as shown in Figure 5.22.
58
FIGURE 5.21. HFSS simulation structure for simulation of a resistor embedded
in a test fixture with probe pads.
A comparison of the simulations illustrate the excess lengths and
impedance discontinuities present in the probe pads and vias, which was not
accounted for in the previous deembedding scheme. This points to the last shortcoming in the deembedding procedure and the test fixture design.
59
−4
2
x 10
Ggnd (S)
1
0
Deembedded Data [probe pad excluded]
Deembedded Data [probe pad included]
Reference Data
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(a)
−4
x 10
Bgnd (S)
2
Deembedded Data [probe pad excluded]
Deembedded Data [probe pad included]
Reference Data
1
0
−1
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(b)
−4
11
x 10
Gmut (S)
10
9
Deembedded Data [probe pad excluded]
Deembedded Data [probe pad included]
Reference Data
8
7
2
4
6
8
10
12
14
Frequency (GHz)
(c)
−4
2
x 10
Bmut (S)
1
0
Deembedded Data [probe pad excluded]
Deembedded Data [probe pad included]
Reference Data
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 5.22. Simulated deembedded self and mutual admittances for the 1
kΩ resistor embedded in the structure shown in Figures 5.20 and 5.21. (a) Self
conductance, (b) self susceptance, (c) mutual conductance, and (d) mutual susceptance.
60
6. NEW PROBING SCHEME
6.1. Probing Design
High frequency measurements using coplanar-waveguide (CPW) probes are
highly repeatable, and have accurate and reliable broadband calibration capability
[16]. Prior off-chip probing schemes allow the CPW probes, that provide a ground
reference plane, to connect through vias to the copper block, where the back side
of the substrate is connected.
Since the measurement system ground is the backside of the substrate,
the two contact substrate coupling structure is essentially a microstrip circuit.
A broadband vialess CPW-microstrip transition for the new probing scheme is
suggested for future work of high frequency substrate characterization as shown
in Figure 6.2. The structure provides a gradual transformation of electric and
magnetic fields and constant impedance along the transition. The transition uses
sections of CPW and CPWG (coplanar waveguide with ground) with gradually increasing gaps between the signal and coplanar ground conductors. It also includes
a tapered slot in the bottom ground conductor to provide low return loss. The
electrical connection between the top ground of the CPW and the bottom ground
of the microstrip is realized by electromagnetic coupling, thus no via holes are
required [17]. A thorough discussion of the CPW-microstrip transition in [17] is
used as a guideline in designing this broadband vialess CPW-microstrip transition
for the new probing scheme.
This design electromagnetically couples the backside of the die to ground,
instead of employing connections through vias in the prior off-chip probing scheme.
Not only does it eliminate the interactions with the probe station chuck since the
backside is still grounded, but it also decreases the steps in the deembedding
61
FIGURE 6.1. New model used for deembedding.
procedure and provides a consistent signal return path in the frequency range of
interest.
The deembedding model for the new probing scheme is shown in Figure 6.1.
This model eliminates the removal of the transmission lines and bondwires parasitics from the prior test fixture deembedding model shown in Figure 2.3. The
parasitics introduced by the probe pads and interconnects are included by taking
into account the effects of the contact resistances and the step discontinuity [18].
On-chip probe pad deembedding also serves to eliminate the similar excess deembedding problem in the off-chip probing scheme.
FIGURE 6.2. Vialess CPW-microstrip transition.
The open dummy structures shown in Figure 6.3(d), which yield the open
S-parameter matrix for the dummy structure, serves to deembed the probe pad
62
on the chip in the first step of the new deembedding procedure. After converting
the open-dummy S-parameter matrix to an open-dummy Y-parameter matrix, the
pad parasitic chain parameter matrix of the probe pads can be expressed as


1
0

Tpad = 
(6.1)

Y11,open + Y12,open 1
The on-chip deembedding model maintains the same deembedding procedure developed in prior test fixture design, but bypasses the first two deembedding
steps. The new model replaces the first two deembedding steps with an on-chip
probe pad deembedding step.
6.2. Probing Simulations
The purpose of these simulations is the design and validation of on-chip
test structures that enable the new probing measurements. The model used for
these simulations includes the on-chip probe pads, the on-chip interconnects, a
uniform block of non-conductive silicon substrate and a simplified substrate network that is represented by a 20µm x 20µm resistor. The actual substrate network
with two substrate contacts was replaced with a resistor on a non-conductive silicon substrate. In order to represent a reference network model that only has
finite mutual admittance and zero self admittance, defined by the resistor, a nonconductive silicon was used instead of a heavily doped silicon substrate. Memory
requirements for these simulations were also eased by replacing the model for
the silicon substrate with a uniform block of a non-conductive material, whose
dielectric constant is chosen to be silicon dioxide.
The structure is surrounded by an air box, which defines the boundary
over which the electromagnetic fields will be calculated. Stimuli are applied to
63
(a)
(b)
(c)
(d)
FIGURE 6.3. HFSS structure for simulation of a resistor embedded in the test
structure suggested for future work. Structure for simulation of (a) resistor,
(b) on-chip empty structure, (c) on-chip through trace, and (d) open dummy
pad structure.
64
−0.5
|S | (dB)
−1
11
−1.5
−2
−2.5
Simulated Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
Simulated Data
Reference Data
−18
21
|S | (dB)
−16
−20
−22
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 6.4. Simulated S-parameters for a 1 kΩ resistor embedded in the on-chip
test structure. (a) S11 , (b) S21 .
the network through wave ports, which are defined by rectangles at the ends of
the probe pads as shown in Figure 6.3. The full thickness of the tapered ground
conductor has been excluded from the model to minimize the amount of memory
required for simulations. CPWG sections with a gradually increasing gap between
the signal and coplanar ground conductors are the top metal layer. The top view
of the other deembedding structures necessary for complete verification of the
on-chip deembedding model are shown in Figures 6.3(b)-(d)
Figure 6.4 shows the S-parameters that would be obtained from “measurements” taken of the 1 kΩ resistor embedded in the test structures and also plotted
are the reference S-parameters for the resistor. The reference S-parameter repre-
65
−0.5
|S | (dB)
−1
11
−1.5
−2
−2.5
Step 1 Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
Step 1 Data
Reference Data
−18
21
|S | (dB)
−16
−20
−22
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 6.5. Simulated S-parameters for a 1 kΩ resistor following the first deembedding step. (a) S11 , (b) S21 .
sents the end goal of the deembedding procedure, and the standard by which its
effectiveness will be judged.
The simulated data agrees quite well with the reference S-paramters at 2
GHz. As the frequency increases the on-chip interconnect parasitic effects of the
test structures become important. Figures 6.5 through 6.7 show how the simulated
S-parameters evolve through the deembedding procedure, with each successive
deembedding step. The S-parameters converge to the reference S-parameters.
The corresponding admittances to ground and mutual admittances, which
are of interest when developing and evaluating a model, are shown in Figure 6.8.
The deembedded admittance to ground, Ygnd , and mutual admittance, Ymut , for
the 1 kΩ resistor of Figure 6.3(a) are plotted in Figure 6.8. The 20µm x 20µm 1
66
−0.5
|S | (dB)
−1
11
−1.5
−2
−2.5
Step 2 Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
Step 2 Data
Reference Data
−18
21
|S | (dB)
−16
−20
−22
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 6.6. Simulated S-parameters for a 1 kΩ resistor following the second
deembedding step. (a) S11 , (b) S21 .
67
−0.5
|S | (dB)
−1
11
−1.5
−2
−2.5
Deembedded Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
Deembedded Data
Reference Data
−18
21
|S | (dB)
−16
−20
−22
2
4
6
8
10
12
14
Frequency (GHz)
(b)
FIGURE 6.7. Simulated S-parameters for a 1 kΩ resistor following the final deembedding step. (a) S11 , (b) S21 .
kΩ resistor is electrically small over this frequency range and since the resistor is
placed on a non-conductive silicon substrate, the conductance to ground should
be zero and the mutual conductance should be 1 mS. There appears to be an
insignificant discrepancy between the reference and deembedded self and mutual
admittances.
Another simulation with a 10 kΩ resistor is performed and the final deembedded result of this 10 kΩ resistor along with its reference is shown in Figure 6.9
in terms of its ground and mutual admittances. The deembedded susceptance to
ground, Bgnd , corresponds to a shunt capacitance of 0.04 fF, which is within the
error tolerance of the parasitic extraction tool [7].
68
The new probing scheme works well for characterization of a lightly doped
substrate, but not very well for the heavily doped substrate. Substrate loss in
the heavily doped substrate causes a significant amount of insertion loss, and
degrades the deembedding procedure. A slight alignment deviation of the chip on
the tapered ground conductor, due to a poor test structure assembly, can cause
discrepancies in measurements as reported in [17]. Probe crosstalk can also be a
possible shortcoming of this new probing scheme, hence, probe pads need to be
separated sufficiently to suppress crosstalk [13]. These are possible shortcomings
for the new probing scheme that should be taken care of in the implementation.
69
−4
2
x 10
Deembedded Resistor Data
Reference Data
Ggnd (S)
1
0
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
16
18
20
(a)
−4
x 10
Deembedded Resistor Data
Reference Data
Bgnd (S)
2
1
0
−1
2
4
6
8
10
12
14
Frequency (GHz)
(b)
−4
11
x 10
Gmut (S)
10
9
8
7
Deembedded Resistor Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
(c)
−4
2
x 10
Deembedded Resistor Data
Reference Data
Bmut (S)
1
0
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 6.8. Simulated deembedded self and mutual admittances for the 1 kΩ
resistor. (a) Self conductance, (b) self susceptance, (c) mutual conductance, and
(d) mutual susceptance.
70
−5
2
x 10
Deembedded Resistor Data
Reference Data
Ggnd (S)
1
0
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
16
18
20
(a)
−5
3
x 10
Deembedded Resistor Data
Reference Data
Bgnd (S)
2
1
0
−1
2
4
6
8
10
12
14
Frequency (GHz)
(b)
−5
11
x 10
Gmut (S)
10
9
8
7
Deembedded Resistor Data
Reference Data
2
4
6
8
10
12
14
Frequency (GHz)
(c)
−5
2
x 10
Deembedded Resistor Data
Reference Data
Bmut (S)
1
0
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
(d)
FIGURE 6.9. Simulated deembedded self and mutual admittances for the 10 kΩ
resistor. (a) Self conductance, (b) self susceptance, (c) mutual conductance, and
(d) mutual susceptance.
71
7. CONCLUSION
7.1. Conclusion
Experimental validation of the test structures, following the modifications
proposed in this thesis, have shown that grounding the back side of the die by
off-chip probing eliminates the interactions with the probe station chuck. These
test structures allow the measured substrate networks to closely resemble the
equivalent circuit models for use in simulations.
Measurements and simulations of the test chips mounted in the test fixture revealed shortcomings in the prior test fixture design. The problems seen
in measurements were replicated in HFSS simulations, and these problems were
verified as resonance in signal return path due to imperfect via connections to the
backplane copper block, lack of isolation with structures on the alumina ceramic.
These violate the isolated two-port network assumption used in the deembedding
steps. Incorrect parameter deembedding, due to excess length and impedance
discontinuities present in the probe pad and via structures, also plague the deembedding procedure.
Although the prior off-chip probing schemes provide a solution to eliminate
the interactions with the probe station chuck by grounding the back side of the
die, there is no guarantee that the via connections and their placements would
allow good signal return path in the broad frequency range of interest. Not only
additional steps are needed in the fabrication of the test fixture and assembly
of the chip in the fixture, but also the steps in the deembedding procedure are
increased. Hence, it is highly desirable to have a vialess on-chip CPW-microstrip
transition. A prototype design of an on-chip probing along with its deembedding
model has been verified in simulation and results are shown in Chapter 6.
72
BIBLIOGRAPHY
[1] M. van Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. G. E. Engels, and
I. Bolsens, “Analysis and experimental verification of digital substrate noise
generation for epi-type substrates,” IEEE J. Solid-State Circuits, vol. 35, pp.
1002–1008, July 2000.
[2] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results
and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, pp. 420–430, April. 1993.
[3] P. Birrer, “Silencer! a tool for substrate noise coupling analysis,” Master’s
thesis, Oregon State University, Corvallis, OR, 2004.
[4] B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J.
Allstot, “Addressing substrate coupling in mixed-mode IC’s: Simulation and
power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29, no. 3, pp.
226–238, March. 1994.
[5] H. Lan, Z. Yu, and R. W. Dutton, “A CAD-oriented modeling approach of
frequency-dependent behavior of substrate noise coupling for mixed-signal IC
design,” in Proc. IEEE 2003 Int. Symposium on Quality Electronic Design,
San Jose, California, March. 2003, pp. 195–200.
[6] M. Pfost and H.-M. Rein, “Modeling and measurement of substrate coupling
in Si-bipolar IC’s up to 40 GHz,” IEEE J. Solid-State Circuits, vol. 33, no. 4,
pp. 582–591, April. 1998.
[7] C. Xu, T. S. Fiez, and K. Mayaram, “High frequency lumped element models
for substrate noise coupling,” in Proc. IEEE 2003 Int. Workshop on Behavioral Modeling and Simulation, San Jose, California, Oct. 2003, pp. 47–50.
[8] K. Webb, “A test fixture and deembedding procedure for high-frequency substrate characterization,” Master’s thesis, Oregon State University, June 2005.
[9] W. Steiner, H.-M. Rein, and J. Berntgen, “Substrate coupling in a high-gain
30-Gb/s SiGe amplifier–modeling, suppresion, and measurement,” IEEE J.
Solid-State Circuits, vol. 40, pp. 2053–2045, Oct. 2005.
[10] Kyocera America, Inc., San Diego, CA., http://americas.kyocera.com
[11] HFSS Three-dimensional electromagnetic simulation program, Ansoft Corporation, Pittsburgh, PA, 2003.
[12] Electro Scientific Industries, Inc. Portland, OR., http://esi.com
[13] Cascade Microtech, Beaverton, OR., http://www.cascademicrotech.com
73
[14] Agilent Technologies, Inc., Palo Alto, CA., http://www.agilent.com
[15] The Mathworks, Inc., Natick, MA 01760, USA.
[16] A. Safwata, K. Zaki, W. Johnson, and C. Lee, “Novel design for coplanar
waveguide to microstrip transition,” in IEEE Microwave Symposium Digest,
vol. 2, May 2001, pp. 607–610.
[17] L. Zhu and K. L. Melde, “On-wafer measurement of microstrip-based circuits with a broadband vialess transition,” IEEE Trans. Advanced Packaging,
vol. 29, pp. 654–659, Aug. 2003.
[18] M.-H. Cho, G.-W. Huang, K.-M. Chen, A.-S. Peng, C.-S. Chiu, Y.-M. Teng,
and H.-Y. Chen, “A novel de-embedding technique for on-wafer microwave
characterization,” 34th European Microwave Conference, Oct. 2004, pp. 917–
920.
74
APPENDICES
75
76
APPENDIX A. Test Fixture Mechanical Drawings
77
78
APPENDIX B. EPIC Simulation
The simulations described in this appendix were performed in EPIC (Extraction of Parasitics in Integrated Circuits), a Green’s Function-based substrate
simulator [7]. The objective of these simulations was to obtain data for the substrate network defined by the pairs of the modified substrate contacts of Table 3.1.
The simulations included only the on-chip substrate contacts shown and the
heavily-doped silicon substrate that surrounds them. The on-chip interconnects
and off-chip test fixture were not included in these simulations. This heavily-doped
substrate can be described by three discrete layers, as illustrated in Figure B-1.
The bulk layer is a 200 µm-thick heavily-doped layer. The 4 µm-thick epitaxial
layer has a high resistivity of 6 Ω·cm, and serves to provide some degree of isolation
between circuits on chip and also aids latchup prevention in the digital circuitry.
The top layer is a 1 µm-thick, 0.2 Ω·cm channel stop layer.
FIGURE B-1. Three-layer substrate used for simulation.
EPIC simulations were performed for each of the test structures shown in
Table 3.1. Deembedded mutual and self conductances and susceptances for each
contact dimension, parameterized by contact spacing, are plotted in figures B-2
and B-3.
79
The conductance to ground, Ggnd , and the susceptance to ground, Bgnd ,
both show little variation with substrate contact spacing for separations of 50 µm
or greater. However, the tendency of Ggnd to decrease slightly for contact separations of 20 µm or less is illustrated. Ggnd increases slightly with frequency,
while Bgnd shows the behavior of a nearly constant-valued capacitance, increasing
linearly with frequency.
The mutual conductances, Gmut , and mutual susceptances, Bmut , are several orders of magnitude lower than Ggnd and Bgnd . The mutual conductance,
Gmut , drops off rapidly for contact separations larger than 20 µm, and tends to
decrease with increasing frequency.
A closer inspection of figures B-2(d) and B-3(d), reveals that Bmut for
contact separations larger than 50 µm has a linear relationship with frequency,
and is inversely proportional to contact spacing. Figure B-2(d) and B-3(d),
however, show that, at contact separations smaller than 50 µm, Bmut can exhibit
the behavior of a parallel RLC network, and in fact, appears mostly inductive at
all frequencies.
80
−3
Ggnd (S)
3.4
x 10
3.2
20µm spacing
50µm spacing
100µm spacing
200µm spacing
3
2.8
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
−3
Bgnd (S)
1.5
x 10
20µm spacing
50µm spacing
100µm spacing
200µm spacing
1
0.5
0
2
4
6
8
10
12
14
Frequency (GHz)
(b)
−4
Gmut (S)
1.5
x 10
20µm spacing
50µm spacing
100µm spacing
200µm spacing
1
0.5
0
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(c)
−5
2
x 10
Bmut (S)
0
−2
20µm spacing
50µm spacing
100µm spacing
200µm spacing
−4
−6
2
4
6
8
10
12
14
Frequency (GHz)
(d)
FIGURE B-2. Simulated deembedded self and mutual admittances for a pair
of 10µm x 10µm substrate contacts. (a) Conductance, and (b) susceptance to
ground. Mutual (c) conductance, and (d) susceptance.
81
−3
10.5
x 10
Ggnd (S)
10
9.5
20µm spacing
50µm spacing
100µm spacing
200µm spacing
9
8.5
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(a)
−3
6
x 10
20µm spacing
50µm spacing
100µm spacing
200µm spacing
B
gnd
(S)
4
2
0
2
4
6
8
10
12
14
Frequency (GHz)
(b)
−4
8
x 10
20µm spacing
50µm spacing
100µm spacing
200µm spacing
4
G
mut
(S)
6
2
0
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
16
18
20
(c)
−4
Bmut (S)
1
x 10
0
20µm spacing
50µm spacing
100µm spacing
200µm spacing
−1
−2
2
4
6
8
10
12
14
Frequency (GHz)
(d)
FIGURE B-3. Simulated deembedded self and mutual admittances for a pair
of 10µm x 60µm substrate contacts. (a) Conductance, and (b) susceptance to
ground. Mutual (c) conductance, and (d) susceptance.
82
APPENDIX C. Deembedding on Rational Fitted Measurement Data
In an effort to smooth the measurement data from noise, the measured
S-parameters, along with its microstrip and bondwire characterization structure,
were fitted to a rational polynomial. The measured return loss and insertion loss
were each fitted to a rational polynomial and the S-parameters generated by these
rational polynomials were used in the deembedding procedure. The rationally
fitted S-parameters for the on-chip through trace structure are shown by the plots
in Figure C-4, along with the corresponding simulated and measured data. The
rationally fitted S-parameters for the microstrip and bondwire characterization
structures, along with their simulated and measured data, are shown by the plots
in Figure C-5 and C-6, respectively. The rationally fitted S-parameters captured
only the artifacts in measurement with no noise present in the return loss and
insertion loss.
The deembedded S-parameters of the bondwire parasitics are shown in
Figure C-7, along with the measured and simulated data. The deembedded Sparameter data of the bondwire parasitics from rational fitting showed smoother
response compared to the deembedded S-parameters taken from measurement,
with the artifacts beyond 18 GHz still present.
The deembedded S-parameters of the on-chip through trace structure following the first deembedding step are shown by the plots in Figure C-8. The
microstrip parasitics were deembedded from the on-chip through trace structure
measurement following the first deembedding step. The artifacts are contributed
by the artifacts that were already present in the rationally fitted insertion loss of
the on-chip through trace structure at 12 GHz. Moreover, the artifacts present
in the deembedded return loss, shown as a small peak at 5 GHz, are due to the
83
0
|S | (dB)
−10
11
−20
−30
Rational polynomial fit of Data
Measurement Data
Simulation Data
−40
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(a)
0
Rational polynomial fit of Data
Measurement Data
Simulation Data
21
|S | (dB)
−2
−4
−6
−8
−10
−12
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
(b)
FIGURE C-4. Simulated and rational polynomial fit of measurement data for the
on-chip through trace structure. (a) S11 , (b) S21 .
sharp dip in the rationally fitted return loss of the on-chip through trace structure
at 5 GHz.
The deembedded S-parameters of the on-chip through trace structure following the second deembedding step are shown by the plots in Figure C-9. The
bondwire parasitics were deembedded following the second deembedding step.
The artifacts in the rational polynomial fit of insertion loss of the bondwire parasitics, were present in the deembedded insertion loss of the on-chip through trace.
The artifacts in the bondwire parasitics are shown as a sharp dip in the insertion
loss at ∼ 18 GHz. These artifacts caused a peak in the deembedded insertion loss
of the on-chip through trace at ∼ 18 GHz.
84
11
|S | (dB)
−5
−10
−15
Rational polynomial fit of Data
Measurement Data
Simulation Data
−20
−25
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
|S21| (dB)
0
−0.5
−1
−1.5
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE C-5. Simulated and rational polynomial fit of measurement data for the
microstrip structure. (a) S11 , (b) S21 .
85
−20
11
|S | (dB)
0
−40
−60
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
|S21| (dB)
0
Rational polynomial fit of Data
Measurement Data
Simulation Data
−0.5
−1
−1.5
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE C-6. Simulated and rational polynomial fit of measurement data for the
bondwire characterization structure. (a) S11 , (b) S21 .
86
0
11
|S | (dB)
−10
−20
−30
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
0
21
|S | (dB)
1
−1
−2
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE C-7. Simulated and rational polynomial fit of measurement data for the
bondwire characterization structure following the first deembedding step. (a) S11
after step 1, (b) S21 after step 1.
87
0
11
|S | (dB)
−20
−40
−60
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
−5
21
|S | (dB)
0
−10
−15
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE C-8. Simulated and rational polynomial fit of measurement data for
the on-chip through trace structure following the first deembedding step. (a) S11
after step 1, (b) S21 after step 1.
88
0
11
|S | (dB)
−10
−20
−30
Rational polynomial fit of Data
Measurement Data
Simulation Data
2
4
6
8
10
12
Frequency (GHz)
14
16
18
20
14
16
18
20
(a)
0
21
|S | (dB)
−2
−4
−6
Rational polynomial fit of Data
Measurement Data
Simulation Data
−8
−10
2
4
6
8
10
12
Frequency (GHz)
(b)
FIGURE C-9. Simulated and rational polynomial fit of measurement data for the
on-chip through trace structure following the second deembedding step. (a) S11
after step 2, (b) S21 after step 2.
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APPENDIX D. Matlab Deembedding Code
D.1. Three Step On-Chip Deembedding Sequence
¨
[ f , s 1 k r e s ] = r e a d s 2 p ( ' s 1 k i d e a l . s2p ' )
[ f , s 1 0 k r e s ] = r e a d s 2 p ( ' s 1 0 k i d e a l . s2p ' )
[ f , s o p e n ] = r e a d s 2 p ( ' c p w m s t r i p o p t i m i z e d /pad . s2p ' ) ;
[ f , s t h r u ] = r e a d s 2 p ( ' c p w m s t r i p o p t i m i z e d / t h r u . s2p ' ) ;
[ f , s empty ] = r e a d s 2 p ( ' c p w m s t r i p o p t i m i z e d /empty . s2p ' ) ;
[ f , s d u t 1 k ] = r e a d s 2 p ( ' c p w m s t r i p o p t i m i z e d / f u l l 1 k . s2p ' ) ;
[ f , s d u t 1 0 k ] = r e a d s 2 p ( ' c p w m s t r i p o p t i m i z e d / f u l l 1 0 k . s2p ' ) ;
L = 200
g = 20
s d 1 k = deembedonchip ( s d u t 1 k , s empty , s t h r u , s o p e n , f , L , g ) ;
s d 1 0 k = deembedonchip ( s d u t 1 0 k , s empty , s t h r u , s o p e n , f , L , g ) ;
[ y 1 k r e f s e l f , y 1k ref mut ] = s2ymutself ( s 1k res ) ;
[ y 1 0 k r e f s e l f , y 10k ref mut ] = s2ymutself ( s 10k res ) ;
[ y 1 k d e m s e l f , y 1k dem mut ] = s 2 y m u t s e l f ( s d 1 k ) ;
[ y 1 0 k d e m s e l f , y 10k dem mut ] = s 2 y m u t s e l f ( s d 1 0 k ) ;
figure (1)
s u b p l o t f i g 2 b 2 y b l u e ( s 1 k r e s , f ) ; h o l d on
subplotfig2b2 yred ( s d 1k , f ) ;
s u b p l o t 221
a x i s ( [ 2 e9 2 e10 −2e−4 2 e −4])
s u b p l o t 222
¥
90
a x i s ( [ 2 e9 2 e10 −1e−4 3 e −4])
s u b p l o t 223
a x i s ( [ 2 e9 2 e10 7 e−4 11 e −4])
l e g e n d ( ' 1 K\Omega R e f e r e n c e ' , ' 1 K\Omega Deembedded ' , . . .
' l o c a t i o n ' , ' southwest ' )
s u b p l o t 224
a x i s ( [ 2 e9 2 e10 −2e−4 2 e −4])
figure (2)
s u b p l o t f i g 2 b 2 y b l u e ( s 1 0 k r e s , f ) ; h o l d on
subplotfig2b2 yred ( s d 10k , f ) ;
s u b p l o t 221
a x i s ( [ 2 e9 2 e10 −2e−6 2 e −6])
s u b p l o t 222
a x i s ( [ 2 e9 2 e10 −1e−6 3 e −6])
s u b p l o t 223
a x i s ( [ 2 e9 2 e10 7 e−6 11 e −6])
l e g e n d ( ' 10 K\Omega R e f e r e n c e ' , ' 10 K\Omega Deembedded ' , . . .
' l o c a t i o n ' , ' southwest ' )
s u b p l o t 224
a x i s ( [ 2 e9 2 e10 −2e−6 2 e −6])
figure (3)
f s d r e s r e c t p l o t y 1 k ( f /1 e9 , y 1 k d e m s e l f , . . .
y 1k ref self , . . .
y 1k dem mut , . . .
y 1k ref mut , . . .
{ ' Deembedded R e s i s t o r Data ' , ' R e f e r e n c e Data ' } ) ;
91
figure (7)
f s d r e s r e c t p l o t y 1 0 k ( f /1 e9 , y 1 0 k d e m s e l f , . . .
y 10k ref self , . . .
y 10k dem mut , . . .
y 10k ref mut , . . .
{ ' Deembedded R e s i s t o r Data ' , ' R e f e r e n c e Data ' } ) ;
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D.2. Three Step On-Chip Deembedding Function
¨
¥
f u n c t i o n s d = deembedonchip ( s d u t , s empty , s t h r u , s o p e n , f , L , g )
% 1 . Convert [ S OPEN] t o [Y OPEN]
y open = s2y ( s o p e n ) ;
%
%
C a l c u l a t e [A PAD]
|
1
0
% [A PAD] = |
%
| Y11 OPEN + Y12 OPEN
|
|
1
|
y11 open = y open ( : , 1 ) ;
y12 open = y open ( : , 3 ) ;
a pad ( : , 2 ) = y11 open + y12 open ;
a pad ( : , 1 ) = 1 ;
a pad ( : , 4 ) = 1 ;
a pad ( : , 3 ) = 0 ;
% 2 . Convert [ S THRU] t o [A THRU]
a t h r u = s2abcd ( s t h r u ) ;
%
C a l c u l a t e the i n t r i n s i c i n t e r c o n n e c t parameters using
%
[A INT ] = [A PAD]−1 [A THRU] [A PAD]−1
a i n t = a b c d s t r i p ( a pad , a t h r u , a pad , f ) ;
% 3 . Convert [A INT ] t o [ S INT ] and
s i n t = abcd2s ( a i n t ) ;
s11 int (:,1) = s int ( : , 1 ) ;
s21 int (:,1) = s int ( : , 2 ) ;
s12 int (:,1) = s int ( : , 3 ) ;
93
s22 int (:,1) = s int ( : , 4 ) ;
% Pad deembedding doesn ' t seem t o g i v e much p a r a s i t i c s t o t h r u
% S t e p 4 and 5 w i l l be by−p a s s e d u s i n g ABCD c h a i n p a r a m e t e r i z a t i o n
l = (L − g ) / 2 ;
n = round ( l o g 2 ( g + 2∗ l ) ) ;
k = round ( l /L∗ ( 2 ˆ n ) ) ;
a int1 = abcd factor ( a int , n , k );
a int2 = a int1 ;
s i n t 1 = abcd2s ( a i n t 1 ) ;
% 6 . C a l c u l a t e t h e ABCD m a t r i c e s o f t h e i n p u t p o r t [A IN ] and [A OUT]
% [A IN ]
= [A PAD] [A INT1 ]
% [A OUT] = [A IN2 ] [A PAD]
a in
= a b c d c a s c ( a pad
, a int1 , f );
a o u t = a b c d c a s c ( a i n t 2 , a pad
, f );
% 7 . Convert [ S DUT] t o [A DUT]
a d u t = s2abcd ( s d u t ) ;
% C a l c u l a t e t h e [A DE] = [A IN]−1 [A DUT] [A OUT]−1
a de = a b c d s t r i p ( a i n , a dut , a out , f ) ;
% 8 . Convert [A DE] b a c k t o [ S DE]
s d e = abcd2s ( a d e ) ;
% 9 . c o n v e r t [ S D] t o [Y D] t o remove empty a d m i t t a n c e s
y d e = s2y ( s d e ) ;
% Convert [ S EMPTY] t o [A EMPTY]
a empty = s2abcd ( s empty ) ;
% C a l c u l a t e [A E ] = [A IN]−1 [A EMPTY] [A OUT]−1
a e = a b c d s t r i p ( a i n , a empty , a o u t , f ) ;
94
% Convert [A E ] t o [ S E ] t o [Y E ]
s e = abcd2s ( a e ) ;
y e = s2y ( s e ) ;
% C a l c u l a t e [Y D] = [Y DE] − [Y E ]
y d = y de − y e ;
% Convert [Y D] t o [ S D]
s d = y2s ( y d ) ;
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D.3. Chain Parameter Factorization Function
¨
¥
funct ion abcd int = a b c d s t r i p ( abcd in , abcd cascade , abcd out , f )
% remove t h e o u t e r s t r u c t u r e d a t a from t h e c a s c a d e s t r u c t u r e d a t a
f o r i =1: l e n g t h ( f )
a b c d i n f i = [ abcd in ( i , 1 ) , abcd in ( i , 2 ) ; . . .
abcd in ( i , 3 ) , abcd in ( i , 4 ) ] ;
a b c d o u t f i = [ abcd out ( i , 1 ) , abcd out ( i , 2 ) ; . . .
abcd out ( i , 3 ) , abcd out ( i , 4 ) ] ;
abcd cascade fi = [ abcd cascade ( i , 1 ) , abcd cascade ( i , 2 ) ; . . .
abcd cascade ( i , 3 ) , abcd cascade ( i , 4 ) ] ;
a b c d i n t f i = inv ( a b c d i n f i )∗ a b c d c a s c a d e f i ∗ inv ( a b c d o u t f i ) ;
abcd int ( i , : ) = [ a b c d i n t f i ( 1 , : ) , a b c d i n t f i ( 2 , : ) ] ;
end
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D.4. Time Domain Response Function
¨
¥
function [ t , tdr 11 , tdr 22 , tdt 21 , tdt 12 ] = . . .
tdr tdt twice generate ( link )
FileName = l i n k ;
f i t = 80
SingleEndedData = r e a d ( r f d a t a . data , FileName ) ;
Freq = SingleEndedData . Freq ;
SingleEndedSparams = ( SingleEndedData . S P a r a m e t e r s ) ;
SingleEndedCkt = r f c k t . p a s s i v e ( ' NetworkData ' ,
...
r f d a t a . network ( ' Data ' , SingleEndedSparams , ' Freq ' , Freq ) ) ;
S11 = SingleEndedSparams ( 1 , 1 , : ) ;
S21 = SingleEndedSparams ( 2 , 1 , : ) ;
S12 = SingleEndedSparams ( 1 , 2 , : ) ;
S22 = SingleEndedSparams ( 2 , 2 , : ) ;
S11 DATA ( : , 1 ) = SingleEndedSparams ( 1 , 1 , : ) ;
S21 DATA ( : , 1 ) = SingleEndedSparams ( 2 , 1 , : ) ;
S12 DATA ( : , 1 ) = SingleEndedSparams ( 1 , 2 , : ) ;
S22 DATA ( : , 1 ) = SingleEndedSparams ( 2 , 2 , : ) ;
SampleTime = ( 1 / 1 0 ) ∗ 1 e −12;
OverSamplingFactor = 2 ∗ 2 5 ;
TotalPlotPoints = 2500;
TotalSampleNumber = 2 5 0 0 ;
Weight = 1 : l e n g t h ( Freq ) ;
% Fitting weight
FittingTolerance = −f i t ;
% R a t i o n a l f i t t i n g t o l e r a n c e i n dB
97
D e la y F ac t or = 0 ;
% Delay f a c t o r .
% S e t d e l a y f a c t o r t o z e r o i f your
% d a t a d o e s not have a w e l l−d e f i n e d
% principle delay
num = 0 ;
S11TDRRationalModel = r a t i o n a l f i t ( Freq , S11 , F i t t i n g T o l e r a n c e ) ;
S22TDRRationalModel = r a t i o n a l f i t ( Freq , S22 , F i t t i n g T o l e r a n c e ) ;
S11TDRPoles = l e n g t h ( S11TDRRationalModel .A ) ;
S22TDRPoles = l e n g t h ( S22TDRRationalModel .A ) ;
S21TDTRationalModel = r a t i o n a l f i t ( Freq , S21 ,
...
F i t t i n g T o l e r a n c e , Weight , D e l ay F ac t o r ) ;
S12TDTRationalModel = r a t i o n a l f i t ( Freq , S12 ,
...
F i t t i n g T o l e r a n c e , Weight , D e l ay F ac t o r ) ;
S21TDTPoles = l e n g t h ( S21TDTRationalModel .A ) ;
S12TDTPoles = l e n g t h ( S12TDTRationalModel .A ) ;
P l o t F r e q = l i n s p a c e ( 0 , 20 e9 , 2 0 0 0 0 ) ' ;
S11RespAtPlotFrequency = f r e q r e s p ( S11TDRRationalModel , P l o t F r e q ) ;
S21RespAtPlotFrequency = f r e q r e s p ( S21TDTRationalModel , P l o t F r e q ) ;
S22RespAtPlotFrequency = f r e q r e s p ( S11TDRRationalModel , P l o t F r e q ) ;
S12RespAtPlotFrequency = f r e q r e s p ( S21TDTRationalModel , P l o t F r e q ) ;
I n p u t S i g n a l = [ z e r o s ( 1 , num ) ' ; o n e s ( 1 , TotalSampleNumber − num ) ' ] ;
[ S11TDRSignal , OutputTime1 ] = t i m e r e s p ( S11TDRRationalModel ,
...
I n p u t S i g n a l , SampleTime ) ;
[ S22TDRSignal , OutputTime2 ] = t i m e r e s p ( S22TDRRationalModel ,
...
I n p u t S i g n a l , SampleTime ) ;
[ S21TDTSignal , OutputTime3 ] = t i m e r e s p ( S21TDTRationalModel ,
...
98
I n p u t S i g n a l , SampleTime ) ;
[ S12TDTSignal , OutputTime4 ] = t i m e r e s p ( S12TDTRationalModel ,
...
I n p u t S i g n a l , SampleTime ) ;
t = OutputTime1 ( 1 : T o t a l P l o t P o i n t s ) ∗ 1 e12 ;
t d r 1 1 = S11TDRSignal ( 1 : T o t a l P l o t P o i n t s ) ;
t d r 2 2 = S22TDRSignal ( 1 : T o t a l P l o t P o i n t s ) ;
t d t 2 1 = S21TDTSignal ( 1 : T o t a l P l o t P o i n t s ) ;
t d t 1 2 = S12TDTSignal ( 1 : T o t a l P l o t P o i n t s ) ;
§
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