6.012 - Microelectronic Devices and Circuits
Spring 2006 Design Problem Circuit
Full schematic
+ 1.5 V
Q1
A
Q2
Q3
Q4
B
Q5
Q9 Q10
Q11 Q12
A
C
Q24
C
Q6
Q19
Q18
Q13
+
v
Q7
IN1
D Q8
Q17
Q16
Q14
+
vIN2
B
Q15
Q21
Q20
Q28
Q25
Q26
Q29
D
Q22
Q23 B
+
vOUT
-
Q27
- 1.5 V
Bias chains
Source-coupled pair
gain stage with
Lee active load
Cascode* differential
gain stage with
cascode current
mirror active load
Complementary
emitter-follower
output stages
Push-pull
output
stage
* Common source stage followed by common base stage.
6.012 Design Problem
Spring 2006 - Slide 1
Circuit drawn with alternative MOSFET symbols:
Some find the MOSFET symbols used in this version of the schematic with the
arrow on the source, rather than the gate, more intuitive when looking at a
schematic. The rest of the foils in this set use the original symbols, so this figure
help you adapt those foils if you prefer these alternative symbols.
+ 1.5 V
Q1
A
Q2
Q3
Q4
B
Q5
C
Q9 Q10
Q11 Q12
Q17
Q16
Q24
C
Q6
Q13
+
v
Q7
IN1
D Q8
A
Q14
+
vIN2
B
Q15
Q18
Q19
Q20
Q21
Q28
Q25
Q26
Q29
D
Q22
Q23 B
+
vOUT
-
Q27
- 1.5 V
Bias chains
6.012 Design Problem
Source-coupled pair
gain stage with
Lee active load
Cascode* differential
gain stage with
cascode current
mirror active load
•Common source stage followed
by common base stage.
Complementary
emitter-follower
output stages
Push-pull
output
stage
Spring 2006 - Slide 2
Conceptual schematic: full circuit
+ 1.5 V
IBIAS3
Active load
(Lee load)
Q17
Q16
C
Q18
Q13
+
vIN1
-
Q14
+
vIN2
IBIAS1
Q19
Q21
Q28
Q25
Q26
Q29
Active Load
(Current mirror
cascode load)
+
vOUT
-
IBIAS2
- 1.5 V
Source-coupled pair
gain stage with
Lee active load
6.012 Design Problem
Source-coupled pair
stage followed by
common gate stage
with cascode current
mirror active load
Complementary
emitter-follower
output stages
Push-pull
output
stage
Spring 2006 - Slide 3
Conceptual schematic: difference-mode inputs
Common
Source
gLL,diff
Q13
+
vid/2
-
Q 17
Emitter
Follower
roQ 24
Q28
Q26
Common
Source
Q 19
Common
Gate
gCL,diff
Emitter
Follower
+
vod
100!
-
Avd = vod/vid
6.012 Design Problem
Spring 2006 - Slide 4
Conceptual schematic: common-mode inputs
Common
Source
gLL,com
Q13
+
Q 17
Source
Degeneration
(parallel
feedback)
vic
-
2roQ 15
roQ 24
Emitter
Follower
Q26
Q 19
Common
Gate
gCL,com
Emitter
Follower
Q28
+
voc
100!
-
Avc = voc/vic
6.012 Design Problem
Spring 2006 - Slide 5
Left to right through the design problem circuit:
1. Biasing: the bias chains
+ 1.5 V
Q1
+ 1.5 V
Q1
A
A
Q2
Q3
+ 1.5 V
Q5
C
RREF1
Q7
RREF2
C
Q6
≈
+ 1.5 V
RREF3
D
RREF3
D
Q4
B
- 1.5 V
Q4
B
- 1.5 V
Q8
- 1.5 V
RREF2
- 1.5 V
Points to ponder:
- What is the drain current of a minimum size n-channel MOSFET when (VGS-VT) =
(VGS-VT)min? What is it for a minimally biased p-channel MOSFET?
- How can Q1 and Q4 both be at this minimum bias point?
6.012 Design Problem
Spring 2006 - Slide 6
Left to right through the design problem circuit:
1. Biasing: looking at how each of the four stages is biased
+ 1.5 V
Q9 Q10
Q11 Q12
IBIAS3
Q17
Q16
C
Q13
+
vIN1
-
Q14
+
vIN2
IBIAS1
Q18
Q19
Q20
Q21
Q28
Q25
Q29
D
Q22
Q26
+
vOUT
-
Q23
IBIAS2
- 1.5 V
Stage 1: Biased
by the current
source, IBIAS1
6.012 Design Problem
Stage 2: Biased
by Q9, Q10, Q11,
and Q12.
Stage 3: Biased
by IBIAS2 and
IBIAS3.
Point to ponder:
- Stages 2 and 4 are biased by the preceding stages.
Stage 4:
Biased by
Q25and Q26.
Spring 2006 - Slide 7
Left to right through the design problem circuit:
1. Biasing: power dissipation
A constraint on the bias currents is the total power dissipation
specification of 7.5 mW. This means that the total bias current
must be less that 2.5 mA (i.e, 3 V x 2.5 mA = 7.5 mW).
+ 1.5 V
Q1
A
Q2
Q3
IA
Q4
B
Q5
C
Q9 Q10
Q11 Q12
Q24
Q17
Q16
C
Q6
Q13
+
Q7 vIN1
D Q8
A
IB
Q14
+
vIN2
B
IC
Q15
Q18
Q19
Q20
Q21
Q28
Q26
Q25
Q29
D
Q
ID 22
IE
Q23 B
IF
Q27
IG
+
vOUT
-
IH
- 1.5 V
IA + IB + IC + ID + IE + IF + IG + I H " 2.5 mA
PQ = ( IA + IB + IC + ID + IE + IF + IG + I H ) " 3 Volts
6.012 Design Problem
!
!
Spring 2006 - Slide 8
Left to right through the design problem circuit:
2. First gain stage: gain of source-coupled pair with Lee load
A Lee Load is an active load that looks different in common and
difference mode. A full analysis can be found in the handout
"Two Active Loads" posted on Stellar.
+ 1.5 V
Q9 Q10
Difference mode:
Q11 Q12
+
v id
gm13 v id
v od
-
-
+
Q13
vOUT1
+
vIN1
-
B
Q14
Q15
+
go13
2go9
+
vOUT2
+
vIN2
-
Common mode:
+
v ic
+
v gs13
-
+
gm13 v gs13
go13
v oc
2gm9
2r015
-
-
- 1.5 V
6.012 Design Problem
Spring 2006 - Slide 9
Left to right through the design problem circuit:
2. First gain stage: gain of source-coupled pair with Lee load
Difference mode:
+
v id
-
v od =
Common mode:
gm13 v id
go13
+
+
v od
-
2go9
"gm13
v id
g013 + 2g09
# V V
&
2 ID13
2 % A 9 A13 (
(VGS13 " VTn ) v = $ VA 9 + VA13 ' v = 2VA,eff 9,13 v
=
ID13
I
2 id
(VGS13 " VTn ) id (VGS13 " VTn ) id
+ 2 D13
VA13
VA 9
v ic
+
v gs13
-
+
go13
gm13 v gs13
v oc
2gm9
2r015
-
-
v oc "
(VGS 9 # VTp ) v
#g015
v ic =
ic
4gm 9
2VA15
Combined:
!
v out1 =
"V
"gm13
g
(v " v )
(v + v )
(V " V ) (v + v )
# in1 in 2 " 015 # in1 in 2 = ! A .eff 9,13 # (v in1 " v in 2 ) " GS13 Tn # in1 in 2
go13 + 2go9
2
4gm 9
2
2VA15
2
(VGS13 " VTn )
v out 2 =
VA .eff 9,13
gm13
g
(v " v )
(v + v )
(V " V ) (v + v )
# in1 in 2 " 015 # in1 in 2 =
# (v in1 " v in 2 ) " GS13 Tn # in1 in 2
go13 + 2go9
2
4gm 9
2
2VA15
2
(VGS13 " VTn )
Points to ponder:
- The outputs go to the gates of other MOSFET, so they do not load this stage. What
!
does this about getting the maximum difference mode out of this stage?
- How can Q9 through Q15 all be biased at their minimum bias point?
6.012 Design Problem
Spring 2006 - Slide 10
Left to right through the design problem circuit:
2. First gain stage, cont: common-mode input range
+ 1.5 V
vSG stays constant
Q9 +Q10
-
vC
up
vC
down
Q13, Q14 forced
out of
saturation
if v C too high
Q13
+
vGS
Q11+Q12
-
-
-
Q14
+
vGS
vC
up
vc
down
vGS stays constant
B
Q15
+
-
Q15 forced out
of saturation
if v c too low
- 1.5 V
Point to ponder:
- What is vDS and what is vGD at the boundary between the saturation and linear
regions?
6.012 Design Problem
Spring 2006 - Slide 11
Left to right through the design problem circuit:
3. Second gain stage: source-coupled cascode, current mirror load
+ 1.5 V
Q16
+
vIN1
-
Q17
0.75 V
Q19
Q18
Q21
Q20
-0.75 V
Q22
Q23
Comments/Observations:
- This stage is essentially a normal
+
vIN2
+
vOUT
-
rin3
source-coupled pair with a current
mirror load, but there are differences..
- The first difference is that two driver
transistors are cascode pairs. The stage
thus has two sub-stages, the first being a
source-coupled pair which is loaded by
the second, which is a common-gate
pair. The combination of a common
source stage followed by a common gate
stage is called a "cascode.
- The second difference is that the
current mirror load is also cascoded.
- The third difference is that the stage is
not biased with a current mirror, but is
instead biased by the first gain stage.
- 1.5 V
Point to ponder:
- Notice that output of the stage is loaded by the input resistance of the third stage.
In the first stage there was no loading. How does this effect the gain and how we
maximize it?
6.012 Design Problem
Spring 2006 - Slide 12
Left to right through the design problem circuit:
3. Second stage: gain of a simple current mirror with loading
V+
Q1
The output voltage is, in general:
gm 3
g06
v out =
v
"
v
+
( 1 2)
(v1 + v 2 )
g01 + g03 + gload
2gm 3
Q2
+
+
vIN1
-
Q4
Q3
vOUT
!
+
vIN2
-
Substituting for ID and dividing by K3:
(VGS 3 " VTN )
A
=
vd
!
# (V " V ) 2 g &
% GS 3 TN + load (
K 3 ('
%$ 2VA,eff
Q6
+
rload
Focusing on the differential
gain and writing it in terms of
the bias point:
K (V "* VTN )
gm 3
Avd =
= 3 GS 3
g01 + g03 + gload ( ID VA ,eff ) + gload
V REF
V-
Point to ponder:
- When the output is not loaded the voltage gain, 2VA,eff/(VGS3 - VTN), does not depend on
the K's of the transistors, but when it is loaded by rload, making K bigger can increase the
gain.
6.012 Design Problem
!
Spring 2006 - Slide 13
Left to right through the design problem circuit:
3. Second stage: the impact of having cascode pairs
+ 1.5 V
Q17
Q16
+
vIN1
-
0.75 V
Q19
Q18
+
vIN2
-
Replacing all the transistors in a current mirror
by cascode pairs significantly increases the
output resistances and the maximum gain:
V+
A Cascode Pair:
Commonsource
+
Q20
-0.75 V
Q22
Q21 vOUT
Q23
rin3
Q1
Q2
+
V IN+vin
-
gl
Commongate
+
V OUT+vout
-
V-
- 1.5 V
Av,Cascode =
v out
gm1
="
,
g
v in
gl + g02 01
gm 2
rout = r01
gm 2
g02
Points to ponder:
- What is the value of gload?
- Is it feasible to bias Q16 and Q17 to get the largest gain? How close can one come?
- Changing the bias on Q16/Q17 means that of Q9/Q10/Q11/Q12 must change. Is this OK?
- How much can K be increased? Is there any disadvantage to making K this big?
- Over what range!
can vOUT swing (positive and negative)?
6.012 Design Problem
Spring 2006 - Slide 14
V+
Left to right through the design problem circuit:
3. Second stage: the cascode
Commonsource
Schematic:
gl
Commongate
Q1
+
Q2
+
V IN+vin
V-
V OUT+vout
-
ro2
L.E.C.:
+
vgs1
gm1vgs1
vgs2
ro1
+
-
Av =
v out
=
v in g +
l
"gm1
g01
( gl + g02 )
(gm 2 + g02 )
#o
gm2vgs2
+
vout
rl
-
"gm1
gl + g01
g02
gm 2
gm 2 + g02 + g01
g02 g01
g
" r01 m 2
g02
rout =
Point to ponder:
- Av of a common-source stage, with a much larger output resistance.
6.012 Design Problem
Spring 2006 - Slide 15
!
!
Left to right through the design problem circuit:
3. Second stage: looking more at the cascode
The cascode stage looks like a common source stage made of a
special "cascode" transistor, QCC:
Commonsource
Q1
V+
gl
gl
Commongate
Q2
+
V IN+vin
-
V+
=
+
V OUT+vout
-
Cascode
equivalent
+
V IN+vin
-
g
d
+
vgsCC
s
QCC
V OUT+vout
-
V-
V-
QCC:
+
gmCC vgsCC
gm,CC = gm1
roCC
s
6.012 Design Problem
VA,CC " VA1
ro,CC " r01
gm 2
go2
or
gm 2
go2
#CC = #1
go2
gm 2
Spring 2006 - Slide 16
!
Left to right through the design problem circuit:
3. Second gain stage: substituting the cascode equivalents
+ 1.5 V
V+
Q17
Q16
+
vIN1
-
0.75 V
Q19
Q18
+
vIN2
-
=
+
vIN1
-
QCC1
QCC2
+
+
Q20
-0.75 V
Q21 vOUT
-
QCC3 QCC4
rin3
vOUT rin3
-
+
vIN2
-
VQ22
Q23
- 1.5 V
6.012 Design Problem
QCC1 =
QCC2 =
QCC3 =
QCC4 =
Common
source
Q16/Q18
Q17/Q19
Q22/Q20
Q23/Q21
Common
gate
Spring 2006 - Slide 17
Left to right through the design problem circuit:
3. Second gain stage: substituting the cascode equivalents
V+
g m,CC
QCC1
+
vIN1
-
QCC2
+
QCC3 QCC4
v out
vOUT rin3
-
+
vIN2
-
Q CC1
gm16
Q CC2
gm17
Q CC3
gm 22
Q CC4
gm 23
g o,CC
go16 go18
gm18
go17 go19
gm19
go22 go20
gm 20
go23 go21
gm 21
V(v + v in 2 )
= Avd v id + Avc v ic = Avd (v in1 " v in 2 ) + Avc in1
2
!
Avd = vout/(vin1-vin2) with vin1 = vid/2, vin2 = -vid/2:
!
Avd =
6.012 Design Problem
!
2gm,CC 2
2gm17
=
% " go23 go21
%
go,CC 2 + go,CC 4 + gin 3 "$ go17 go19
'+$
'
gm19 & #
gm 21 & + gin 3
#
Avd continued on next foil
Spring 2006 - Slide 18
Left to right through the design problem circuit:
3. Second gain stage: completing the gain derivation
Avd cont.:
2
Avd =
2ID
(VGS17 " VTp )
ID
ID (VGS19 " VTp )
I
I
(V " VTn ) + g
#
#
+ D # D # GS 21
in 3
VA17 VA19
2ID
VA 23 VA 21
2ID
2
2
=
#
(VGS17 " VTp ) $&(VGS19 " VTp ) + (VGS 21 " VTn ) + gin 3 ')
2VA 23VA 21
ID )(
&% 2VA17VA19
2
2
=
#
' Lesson: Bias the FETs
(VGS " VT ) min $(VGS " VT )
at (VGS-VT)min. Then
2gin 3
min
&
)
+
2
make gin3 as small as
&
)
VA2
K
V
"
V
(
)
17
GS
T
min (
%
possible and K17 as
large as you can.*
!
Avc = vout with vin1 =vin2 = vic,:
1
Avc "
2
6.012 Design Problem
Lesson: Not much can
be done about Avc.
* This may not be the peak gain, but it will be OK.
!
Spring 2006 - Slide 19
Left to right through the design problem circuit:
4. Third and fourth stages: emitter-followers
+ 1.5 V
A
Comments/Observations:
- These stages involve four emitter
Q24
Q28
+
vIN
-
Q25
B
Q26
+
vOUT 100!
Q29
-
Q27
- 1.5 V
follower building blocks arranged as
two parallel cascades of two emitter
follower stages each. These stages
offer the most design challenges and
trade-offs of any of the stages in the
design problem.
- They must be biased properly
taking into account KVL and KCL
constraints.
- Although they have voltage gains of
almost one, they have a big effect on
the overall voltage gain of the
amplifier because they load the second
gain stage.
- They determine the output
resistance of the amplifier.
Point to ponder:
- Am I having fun yet? (This is where the fun begins.)
6.012 Design Problem
Spring 2006 - Slide 20
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: biasing - getting the currents right
+ 1.5 V
A
IIN = 0
+
vIN Q25
B
Constraint at output node:
Q24
IBIAS3
IE28/("n+1)
Q28
IB25 =
|IE26|
|IB26|
IE28
Q26
|IE29|
IE25
Q29
|IE29|/("p+1)
IE 28 = IE 29
IB 25 = IB 26
Constraint at input node:
Equivalently: IE 25 (" n + 1) = IE 26 " p + 1
!
(
)
Sum at emitter of Q25:
IOUT = 0
100!
!
IBIAS 2 = IE 25 + IE 29 (" p + 1)
!
= (" n + 1) IB 25 + IE 29 (" p + 1)
#
&
IE 29
(
= (" n + 1)%IB 25 +
(" n + 1)(" p + 1)('
%$
Q27
IBIAS2
- 1.5 V
Sum at emitter of Q26:
#
&
IE 28
(
IBIAS 3 = (" p + 1) IB 26 + IE 28 (" n + 1) = (" p + 1)% IB 26 +
!
(" n + 1)(" p + 1) ('
%$
Combining everything: IBIAS 3 IBIAS 2 = (" p + 1) (" n + 1) # " p " n
6.012 Design Problem
!
Lesson: The bias currents are not totally unconstrained.
Spring 2006 - Slide 21
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: biasing - getting the voltages right
+ 1.5 V
KVL constraint:
A
VBE 28 + VEB 29 " VBE 25 " VEB 26 = 0
Q24
Relating voltages to currents:
+
Q28
+
V EB26
- Q26V BE28 ++ Q25
V EB29
V BE25
Q29
B
Q27
- 1.5 V
!
100!
VEB 26 = ( kT q) ln[ IE 26 " 26 IESp ]
VBE 28 = ( kT q) ln[ IE 28 " 28 IESn ]
VBE 29 = ( kT q) ln[ IE 29 " 29 IESp ]
Combining everything, including the fact
that IESp=IESn=IES, and the results |IE28|=IE29
and |I!
E26|/(βp+1)=IE25/(βn+1), yields:
Point to ponder:
- What do the results on this foil and the
last mean, and are there any other things
to consider when biasing these stages?
6.012 Design Problem
VBE 25 = ( kT q) ln[ IE 25 " 25 IESn ]
IE 28
=
IE 25
Lesson: The BJT areas matter.
!
("
p
+ 1) # 28# 29
(" n + 1) # 25# 26
Spring 2006 - Slide 22
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: input resistance, rin
We will use the approximation that the two emitter-follower paths can be modeled as
being in parallel for purposes of calculating the input resistance.
+ 1.5 V
A
+ 1.5 V
Q24
Q28
200!
In
parallel
Q25
rin2
Q29
Q26
rin1
200!
B
- 1.5 V
rin ≈ rin1|| rin2
Q27
- 1.5 V
Point to ponder:
- Remember that the ratio of IBIAS3 to IBIAS4 is constrained.
- Is there a penalty for picking a bias that maximizes rin? What else would be impacted?
6.012 Design Problem
Spring 2006 - Slide 23
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: output resistance, rout
* We will use the approximation that the two emitter-follower paths can be
modeled as being in parallel for purposes of calculating the output resistance.
+ 1.5 V
A
+ 1.5 V
Q24
In
parallel
Q28
Q26
rout1
Q25
2roS2
2roS2
B
- 1.5 V
rout ≈ rout1|| rout2
rout2
Q29
Q27
- 1.5 V
Point to ponder:
- Remember that the ratio of IBIAS3 to IBIAS4 is constrained.
- Is there a trade-off between power dissipation and rout? Is there an optimum bias?
6.012 Design Problem
Spring 2006 - Slide 24
+ 1.5 V
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: rin and
rt
rout of an emitter follower
+
vt
-
* Reviewing the input and output resistances
of a single emitter follower stage.
+
Right: Emitter-follower stage
Below: LECs for finding rin and rout
rin
"ib
ro
rt
rl
- 1.5 V
ib
r!
vout
-
IBIAS
iin = i b
+
Q25
"ib
r!
ro
vin
roBias
roBias
rl
-
rin = r" + (# + 1)( rl || ro || rBias )
$ r" + (# + 1) rl
+ it
vt
-
rout
rout = 1 [ go + gBias + (" + 1) ( r# + rt )]
$ ( r# + rt ) (" + 1)
Point to ponder:
- Looking in the resistance is multiplied by (β+1); looking back it is divided by(β+1) .
6.012
! Design Problem
!
Spring 2006 - Slide 25
+ 1.5 V
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: the voltage
rt
gain, Av, of an emitter follower
* Reviewing the voltage gain of an
emitter follower stage.
Q25
+
vt
-
+
Right: Emitter-follower stage
Below: LEC for finding Av
IBIAS
iin = i b
+
r!
vin
roBias
-
vout
-
rl
- 1.5 V
"ib
ro
+
rl vout = A v vin
-
v out = (" + 1)ib ( rl || ro || rBias )
v in = ib r# + (" + 1)ib ( rl || ro || rBias )
Av =
v out
(" + 1)( rl || ro || rBias )
=
v in r# + (" + 1)( rl || ro || rBias )
$
(" + 1)rl
r# + (" + 1) rl
Point to ponder:
- The voltage gains of the third-stage emitter followers (Q25 and Q26) will likely be very
close to one, but that of the stage-four followers might be noticeably less than one.
6.012 Design Problem
!
Spring 2006 - Slide 26
Left to right through the design problem circuit:
4. Third and fourth stages, cont.: output voltage swing
Q19 forced out
of saturation
if v OUT too high
+ 1.5 V
V SG
Q17
Q16
+
vIN1
-
C
Q19
Q18
Gate node
voltage fixed
Q20
Q21 forced out
of saturation
if v OUT too low
A-
+
vIN2
-
V SG stays constant
+ Q24
Q24 forced out
of saturation
if v OUT too high
Q28
Q21
Q25
Q26
Q29
D
Q22
V GS
V GS stays constant
vOUT
down
Q27
B
Q23 +
Gate node
voltage fixed
vOUT
up
-
Q27 forced out
of saturation
if v OUT too low
- 1.5 V
Points to ponder:
- How far + and - can the node connecting the drains of Q19 and Q21 swing?
- How low can the voltage on the drain of Q27 go? How high for the drain of Q24?
- How much do vBE28 and vEB29 increase as |vOUT| inceases?
6.012 Design Problem
Spring 2006 - Slide 27
Left to right through the design problem circuit:
4. Third and fourth stages: putting it all together
Comments/Observations:
- These stages involve four emitter
+ 1.5 V
A
Q24
Q28
+
vIN
-
Q25
B
Q26
+
vOUT 100!
Q29
-
Q27
- 1.5 V
Point to ponder:
- Now that I know everything,
how can I meet the specs?
6.012 Design Problem
follower building blocks arranged as
two parallel cascades of two emitter
follower stages each. These stages offer
the most design challenges and tradeoffs of any of the stages in the design
problem.
- They must be biased properly taking
into account KVL and KCL
constraints.
- Although they have voltage gains of
almost one, these stages have a big
effect on the overall voltage gain of the
amplifier because they load the second
gain stage.
- These stages determine the output
resistance of the amplifier.
- IBIAS3 and IBIAS4 set the bias levels of
Q25 and Q26. The bias levels of Q28 and
Q29 are set by the γ's.
- A reasonable choice is to make γ28 = γ
29, and γ25 = [(βn+1)/(βp+1)]γ26,in which
case:
IE28/IE25 = γ28/γ25
Spring 2006 - Slide 28
Left to right through the design problem circuit:
6. Overall gain expression
The defining relationships:
v out = Avd v id + Avc v ic = Avd (v in1 " v in 2 ) + Avc (v in1 + v in 2 ) 2
The difference-mode gain:
!
Avd = Avd1 " Avd 2 " Av 3 " Av 4
* n + 1) 2rl
# gm13
#2gm17
(
=
"
" 1"
2( g013 + 2go9 ) $ g017 g019 ' $ g023 g021 '
r+ 28 + (* n + 1) 2rl
&
)+&
) + gin 3
g
g
% m19 ( % m 23 (
rl = 100"
The common-mode gain:
$ n + 1) 2rl
# g015 #1
(
Avc = Avc1 " Avc 2 " Av 3 " Av 4 =
"
" 1"
4gm 9
2
r% 28 + (!$ n + 1) 2rl
!
Point to ponder:
- The follower stages treat the difference and common mode outputs the same.
!
- Let's put it all together and see what your design can do!
6.012 Design Problem
Spring 2006 - Slide 29
Left to right through the design problem circuit:
5. DC offset of a differential amplifier (OP-amp)
Procedure for finding the DC offset:
I. Identify the high impedance node* in the amplifier, and calculate what
the voltage on that node is when the output voltage is zero.
High impedance node
+ 1.5 V
Q1
Q5
A
Q2
C
Q9 Q10
Q11 Q12
Q8
Q24
C
Q13
+
Q7 vIN1
D -
Q4
B
Q17
Q16
Q6
Q3
A
Q14
+
vIN2
B
Q15
Q18
Q19
Q20
Q21
Q28
Q25
Q29
D
Q22
Q23 B
Q26
+
vOUT
-
Q27
- 1.5 V
Node voltage when vOUT = 0: VNODE-I = VBE25 - VEB29 ≈ 0 V
* Example: The output node of a CMOS inverter is an high impedance node.
When both MOSFETs were saturated the voltage on this node could take on
a range of values, and we couldn't say what vOUT was when vIN was VDD/2.
6.012 Design Problem
Spring 2006 - Slide 30
Left to right through the design problem circuit:
5. DC offset of a differential amplifier (OP-amp)
Procedure for finding the DC offset:
II. Disconnect the circuit following the high impedance node and
calculate the voltage on the node when vIN1 = vIN2 = 0, assuming
perfect symmetry and matching. Call this voltage VNODE-II.
+ 1.5 V
Q1
A
Q2
Q5
Q9 Q10
Q4
B
C
Q6
Q18
Q19
Q20
+
Q21 V NODE = ?
-
Q14
Q7 vIN1 = 0
D
Q8
Q17
Q16
Q13
Q3
High impedance node
Q11 Q12
C
vIN2 = 0
B
Both inputs zero
Q15
D
Q22
Q23
Complementary node
- 1.5 V
With perfect matching and symmetry,the voltage on the high
impedance node will equal that on the complementary node. In
this case VNODE-II = -1.5V + VGS22
6.012 Design Problem
Spring 2006 - Slide 31
Left to right through the design problem circuit:
5. DC offset of a differential amplifier (OP-Amp)
Procedure for finding the DC offset:
III. Knowing the differential voltage gain of the stage, Avd, we can
calculate the DC off-set at the output by subtracting the voltage
calculated in Step I, which we can call VNODE-I, from the voltage
calculated in Step II, VNODE-II.
When vIN1- vIN2 = (VNODE-I - VNODE-II)/Avd, VOUT is on the same order
and thus essentially zero. We will define this value of vIN1- vIN2 to
be the DC offset, certainly compared to (VNODE-I - VNODE-II).
R
R
vIN1 !
Avd
vIN2
6.012 Design Problem
DC offset = (VNODE-I - VNODE-II)/Avd
+
+
vOUT
-
RL
Example: In the design problem,
if Avd.turns out to be -1 x 104,
and (VNODE-I-VNODE-II) is -0.9V,
then the DC offset is 90 µV.
Spring 2006 - Slide 32
MIT OpenCourseWare
http://ocw.mit.edu
6.012 Microelectronic Devices and Circuits
Fall 2009
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