MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Department of Electrical Engineering and Computer Sciences
Analysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #2
Prof. Anantha Chandrakasan
Student Name:
Problem 1 (30 Points): _____________________
Problem 2 (24 Points): _____________________
Problem 3 (22 Points): _____________________
Problem 4 (24 Points): _____________________
Total (100 Points):
_____________________
For the entire quiz, ignore body effect (γ=0) and leakage effects. Also assume that all NMOS
device bulks are connected to 0V and PMOS well terminals are connected to VDD.
STATE ANY ASSUMPTIONS YOU MAKE IN SOLVING PROBLEMS and
SHOW YOUR WORK
There are 13 pages in total
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Problem 1: Carry Skip Adder: In this problem, we will explore the addition of two numbers based on the Carry
Skip (or Carry Bypass) technique.
a) Consider the following 16-bit Carry Skip Adder. Assume that the Sum Logic (SL) block for stage i has as inputs Pi,
Gi, and Cin,i. Assume the following delays:
• Delay to produce the Pi, Gi signals from the Ai, Bi inputs is 1 (i.e., the delay of the PG_L block)
• Delay to compute Cout_i from Pi, Gi and Cin,i inputs is 1 (i.e., the delay of the Carry Logic (CL) block)
• Delay to compute Si from Cin,i, Pi, Gi being valid is 2 (i.e., the delay of the Sum Logic (SL) block)
• Delay for the 2:1 multiplexor is 2
• Delay to compute the group propagate, GPi, is 1 (assume for the entire problem that this delay is independent of
the fan-in)
Cin,0
PG
_L
PG
_L
PG
_L
CL
0
CL
1
CL
2
CL
3
SL
0
SL
1
SL
2
SL
3
S0
S1
S2
S3
0
1
PG
_L
PG
_L
PG
_L
PG
_L
CL
4
CL
5
CL
6
CL
7
SL
4
SL
5
SL
6
SL
7
S4
S5
S6
S7
0
1
A8 B8 A9 B9 A10 B10 A11 B11
PG
_L
PG
_L
PG
_L
PG
_L
CL
8
CL
9
CL
10
CL
11
SL
8
SL
9
SL
10
S10
S8
S9
GP 2= P8P9P10P11
PG
_L
A4 B4 A5 B5 A6 B6 A7 B7
GP 1= P4P5P6P7
A0 B0 A1 B1 A2 B2 A3 B3
GP 0= P0P1P2P3
Highlight the critical path for this 16-bit adder directly on Figure 1 (4 points)
A12 B12 A13 B13 A14B14 A15 B15
PG
_L
PG
_L
PG
_L
PG
_L
CL
12
CL
13
CL
14
CL
15
SL
11
SL
12
SL
13
SL
14
SL
15
S11
S12
S13
S14
S15
0
1
Cout,15
Figure 1: A 16 bit Carry Skip Adder with a block size M = 4.
(b) What is the delay for a 32-bit adder assuming equal block sizes of 4 and making the same assumptions of delay as
1 (a)? (4 points)
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(c) Consider an N-bit Carry Skip adder with equal block sizes of M-bits. With the same timing assumptions of 1(a),
derive the optimum block length M, for an N-bit adder. (6 points)
(d) Consider a transmission gate implementation of a 4-bit Carry-Skip section. Derive the signals S1, S2, and S3 as a
function of Pi and Gi. Will this circuit work if Pi = A +B? Explain. (8 points)
S1
Cout,3
Cin
S2
P0
G2
G1
G0
P1
G3
P2
S3
Figure 2: A transmission gate implementation of a 4-bit Carry Skip section.
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(e) Consider the following 32-bit adder variation where the block sizes of each stage are not equal. Highlight the critical path directly on Figure 3. What is the delay of the critical path? (8 points)
A0,B0
A1-3,B1-3
A4-8,B4-8
P,
G
P,G
P,G
0
Bits1-3
Bits 4-8
Bits 9-15
0
Bits1-3
Bits 4-8
Bits 9-15
A9-15,B9-15
A16-22,B16-22
A28-30,B28-30 A31,B31
P,G
P,G
P,
G
Bits 16-22
Bits 23-27
Bits
28-30
31
Bits 16-22
Bits 23-27
Bits
28-30
31
P,G
P,G
A23-27,B23-27
Sum Logic
Figure 3: A 32-bit Carry Skip Adder with a variable block size.
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Problem 2: Sequential Element: Consider the following circuit. Assume that each inverter takes 1 time unit for a
low-to-high or high-to-low transition. Assume that it takes 1 time unit for a pull-up path or pull-down path to pull-up
or pull-down, respectively. Ignore any leakage effects. Assume VDD >> VT. Also assume that there is no skew
between CLK and CLK and assume that the rise/fall times on all signals are zero.
VDD
D
VDD
Symbol
X
I1
I2
I3
SE
CLK
I4
I5
Q
I6
D
Q
CLK
Y
D
CLK
Figure 4: Sequential Element.
(a) Complete the timing diagram below. What type of sequential element is the above circuit? Be specific. (8 points)
1
CLK
D
X
Q
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(b) What is the setup time, tsu, hold time, thold and propagation delay, tp of this sequential building block relative to
the appropriate edge(s)? Explain. (6 points)
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(c) Consider the following simple sequential system built using the sequential element in Figure 4. Assuming that
there is no skew in distributing the clock, what is the minimum possible clock period for which this sequential system will function? Assume that the primary input In is setup before the appropriate clock edge(s). (6 points)
SE1
In
D
Q
CLK
SE2
Combinational
Logic
tlogic (cd) = 2
tlogic = 10
D
Q
Out
CLK
Figure 5: Simple Sequential System.
(d) What is the maximum positive skew on the clock to SE2 such that the circuit still functions? (4 points)
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Problem 3: Sequential Circuit: Consider the following circuit. Assume that each inverter takes 1 time unit for a
low-to-high or high-to-low transition. Also assume that it takes 1 time unit for a pull-up path or pull-down path to
pull-up or pull-down, respectively. Assume that ratioed circuits are properly sized (i.e., assume that the devices in the
cross-coupled inverters are weak and can be overpowered). Assume that the rise/fall times on all signals are zero.
I10
I3
Eval
QSD
I9
VDD
I8
END
I7
CLK
I6
I2
Eval#
QSD#
I5
VDD
VDD
CLK
I1
I4
D
CLK
VDD
CLK
CLK
Figure 6: Sequential Circuit.
(a) Complete the following timing diagram for QSD, QSD#, END. (8 points)
1
CLK
D
END
QSD
QSD#
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(b) Assuming that the circuit of Figure 6 directly drives a dynamic DCVSL gate (i.e., differential N-type dynamic
logic clocked by CLK), what is the setup time of the circuit in Figure 6 relative to the appropriate clock edge?
Explain. (4 points)
(c) What is the hold time, thold and propagation delay, tp, of the circuit in Figure 6 relative to the appropriate clock
edge? (4 points)
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(d) Consider the following sequential implementation which includes both differential dynamic logic and static logic.
The circuit below has a major problem. Identify the problem and propose a solution (draw a gate level schematic).
(6 points)
D
CLK
Dynamic Out
DCVSL
Logic
Figure 6
gate
Out#
QSD#
Circuit of
QSD
Static
Logic
Out_static
Positive
Edge
Triggered
Register
CLK
CLK
Figure 7: Sequential System.
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Problem 4: Interconnect Issues: For this entire problem assume CI/CL = 5. (CI is the interwire capacitance and CL is
the line capacitance to the substrate). An inverter is modeled using resistors and an ideal switch. The switch is connected either to the top resistor or the bottom resistor.
(a) Consider the 2-line bus shown in Figure 8. Compute the total energy drawn from the power supply VDD for the
transition of (In0, In1) from 01 to 10. (6 points)
VDD
R
R
In0
LINE 0
CL
CI
In1
LINE 1
CL
Figure 8: 2-bit bus.
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(b) Consider the following modification in which the inverters are replaced by tri-state inverters. When the enable
signal En is low, the tri-state does not drive the LINE. In addition, a switch with a small resistance R is added in parallel with CI which is closed when the control signal S = 1. Consider the same transition as 4(a) in which (In0, In1)
switches from 01 to 10. However, before the transition happens, the switch is shorted and then opened. Assume that
the time period when the switch is closed is long enough for all the transients to settle. Compute the total energy
drawn from the power supply VDD. (8 points)
VDD
R
En
In0
R
In1
En
En
LINE 0
In0
CL
R
En
In1
S
CI
S
LINE 1
CL
Figure 9: Modified driving scheme for a 2-bit bus.
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(c) Consider the following input sequence, which represents all the possible transitions for 2 input bus.
Transition Sequence: 00J00J01J10J11J00J10J10J01J11J01J01J00J11J11J10J00
What is the difference in energy drawn from the power supply for the above sequence using the approach in 4(b) vs.
4(a). For the scheme in part 4 (b), assume that you may choose on a transition by transition basis if the switch should
be closed before the transition happens. If the switch is closed between transitions, assume that the tri-state driver is
off during that period. (10 points)
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