Development of l6-channel communication multiplexor for Hewlett Packard 2100 series computers
by Richard David Weaver
A thesis submitted to the Graduate Faculty in partial fulfillment of the requirements for the degree of
MASTER OF SCIENCE in Electrical Engineering
Montana State University
© Copyright by Richard David Weaver (1974)
Abstract:
The subject of this thesis is the design, development and construction of a low-cost 16-channel
communication multiplexor (MUX) used for interfacing from 1 to 16 teletypes, modems or other
bit-serial devices to a single I/O channel on a Hewlett Packard 2100 series computer.
This thesis discusses the following items: First, reasons for the project and the problems to be solved
are presented and discussed. Second, specifications of the hardware to be interfaced are presented,
along with a detailed description of the specifications for the MUX. Third, the logic design used to
realize the MUX is described. This section ends with a short summary of testing procedures used to
verify correct operation of the logic. In the fourth section the physical and mechanical design and
construction is presented. The thesis ends with an analysis and discussion of the overall performance
and success of the project. In p r e s e n t i n g . t h i s t h e s i s in p a r t i a l f u l f i l l m e n t o f t h e r e ­
qu ire me nts f o r an advanced degree a t Montana S t a t e U n i v e r s i t y , I
a g re e t h a t t h e L i b r a r y s h a l l make i t f r e e l y a v a i l a b l e f o r i n s p e c t i o n .
I f u r t h e r ag re e t h a t permi ssi on f o r e x t e n s i v e copying o f t h i s t h e s i s
f o r s c h o l a r l y purposes may be g r a n t e d by my major p r o f e s s o r , o r ,
in h i s a bse n c e , by t h e D i r e c t o r of L i b r a r i e s .
I t i s understood
t h a t any copying o r p u b l i c a t i o n o f t h i s t h e s i s f o r f i n a n c i a l gain
s h a l l n o t be allowed w it h o u t my w r i t t e n pe rm is si o n .
Si m&ture & s J l^
D ate/ 7 ^
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rJ J9 :
/I Oy
DEVELOPMENT OF A 16-CHANNEL COMMUNICATION MULTIPLEXOR
. FOR HEWLETT PACKARD 2100 SERIES COMPUTERS
by
RICHARD DAVID WEAVER
A t h e s i s su bmi tte d t o t h e Graduate F a c u l t y in p a r t i a l f u l f i l l
rhent o f t h e re q u ir e m e n ts f o r t h e degree
of
MASTER OF SCIENCE
in .
E l e c t r i c a l Engineering
Approved:
■flead. Major Department
Chairman, Examining Committee
Graduate^Dean
MONTANA STATE UNIVERSITY
Bozeman, Montana
J u n e , 1974
/
Ii i
ACKNOWLEDGMENT
The development o f a l a r g e d i g i t a l system r e q u i r e s t h e r e ­
s o u rc es and t a l e n t o f many pe o p le .
The a u t h o r wishes t o thank th e
people in t h e E l e c t r o n i c s Research L a borator y a t Montana S t a t e
U n i v e r s i t y f o r t h e i r help and t h e use o f t h e shop, stockroom and
p h ot og ra ph ic equipment.
The f a b r i c a t i o n o f p r i n t e d c i r c u i t c ar d s and s h e e t metal
c o n s t r u c t i o n was done by Development Technology In c o r p o r a t e d o f
Bozeman, Montana.
The w r i t e r i s de ep ly g r a t e f u l t o Western Telecomputing Cor­
p o r a t i o n f o r f i n a n c i a l s u p p o r t , f a c i l i t i e s and equipment used in
d e s i g n i n g , b u i l d i n g and t e s t i n g t h e system.
R.D.W.
iv
TABLE OF CONTENTS
Chapter
I.
II.
III.
IV.
Page
INTRODUCTION..............................
I
1.1
1.2
I n t r o d u c t i o n .............................................................................
Background and P r o j e c t I n t r o d u c t i o n .................
I
i
THE SPECIFICATIONS OF THE MULTIPLEXOR.................... ...............
4
2.1
2 .2
2 .3
2 .4
2 .5
2 .6
2 .7
2.8
2.9
2.10
2.11
2.12
4
4
I n t e r f a c e S p e c i f i c a t i o n s ...................................
I/O Computer I n t e r f a c e S p e c i f i c a t i o n s ......................
S e r i a l I/O Device I n t e r f a c e S p e c i f i c a t i o n s . . . . . .
M u l t i p l e x o r S p e c i f i c a t i o n s . ............................................
The Data Output W o r d .. .......................................................
Mode C o n t r o l ...................................... .................. ...................
C le a ri n g Flags and S t a r t i n g O u tp ut...............................
C le a ri n g t h e Power Fa il F l a g . ........................................
The Data Input Word....................................................
S e r i a l Data Co nv ersio n.......................................................
P r i o r i t y I n t e r r u p t System................................................
Summary.......................................
g
g
g
10
13
14
14
16
17
18
THE HARDWARE DESIGN OF THE MULTIPLEXOR.....................
ig
3.1 . I n t r o d u c t i o n ................................................................
3 .2
Logic D i v i s i o n ........................................................................
3 .3
Signal D e f i n i t i o n s ................................................................
3 .4
Common Logic F u n c t i o n s ............... .....................................
3.5
Channel L o g i c ...........................................................................
3 .6
T e s t i n g o f t h e M u l t i p l e x o r ..........................
3 .7 Summary...............................
19
19
20
21
25
31
33
THE MECHANICAL DESIGN OF THE MUX.............................................. 34
4 .1
4 .2
4 .3
4.4
4.5
4 .6
I n t r o d u c t i o n ............................
Card Cages........................................................................
P r i n t e d C i r c u i t C a r d s .........................................
C a b l e s , Connectors and Backplane W i r i n g . . . . ...........
Power S u p p l y . . ............................
Summary...............................................
34
34
35
37
38
3g .
V
TABLE OF CONTENTS
Chapter
V.
Page
FINAL EVALUATION, PERFORMANCE AND CONCLUSION....,......... ..
5.1
5 .2
5 .3
5 .4
5 .5
40
I n t r o d u c t i o n ............. .................
40
, C o n s t r u c t i o n , T e s ti n g and T r o u b l e - S h o o t i n g .................. 40
C o s t .................
41
R e l i a b i l i t y and Perf orm an ce.................................
42
C o n c l u s io n ...........................
43
vi
LIST OF FIGURES
Figure
Page
2.1
Mux System Block Diagram..........................................................
5
2 .2
S e r i a l Data Format............. .................................................................
8
2 .3
Computer Output Word B i t D e f i n i t i o n . ....................................... 11
2.4
Computer Data In p u t Word B i t D e f i n i t i o n .
3.1
Common Logic F u n c t i o n s ...................................................................... 22
3.2
Channel L og ic .....................
27
4.1
Mux Physical L a y o u t . . . . .................
36
.......................... 15
vii
ABSTRACT
The s u b j e c t o f t h i s t h e s i s i s t h e d e s i g n , development and con­
s t r u c t i o n o f a lo w -c o s t 16-channel communication m u l t i p l e x o r (MUX)
used f o r i n t e r f a c i n g from I t o 16 t e l e t y p e s , modems o r o t h e r b i t s e r i a l d e v i c e s t o a s i n g l e I/O channel on a Hewlett Packard 2100
s e r i e s computer.
This t h e s i s d i s c u s s e s t h e f o l l o w i n g ite m s : F i r s t , re a so n s f o r
t h e p r o j e c t and t h e problems t o be so lve d a r e p r e s e n t e d and d i s c u s s e d .
Second, s p e c i f i c a t i o n s o f t h e hardware t o be i n t e r f a c e d a r e p r e s e n t e d ,
along w it h a d e t a i l e d d e s c r i p t i o n o f t h e s p e c i f i c a t i o n s f o r t h e MUX.
T h i r d , t h e l o g i c d e si gn used t o r e a l i z e t h e MUX i s d e s c r i b e d . This
s e c t i o n ends w it h a s h o r t summary o f t e s t i n g pro c e dur es used to
v e rify c o r r e c t operation of the lo g ic .
In t h e f o u r t h s e c t i o n th e
ph y s ic a l and mechanical desi gn and c o n s t r u c t i o n i s p r e s e n t e d . The
t h e s i s ends with an a n a l y s i s and d i s c u s s i o n o f t h e o v e r a l l performance
and su cc e ss o f t h e p r o j e c t .
CHAPTER I
INTRODUCTION .
1.1
INTRODUCTION
This t h e s i s d e s c r i b e s t h e s p e c i f i c a t i o n s , desi gn and con­
s t r u c t i o n o f a 16-Channel Communication M u l t i p l e x o r .
The m u l t i ­
p l e x o r (MUX) p ro v i d e s a way o f i n t e r f a c i n g from I t o 16 b i t s e r i a l
( t e l e t y p e ) d a t a c ha n n e ls t o a Hewlett Packard (HP) 2100 s e r i e s
computer.
This t h e s i s i s o r ga ni z ed in c h a p t e r form as d e s c r i b e d below.
Chapter one p ro v id e s t h e i n t r o d u c t i o n and re a so n s f o r t h e p r o j e c t .
Chapter two e x p l a i n s t h e computer i n t e r f a c e , m u l t i p l e x o r and I/O
de vi ce s p e c i f i c a t i o n s .
Chapter t h r e e d e s c r i b e s t h e d e si gn and t e s t i n g ,
pr o c e d u re s used in de ve lo pi ng t h e MUX.
Chapter f o u r d e s c r i b e s th e
c o n s t r u c t i o n t e c h n i q u e s and problems encoun tere d in a c t u a l l y b u i l d i n g
a working model.
Chapter f i v e d i s c u s s e s t h e o v e r a l l e f f e c t i v e n e s s
o f t h e p r o j e c t upon i t s c o m pl e tio n.
R e l a t i v e c o s t , performance and
r e l i a b i l i t y are also discussed.
1.2
BACKGROUND AND PROJECT INTRODUCTION
This p r o j e c t was s t a r t e d when i t became n e c e s s a r y t o connect
16 t e l e t y p e s t o an HP 2116B computer f o r use with Time-Share Basic.
A ls o, a l a r g e number o f s e r i a l d a t a i n p u t c hann el s were needed in d a t a
2
a c q u i s i t i o n systems t h a t were being developed.
There were two
p o s s i b l e ways t o do t h i s i n t e r f a c i n g b e fo re t h e MUX was c o n s t r u c t e d
and both were ex pen s iv e and n o t ve ry s a t i s f a c t o r y .
The f i r s t c o n s i s t e d o f buying one t e l e t y p e i n t e r f a c e card f o r
each channel t o be i n t e r f a c e d .
The c o s t per channel was high and each
channel implemented r e q u i r e d one i n p u t - o u t p u t (I/O) s l o t in t h e com­
puter.
There a r e o nly 19 I/O s l o t s t o t a l in t h e 2116B computer and
two a r e used t o i n t e r f a c e a d i s c d r i v e , one i s r e q u i r e d f o r a cl ock
and t h r e e more f o r a high speed p a p e r ta p e r e a d e r , high speed pa per t a p e punch and c o n s o le t e l e t y p e .
T h e r e f o r e , only 13 s l o t s were a v a i l ­
able f o r user te le ty p e channels.
Also t h e 2116B computer cannot
supp ly enough c u r r e n t t o t h a t much I/O equipment so a power supply
e x t e n d e r ( a l s o ex p en s iv e ) must be i n s t a l l e d .
Therefore, to in te rfa c e
o nl y 13 u s e r c h a n n e ls o f B a s i c , r e q u i r e d having 13 i n t e r f a c e bo a rd s,
a power supply e x t e n d e r and usi ng every a v a i l a b l e I/O s l o t .
The o t h e r a l t e r n a t i v e was t o buy a n o t h e r e n t i r e HP 2114 computer
and t h e HP s o ft w a re m u l t i p l e x o r .
This uses only one 16 p a r a l l e l - b i t
board which brought in t h e 16 t e l e t y p e c h a n n e l s , one on each o f i t s
16 i n p u t b i t s .
Then by sampling a t a high f r e q u e n c y , t h e waveforms
coming in on each l i n e could be r e c o n s t r u c t e d by t h e computer.
The.
whole I/O p ro c e s s c o m p le te ly t i e d up one computer making t h e c o s t f o r
t h i s s o l u t i o n very e x p e n s iv e .
Also f o u r 16 b i t s - I / O c a r d s were r e ­
q u i r e d f o r d a t a t r a n s f e r between t h e 2114 I/O computer and t h e 21168
3
p r o c e s s o r computer.
During t h e development o f t h i s p r o j e c t , HP r e p l a c e d th e o l d e r
2116, 211.4 and 2115 s e r i e s computers with t h e HP2100A computer.
This
computer, which th e y a r e s t i l l p r e s e n t l y s e l l i n g , has only 13 I/O
s l o t s t o t a l , l e a v i n g o nly 7 f o r t i m e - s h a r e Basic u s e r s .
With t h i s
computer t h e need f o r a m u l t i p l e x o r f o r t i m e - s h a r e u s e r s was g r e a t e r
than e v e r .
The need f o r a m u l t i p l e x i n g d e v i c e can now be c l e a r l y seen.
What i s needed i s some "black box" t h a t w i l l con nec t t o 16 s e r i a l
d a t a c ha n n e ls ( t e l e t y p e s ) and i n t e r f a c e to th e computer through only
one I/O c h a n n e l .
This one i n t e r f a c e t o t h e computer, however, must
no t keep t h e computer so c om ple te ly t i e d up in I/O t h a t i t cannot do
o t h e r o p e r a t i o n s as was one o f t h e problems with t h e HP sof tw are
MUX.
CHAPTER II
THE SPECIFICATIONS OF THE MULTIPLEXOR
2.1
INTERFACE SPECIFICATIONS
The f i r s t s t e p in d e s i g n i n g t h e m u l t i p l e x o r i s d e f i n i n g or
s t a t i n g in d e t a i l t h e s p e c i f i c a t i o n s o f t h e computer i n t e r f a c e and
t h e I/O equipment ( t e l e t y p e , modem o r o t h e r b i t - s e r i a l d e v i c e ) .
Fig ur e 2.1 c o n t a i n s a bloc k diagram o f t h e o v e r a l l system showing
computer, MUX, and I/O de v ic e i n t e r c o n n e c t i o n s .
2.2
I/O COMPUTER INTERFACE SPECIFICATIONS.
The computer i n t e r f a c e s e l e c t e d i s a s ta n d a rd HP 16 b i t ,
p a r a l l e l f u l l - d u p l e x I/O c a r d .
This g iv e s two indepen de nt s t o r a g e
r e g i s t e r s , one f o r 16 d a ta o u t p u t b i t s (from t h e computer) and one
f o r 16 d a t a i n p u t b i t s ( t o t h e c o m p u t e r ) .
Also a "Device Command"
si g n al i s a v a i l a b l e t h a t can be used t o t e l l an e x t e r n a l dev ice to
t a k e some a c t i o n .
Another l i n e , "Device Flag" can be used by th e
e x t e r n a l de v ic e t o s i g n a l t o t h e computer.
The o p e r a t i o n o f t h e I/O i n t e r f a c e board can th e n be summarized
as f o l l o w s :
The computer can s t o r e 16 b i t s o f in f o r m a t io n in th e
d a t a o u t p u t r e g i s t e r with an OTA o r OTB i n s t r u c t i o n .
The c o n te n t s
d o n ' t change u n t i l t h e computer s t o r e s a n o t h e r 16 b i t s i n t h e r e g ­
ister.
The "Device Flag" l i n e i s puls ed ( f o r a ppro xim a te ly I y s e c ) ,
5
COMPUTER
I/O
I NTE RFA CE
COMMON
LOGI C
USER I
CHANNEL I
LOGI C
USER
2
CHANNEL 2
LOGIC
USER 16
C H A N N E L 16
L OG I C
IVIUX
FIGURE 2.1
MUX SYSTEM BLOCK DIAGRAM
6
once e ve r y time a Se t Control i n s t r u c t i o n i s e x e c u t e d .
Whatever
d a t a i s p r e s e n t on t h e 16 d a t a i n p u t l i n e s coming from t h e e x t e r n a l
de v ic e w i l l be loaded i n t o t h e . d a t a i n p u t r e g i s t e r when t h e "Device
Flag" l i n e i s p u l s e d .
Thi s p u ls e a l s o s e t s t h e I/O channel f l a g
i n d i c a t i n g t o t h e computer t h a t new d a t a i s a v a i l a b l e .
The Computer
can then b r in g in t h e d a t a s t o r e d in t h e i n p u t r e g i s t e r (with an LIA
or LIB) and t a k e whatever a c t i o n i t may d e s i r e , depending on t h e r e ­
s u l t s o f t h e i n p u t d a t a word.
All s i g n a l s d e s c r i b e d above a r e g e n e r a te d by s t a n d a r d (7400
s e r i e s ) TTL l o g i c g a t e s .
This means a l o g i c 0 = 0 t o .8 v o l t s , a
l o g i c I = 2 t o 5 v o l t s and v o l t a g e o u t s i d e t h i s range a f t e r t r a n s i t i o n s
a r e un de fin e d.
The c u r r e n t t h a t must be drawn from an i n p u t in th e
l o g i c 0 s t a t e i s 1 .6 mA maximum and f o r a l o g i c I s t a t e 10 uA must be
supplied.
The t r a n s i t i o n time from one l o g i c s t a t e t o t h e o t h e r i s
t y p i c a l l y 5-50 ns .
Each l o g i c o u t p u t i s c ap a ble o f d r i v i n g a t l e a s t
10 l o g i c i n p u t s f o r a f a n - o u t o f t e n .
The l i n e d r i v e r s (SN7416 and
SN7417) a r e c ap a bl e o f d r i v i n g 20 g a t e i n p u t s .
The MUX was c o n s t r u c t e d
usi ng TTL l o g i c f o r c o m p a t a b i l i t y w it h t h i s computer i n t e r f a c e .
2 .3
SERIAL 1/0 DEVICE INTERFACE SPECIFICATIONS
At t h e u s e r end o f t h e MUX, 16 ch an nel s o f s e r i a l d a ta a r e to
be i n t e r f a c e d .
For each channel t h e r e i s one l i n e coming from a
te r m i n a l and one going t o t h e te rm in a l over which t h e d a t a i s t r a n s -
7
f erred.
F ig ure 2 .2 c o n t a i n s t h e ti m in g diagram showing t h e s t r u c t u r e
of the s e r i a l data s i g n a l .
Al I d a t a s i g n a l s w a i t in t h e l o g i c I or marking c o n d i t i o n .
When
a c h a r a c t e r i s t o be s e n t , a s t a r t p u ls e o f one b i t d u r a t i o n i s o u t p u t
in t h e l o g i c 0 o r space c o n d i t i o n followed by t h e 8 in f or m at io n b i t s .
The c h a r a c t e r i s te r m i n a t e d by one o r two (depending on t h e de vic e)
stop b i t s .
C h a r a c t e r s a r e t r a n s m i t t e d asy nc hro nous ly with t h e s t a r t
and st o p b i t s d e f i n i n g each c h a r a c t e r .
The MUX can a l s o be i n t e r f a c e d d i r e c t l y t o a modem f o r d a ta
t r a n s m i s s i o n over te le p h o n e l i n e s t o remote u s e r s .
In t h i s case
t h r e e c o n t r o l l i n e s ; r i n g i n g i n d i c a t o r , c a r r i e r d e t e c t and d a ta te rm in a l
ready a r e n e c e s s a r y on each channel f o r c o n t r o l o p e r a t i o n s .
The r i n g i n d i c a t o r l i n e i s . u s e d t o t e l l t h e computer when a
channel i s being c a l l e d .
The d a t a te rm in a l ready l i n e i s used to
al low t h e modem t o answer o r once answered can t e r m i n a t e a c a l l .
The
c a r r i e r d e t e c t t e l l s t h e computer whether o r not t h e customer has
p r o p e r l y connected h i s modem f o r d a t a t r a n s m i s s i o n .
T h e r e f o r e , f o r each channel two s e r i a l d a ta l i n e s , a r i n g i n d i c a t o r
l i n e , c a r r i e r d e t e c t l i n e and d a t a t e rm in a l ready a r e r e q u i r e d .
Modems and many b i t - s e r i a l I/O d e v ic e s o p e r a t e usi ng EIA RS232
s ig n a l l e v e l s .
These l o g i c l e v e l s r e q u i r e a l o g i c I t o be in the
range o f +3V t o +25V and a l o g i c 0 t o be in t h e range o f -3V to -25V
a l t h o u g h OV t o -25V i s o f t e n used f o r a l o g i c 0.
The TTL l e v e l s a re
a
SERIAL DATA FORMAT
(GROUND TRUE TTL SIGNAL)
O
START
I
2
3
4
5
INFORMATION BITS
STANDARD B IT TIM ES
HO
B A U D -9 .0 9 m s /B I T
3 0 0 B A U D -3 .3 3 m s /B I T
FIGURE 2 . 2
6
7
STOP
9
a l s o wide ly used so both s i g n a l ty p e s (EIA and TTL) a r e made a v a i l ­
able.
2 .4
MULTIPLEXOR SPECIFICATIONS
The s p e c i f i c a t i o n o f t h e MUX can now proceed and must mesh
e f f e c t i v e l y w it h t h e o p e r a t i o n o f t h e computer i n t e r f a c e board and
t h e d a t a t e r m i n a l s and modems.
The f i r s t s t e p w i l l d e f i n e t h e meanings
and o p e r a t i o n s a s s o c i a t e d with t h e 16 b i t computer o u t p u t word.
Then
t h e 16 b i t computer d a t a i n p u t word s u p p l i e d by t h e MUX must be
defined.
. ,
I t i s in t h e s e s p e c i f i c a t i o n s t h a t t h e o v e r a l l e f f i c i e n c y o f t h e
MUX w i l l be d e te r m in e d.
I f the y a r e awkward t h e MUX w i l l be hard to
program and t h e computer w i l l spend l a r g e amounts o f time p r o c e s s in g
I/O.
Remember t h e d e s ig n i s t o be used with only one computer and
16 u s e r s a l l runn ing timer-share Basic and t h e time devoted to exe­
c u t i n g programs must be maximized.. Also i n e f f i c i e n t s p e c i f i c a t i o n s
can le a d t o more complex l o g i c r e a l i z a t i o n s f o r a given j o b and hence
t h e o v e r a l l pro d u c t w i l l c o s t more than n e c e s s a r y .
2.5
THE DATA OUTPUT WORD
The f i r s t s t e p in t h e MUX s p e c i f i c a t i o n i s d e f i n i n g t h e computer
o u t p u t word.
By o u t p u t t i n g a s e r i e s o f t h e s e words t h e computer
c o n t r o l s t h e e n t i r e o p e r a t i o n o f t h e MUX.
10
In Figure 2 .3 i t can be seen t h a t a l l n e c e s s a r y d a t a and
in f o r m a t io n can be s u p p l i e d to one MUX channel in one computer s te p
o f l o a d in g t h e o u t p u t r e g i s t e r o f t h e I/O c a r d .
The "Device Command"
s i g n a l i s then p uls ed t o t e l l t h e MUX t h a t t h e . d a t a i s c o r r e c t arid
can be a c c e p t e d .
Now from a programming p o i n t o f view, t h e o p e r a t i o n
o f o u t p u t t i n g i n f o r m a t i o n t o t h e MUX i s a t h r e e - s t e p p r o c e s s .
t h e 16 b i t d a ta word i s assembled in t h e computer.
First,
Second, i t i s
s t o r e d on t h e I/O r e g i s t e r c ar d where t h e s i g n a l s a r e a c t u a l l y
t r a n s f e r r e d t o t h e MUX.
Then t h e S e t Control i n s t r u c t i o n i s executed
which p u l s e s "Device Command" c a u s in g t h e MUX t o a c c e p t t h e new d a t a .
2 .6
"MODE" CONTROL
There a r e two ty p e s o f o u t p u t t o a channel as i l l u s t r a t e d in
Figure 2 . 3 .
The f i r s t ty pe s e t s up t h e "Mode" o f t h e channel and i s
determined by b i t 15 = I and b i t 0 = 0.
B i t s 8 through 11 det ermi ne t h e channel a d d r e s s in t h e fo ll ow in g
manner.
I f a l l f o u r b i t s = 0 then channel I i s a c c e s s e d .
Then
by c o u n ti n g up in b i n a r y , each channel i s s e l e c t e d in t u r n , acc ording
to i t s binary r e p r e s e n ta tio n .
With f o u r b i t s , 2^ = 16 combinations
a r e p o s s i b l e , which i s t h e r e q u i r e d number.
As an example, an o u t p u t
o f 0110 f o r b i t s 11 through 8 would s e l e c t channel 7.
When s e t t i n g t h e "mode", b i t s 1-7 a r e ignored by t h e c h a n n e l .
B i t s 12 through 14 de te rm in e the. "mode" o r s t a t e o f a channel and
11
OUTPUT CHARACTER
( OHLY LOADED I F 1 5 = 0 AND 1 2 = 1 )
CHANNEL ADDRESS
I F B IT 1 5 = 0
1 2 = 1 CLEARS "OUTPUT COMPLETE FLAG"
1 3 = 1 CLEARS "CHARACTER RECEIVED
FLAG"
1 4 = 1 CLEARS "R IN G INDICATOR AND
CARRIER DETECT FLAG'
I F 1 5 = 1 AND O=O
1 2 = 1 ENABLES CHARACTER OUTPUT
1 3 = 1 ENABLES CHARACTER ECHO
1 4 = 1 ENABLES CHARACTER INPUT
1 2 = 1 3 = 1 ENABLES ECHO
DISABLES OUTPUT
DISABLES DATA TERMINAL RDY
1 5 = 0 CLEAR FLAGS
1 5 = 1 AND O=O SET MODE
1 5 = 1 AND 0 = 1 CLEAR POWER UP FLAG
FIGURE 2.3
COMPUTER
OUTPUT WORD BIT DEFINITION
12
must de te rm in e t h e f o l l o w i n g i t e m s ; t h e s t a t e o f d a t a te rm in a l
r e a d y , t h e e nab le o r d i s a b l e o f inputj, t h e e nab le o r d i s a b l e o f
o u t p u t and one o t h e r f e a t u r e c a l l e d echo.
In t h e echo-on mode,
d a t a coming.in on t h e s e r i a l d a t a - i n l i n e i s wrapped around and
t r a n s m i t t e d back o u t on t h e s e r i a l d a t a - o u t l i n e .
In t h i s ca s e d a ta
should not s i m u l t a n e o u s l y be o u t p u t by t h e computer through th e
o u t p u t r e g i s t e r because an " ori ng" o f t h e s i g n a l s would r e s u l t .
The o t h e r p o s s i b i l i t y i s e c h o - o f f .
In t h i s mode d a t a coming in on
t h e s e r i a l d a t a - i n l i n e i s kept co m p le te ly s e p a r a t e from t h a t being
o u t p u t by t h e computer on t h e s e r i a l d a t a - o u t l i n e .
Thi s independent
t r a n s m i t t i n g and r e c e i v i n g o f d a t a i s c a l l e d Full -Du ple x o p e r a t i o n .
The modes a r e determined by t h e b i t p a t t e r n s as shown in
Fig ur e 2 .3 and d e s c r i b e d below.
12 = 0 d i s a b l e s o u t p u t .
d i s a b l e s echo.
B i t 12 = I e n a b le s o u t p u t and b i t
B i t 13 = I e n a b l e s echo and b i t 13 = 0
B i t 14 = I e n a b le s i n p u t and b i t 14 = 0 d i s a b l e s i n p u t .
One combination t h a t should no t be allowed as d i s c u s s e d above i s
o u t p u t en abled and echo on.
echo i s enab le d
For t h i s c a s e ( b i t 1 2 = 1 ,
bi t 1 3 = 1 )
o u t p u t i s d i s a b l e d and d a t a te rm in a l read y i s f a l s e .
This mode would no t normally be used w hil e a u s e r i s a c c e s s i n g th e
system and p ro v id e s t h e p e r f e c t c a s e t o te r m i n a t e a c a l l by s e t t i n g
d a t a t e rm in a l ready f a l s e .
minal r e a dy t r u e .
All o t h e r b i t combinations s e t d a ta t e r ­
13
2.7
CLEARING FLAGS AND STARTING OUTPUT
The second ty pe o f o u t p u t t o a c h a n n e l , a l s o shown in Figure
2 . 3 , i s t h a t o f c l e a r i n g f l a g s and o u t p u t t i n g c h a r a c t e r s .
done by s e t t i n g b i t 15 = 0.
a r e s e t as f o l l o w s :
This i s
There a r e t h r e e f l a g s r e q u i r e d which
When i n p u t i s complete t h e " c h a r a c t e r r e c e iv e d "
f l a g i s s e t ; when o u t p u t i s complete t h e "o utp ut complete" f l a g i s
s e t ; and when t h e r i n g i n g i n d i c a t o r o r c a r r i e r d e t e c t s i g n a l s change
s t a t e , the th ir d fla g is s e t.
Remember t h a t t h e d a ta coming in t o
o r o u t o f a channel t o t h e I/O d e v ic e o r modem i s in s e r i a l form.
T h e r e f o r e , each channel must perform a s e r i a l - t o - p a r a l l e l o r p a r a l l e l t o - s e r i a l b i t conversion.
This t a k e s , by computer r e f e r e n c e , a very
long time and d u r in g a c on v e r si o n t h e computer must be f r e e t o do o t h e r
t a s k s and then be t o l d when t h e v a r i o u s o p e r a t i o n s a r e complete.
To c l e a r t h e f l a g s t h e d a ta word i s assembled in t h e computer,
o u t p u t t o t h e MUX thro ugh t h e I/O c a r d and then a Set Control
i n s t r u c t i o n i s ex ecuted as d e s c r i b e d b e f o r e .
s e l e c t t h e c h an ne l.
B i t s 8 through 11
B it 14 = I c l e a r s t h e " ri n g i n d i c a t o r and c a r r i e r
detect flag ", b it 1 3 = 1
c l e a r s t h e " c h a r a c t e r r e c e i v e d f l a g " and
b i t 12 = I c l e a r s t h e " outp ut complete f l a g " .
When t h e "output
complete f l a g " i s c l e a r e d , t h e o u t p u t s h i f t r e g i s t e r i s loaded with
b i t s 0-7 and a new s e r i a l o u t p u t s t a r t e d i f a v a l i d o u t p u t mode was
s e t up ahead o f ti m e .
14
2 .8
CLEARING THE POWER FAIL FLAG
I f , f o r any r e a s o n , t h e MUX should have a power f a i l u r e o r ,
power i s i n i t i a l l y tu r n e d o n, t h e power f a i l f l a g w i l l s e t .
This
c a u s e s t h e computer t o load t h e i n p u t s t a t u s word informing the
computer o f t h e power f a i l u r e .
To c l e a r t h e f l a g an o u t p u t word
o f 1XXXXXXXXXXXXXX1 ( b i t 15 and b i t 0 = I , a l l o t h e r s = I o r 0)
i s loaded followed by t h e usual Se t Control i n s t r u c t i o n .
After t h i s
o p e r a t i o n t h e MUX i s re ad y f o r normal, us e.
2.9
THE DATA INPUT WORD
The second p a r t o f t h e MUX s p e c i f i c a t i o n d e f i n e s t h e 16 b i t
computer i n p u t word.
There i s only one meaning a t t a c h e d t o each
b i t o f t h e i n p u t word and i s diagrammed in Figure 2 . 4 .
There i s a d e si gn problem s t i l l t o be solved t h a t must determine
which channel s h a l l be allowed t o i n p u t d a t a i f t h e r e should be a
m ultiple request fo r service.
But, assuming one has been s e l e c t e d ,
"Device Flag" can be pul s ed by t h e MUX t o load t h e d a t a i n t o th e
computer.
The d e f i n i t i o n o f b i t meaning i s given in Fi gure 2.4 and
d e s c r i b e d below.
B i t s 8 - 1 1 de te rm in e t h e channel r e q u e s t i n g s e r v i c e as d e s c r i b e d
in t h e l a s t s e c t i o n .
B i t 12 i s used t o i n d i c a t e t h e completion o f a
d a t a o u t p u t ( p a r a l l e l - t o - s e r i a l b i t - c o n v e r s i o n ) and b i t 13 t h e com­
p le tio n of a data input ( s e r i a l - t o - p a r a l I e l ) operatio n .
I f b i t 13
15
IilPU T CHARACTER
CHANNEL ADDRESS
CHANNEL STATUS
1 2 = 1 OUTPUT COMPLETE
1 3 = 1 INPUT COMPLETE
(CHARACTER IN B IT S 0 - 7 )
1 4 = 1 CARRIER DETECT ON
1 4 = 0 CARRIER DETECT OFF
1 5 = 0 NORMAL OPERATION
1 5 = 1 POWER JU ST TURNED ON
(IGNORE B IT S 0 - 1 4 )
FIGURE 2.4
COMPUTER DATA INPUT WORD BIT DEFINITION
i n d i c a t e s i n p u t c om ple te , t h e c h a r a c t e r i s co n ta i n ed in b i t s 0 - 7 .
Once a f l a g i s s e t i t must be c l e a r e d by th e computer as d i s c u s s e d in
S e c ti o n 2 . 7 .
This acknowledges t h a t t h e in fo r m at io n was re c e iv e d
and e n a b l e s o t h e r c han ne ls t o r e q u e s t s e r v i c e .
The r i n g i n d i c a t o r and c a r r i e r d e t e c t f u n c t i o n s a r e handled as
follows.
When e i t h e r l i n e changes s t a t e (0 t o I o r I t o 0 t r a n s ­
i t i o n ) , a fla g is s e t requesting service.
B i t 14 o f t h e i n p u t word,
however, c o n t a i n s o nly t h e s t a t e o f c a r r i e r d e t e c t .
Therefore, i f
a channel r e q u e s t s s e r v i c e and b i t s 12 and 13 a r e no t s e t , th e t h i r d
f l a g s e t by r i n g i n d i c a t o r o r c a r r i e r s t a t u s must be assumed.
I f the
s t a t e o f c a r r i e r d e t e c t has changed, then t h i s f l a g was s e t by th e
c a rrie r detect signal.
I f , however, t h e c a r r i e r d e t e c t has not
changed s t a t e , then t h e o p e r a t i o n o f th e r i n g i n d i c a t o r l i n e can be
deduced.
I f d urin g any i n p u t o p e r a t i o n b i t 1 5 = 1 , then t h e MUX has had
a power f a i l u r e .
Upon r e t u r n o f t h e power, t h e power f a i l f l a g i s s e t .
This r e s e t s a l l c ha nn e ls t o a s t a r t c o n d i t i o n and th e n p u l s e s "Device
Command" t o t e l l t h e computer o f t h e new s t a t u s .
The computer must
then respond by c l e a r i n g t h e power f a i l f l a g as d i s c u s s e d under t h e
o u t p u t word (S ec ti o n 2 . 8 ) which e n a b le s t h e MUX f o r normal o p e r a t i o n .
2.1 0
SERIAL DATA CONVERSION
As d i s c u s s e d in Se c ti o n 2 . 3 any d a t a e n t e r i n g o r le a v i n g a
17
channel must be in t h e s e r i a l d a ta for mat shown in Fig ur e 2 . 2 .
The
d a t a t r a n s m i t t e d o r r e c e i v e d by t h e computer I/O i n t e r f a c e , however,
i s done in 16 p a r a l l e l b i t t r a n s f e r s as d i s c u s s e d in Se c ti o n s 2 .4 2.9.
Each channel t h e r e f o r e r e q u i r e s an o u t p u t s h i f t r e g i s t e r t h a t
can s t o r e t h e computer o u t p u t c h a r a c t e r and s h i f t t h e c h a r a c t e r out
s e r i a l l y t o t h e I/O d e v i c e .
When.entering s e r i a l d a t a a n o t h e r s h i f t r e g i s t e r i s n e c e s s a ry t o
s h i f t in and s t o r e i n p u t c h a r a c t e r s .
A f t e r c o n v e r t i n g t h e inp ut
c h a r a c t e r t o p a r a l l e l form, t h e computer can load t h e c h a r a c t e r i n t o
t h e I/O i n t e r f a c e c ar d as d i s c u s s e d in Se c tio n 2 . 9 .
The c h a r a c t e r i n p u t and o u t p u t f u n c t i o n s a r e e n a b l e d , d i s a b l e d
and i n i t i a t e d as d i s c u s s e d in S e c t i o n s 2 .4 - 2 . 9 .
2.11
PRIORITY INTERRUPT SYSTEM
Whenever a channel r e c e i v e s a c h a r a c t e r ; completes a character-
o u t p u t , o r d e t e c t s a change in c a r r i e r d e t e c t o r r i n g i n d i c a t o r ,
t h e s t a t u s i n fo r m a t io n d e f i n e d in S e c t i o n 2 .9 must be e n t e r e d i n t o
t h e computer I/O i n t e r f a c e f o r p r o c e s s i n g .
In g e n e r a l , many chann el s
w i l l be a s k i n g t o e n t e r s t a t u s s i m u l t a n e o u s l y or b e fo re o t h e r ch an nel s
have completed lo a d i n g d a t a .
To p r e v e n t t h i s problem a p r i o r i t y scheme i s i n c o r p o r a t e d
i n t o t h e l o g i c t h a t p u l s e s t h e DF l i n e p r e v e n t i n g more than one channel
from r e q u e s t i n g s e r v i c e and l o a d in g d a t a onto t h e i n p u t bus si m ul-
18
taneously.
This l o g i c works in t h e fo ll o w i n g manner:
The f i r s t
channel t o r e q u e s t s e r v i c e s e t s a f l a g p re v e n t i n g any o t h e r channel
from r e q u e s t i n g s e r v i c e .
I f two o r more c han ne ls s e t t h e i r r e q u e s t
serv ice fla g s sim ultaneously, a daisy-chained p r i o r i t y l i n e d isab les
a l l c ha nn e ls o f lower p r i o r i t y .
Then as each channel i s processed
t h e n e x t lower p r i o r i t y channel i s enabled t o r e q u e s t s e r v i c e .
Upon completion o f p r o c e s s i n g a l l c ha n n e ls with r e q u e s t . s e r v i c e f l a g s
s e t , t h e ne xt channel (o r c h a n n e ls ) d e s i r i n g s e r v i c e w i l l be enabled
and t h e p r o c e s s r e p e a t s .
2.12
SUMMARYThis conclu de s t h e s p e c i f i c a t i o n s o f t h e MUX.
The s p e c i f i c a t i o n s
fo r . t h e equipment t o be i n t e r f a c e d have been p r e s e n t e d and th e c o n t r o l
o f t h e MUX was s p e c i f i e d by g i v i n g each o f t h e 16 o u t p u t b i t s (from
t h e computer) a s p e c i a l j o b .
Next t h e encoding o f t h e s t a t u s o f
each channel o f t h e MUX was d e s c r i b e d in terms o f t h e I S ^ b i t computer
in p u t word, and o p e r a t i o n o f s e r i a l d a t a co nver sio n was d i s c u s s e d ,
along w it h t h e r e q u e s t f o r s e r v i c e o p e r a t i o n s .
The fo un d a ti o n has
now been s e t upon which t h e a c t u a l d e s i g n , d i s c u s s e d in t h e ne xt
c h a p t e r , can be implemented.
CHAPTER I II
THE HARDWARE DESIGN OF THE MULTIPLEXOR
3.1
INTRODUCTION
The s p e c i f i c a t i o n s o f t h e l a s t c h a p t e r provid e t h e in fo rm at io n
f o r implementing t h e a c t u a l hardware l o g i c d e s ig n .
Se c ti o n 3.4 -
3.5 d e s c r i b e t h e f i n a l l o g i c r e a l i z a t i o n s used t o implement th os e
specifications.
S e c ti o n 3 .6 d e s c r i b e s how t h e desi gn was t e s t e d
and debugged.
3 .2
LOGIC DIVISIONS
As shown in Fi gu re 2.1 t h e l o g i c c i r c u i t s f o r t h e M ul ti p le x o r
f a l l i n t o two c a t e g o r i e s .
common t o a l l 16 c h a n n e l s .
The f i r s t a r e t h o s e l o g i c f u n c t i o n s
These in c l u d e channel a d d r e s s encoding
and de cod ing , s i g n a l b u f f e r i n g and o t h e r common s i g n a l decoding and
encoding f u n c t i o n s .
The second group p ro v id e s t h e l o g i c f u n c t i o n s common only to
one c h a n n e l.
These in c l u d e t h e c h a r a c t e r in p u t and o u t p u t l o g i c ,
mode l a t c h e s and a s s o c i a t e d l o g i c , p r i o r i t y and r e q u e s t s e r v i c e l o g i c ,
f l a g s , and b u f f e r i n g and i n t e r f a c i n g l o g i c f o r t h e u s e r s i g n a l s .
This second group o f l o g i c i s i d e n t i c a l f o r each channel and i s r e ­
pe at e d once f o r each channel implemented.
20
3 .3
SIGNAL DEFINITIONS
All s i g n a l s w i l l be assumed p l u s t r u e ,
This means a. l o g i c
I = 2V t o 5V and a l o g i c 0 = OV t o . 8V f o r TTL l o g i c .
For EIA
l e v e l s i g n a l s a l o g i c I = 3V t o 25V and a l o g i c 0 = -3V t o -25V.
Al I s i g n a l names a r e from one t o t h r e e c h a r a c t e r s long.
If
a s i g n a l i s ground true , a bar w i l l be pla ced over t h e s ig n a l name.
As an example, a l l 16 b i t s o f t h e d a t a o u t p u t word coming from t h e
computer i n t e r f a c e board a r e ground t r u e and have t h e f o ll o w i n g
names:
0 - ( b i t z er o o f o u t p u t word; O = OV t o . 8V when a t a
logic I)
T - ( b i t I o f o u t p u t word)
2" - ( b i t 2 o f o u t p u t word)
•
15 - ( b i t 15 o f o u t p u t word)
Three o t h e r s i g n a l name examples found in Figure 3.1 a r e the
c l e a r f l a g s , mode s e t and power f a i l c l e a r s i g n a l s , d e f i n e d as
follows:
MS’
- ( " s e t mode" i f MS" = OV t o . 8V)
FC
- ( " c l e a r f l a g s " i f FC = OVt o .SM)
PFC
- ( c l e a r power f a i l f l a g i s PFC = OV t o
. 8V)
21
3 .4
COMMON LOGIC FUNCTIONS
The common l o g i c group, shown in Figure 3 . 1 , hand les th e f o l l o w i n g
operations:
(I)
The channel a d d r e s s i s decoded from t h e computer o u t ­
pu t word and one o f t h e 16 c ha nne ls i s en abled ( CSO-CSl5) f o r an
operation.
(2)
Two s i g n a l s , MS’ and FC", a r e decoded f o r use by th e
channel l o g i c f o r s e t t i n g t h e mode o f a channel and c l e a r i n g f l a g s
on t h e c h a n n e l .
f i r s t tu r n e d on.
(3)
A s i g n a l c a l l e d PR i s g e n e r a te d when power i s
This s i g n a l r e s e t s c e r t a i n p o r t i o n s o f t h e lo g i c
on each channel board t o a s t a r t i n g c o n d i t i o n .
i s f i r s t tu r n e d on, computer o u t p u t b i t s
IT,
Also when t h e power
T3, and 12" a r e for ced
t o a l o g i c I t o r e s e t f l a g s and modes in each o f t h e channel lo g i c
gro ups.
(4)
When a channel r e q u e s t s s e r v i c e from t h e computer,
d e vi ce f l a g (DF) must be puls ed t o s e t t h e f l a g on t h e computer i n t e r ­
face card.
This s i g n a l must a l s o be puls ed when power i s tu rn e d on
t o i n d i c a t e t o t h e computer t h a t t h e MUX i s ready f o r o p e r a t i o n .
(5)
When power i s f i r s t tu r n e d o n, b i t 15 o f t h e computer d a ta i n p u t
word (151) must be made a l o g i c a l I .
(6)
The channel a d d re s s must
be encoded in t h e computer i n p u t word by t h e channel t h a t i s p r e s e n t l y
r e q u e s t i n g s e r v i c e (RSI-RSl5 ) .
(7)
S i g n a l s (0T-15I) going to th e
computer i n t e r f a c e must be b u f f e r e d with c a b le l i n e d r i v e s .
The implementation o f t h e s e seven f u n c t i o n s can be seen in
Figu re 3 . 1 .
On t h e l e f t hand s i d e o f t h e drawing a r e t h e outp u t
l i n e d r i v e r s and i n p u t l i n e r e c e i v e r s on t h e I/O i n t e r f a c e card
FIGURE 3.1
COMMON LOGIC FUNCTIONS
23
l o c a t e d in. t h e computer.
The c e n t e r s e c t i o n shows t h e common l o g i c
f u n c t i o n s o f t h e m u l t i p l e x o r . . The r i g h t hand s i d e o f t h e drawing
i l l u s t r a t e s t h e bus sin g t o each o f t h e s i x t e e n channel l o g i c groups.
Next i s a d e t a i l e d d e s c r i p t i o n o f t h e o p e r a t i o n o f t h e common l o g i c
us in g F ig ur e 3.1 as a r e f e r e n c e .
The o u t p u t b i t s 8 - 1 1 from t h e computer ( s i g n a l s Sf9 9,
TT)
TO9
a r e decoded in IC51 and one o f t h e 16 channel s e l e c t l i n e s
(CSXX) i s e n a b le d .
This IC (SN74154) e n a b l e s CSO i f a b in a r y a d d re s s
o f 0000 i s e n t e r e d on l i n e s
TT9 TO9 F9 and
b i n a r y a d d r e s s o f 0001 i s e n t e r e d .
8.
CSl i s enabled i f a
This c o n t i n u e s w it h each CSXX
l i n e s e l e c t e d in t u r n when t h e a p p r o p r i a t e o u t p u t a d d r e s s from b i t s
TT9 TO9 F 9 and
8" a r e e n t e r e d .
The o p e r a t i o n o f t h e c l e a r f l a g l i n e (FCf) oc cu rs when th e
de v ic e command (CD) i s a t a l o g i c a l I (p uls ed by a STC computer
i n s t r u c t i o n ) and o u t p u t b i t 15 ( s i g n a l 15) i s a t a l o g i c 0.
Then
g a t e 38 goes low g i v i n g a high l e v e l o u t o f g a te 44 which a c t i v a t e s
FC" from l i n e d r i v e r 50 (SN7416).
A l s o , FC" i s a c t i v a t e d when th e
p o w e r - f a i l f l i p - f l o p i s being s e t ( s i g n a l PFS) by i n v e r t e r 40.
This
ca us e s t h e f l a g s t o be r e s e t when power i s i n i t i a l l y a p p l i e d .
In a s i m i l a r manner t h e mode s e t s ig n a l
(Ms)
i s a c t i v a t e d when
g a t e 37 goes low because o u t p u t b i t 15 (TE) i s a t a l o g i c a l I 9
o u t p u t b i t 0 i s a t a 0 (0) and t h e d e v i c e command s i g n a l (DC) i s
activated.
i
This ca us e s a high l e v e l from g a t e 43 which a c t i v a t e s
24
MS from l i n e d r i v e r s 49.
Again t h e s e t t i n g o f t h e p o w e r - f a i l f l a g
(PFS) a l s o a c t i v a t e s t h e MS’ s i g n a l t o r e s e t t h e mode f l i p - f l o p s
t o an i n i t i a l s t a r t i n g c o n d i t i o n when power i s tu r n e d on.
The c i r c u i t t o g e n e r a t e PFS o p e r a t e s as f o l l o w s :
When power
i s f i r s t t u r n e d o n, r e s i s t o r Rl and c a p a c i t o r Cl p ro vid e a .1 second,
d e l a y b e fo re c ha r g in g Cl s u f f i c i e n t l y t o t u r n t r a n s i s t o r Ql "on"
through t h e 3 v o l t z e n e r diode CR2.
CRl and. R3 a r e used to d i s ­
charge Cl r a p i d l y when t h e power i s tu r n e d o f f .
Hex i n v e r t e r 40
p r o v id e s c o r r e c t p o l a r i t y and s q u a r in g o f t h e o u t p u t from t h e c o l l e c t o r
o f Ql and s e t s t h e p o w e r - f a i l FF.
When s e t , t h e o u t p u t o f t h e p o w e r - f a i l FF i s used t o f o r c e
14", T3 and TT t o a l o g i c a l I through l i n e d r i v e r s 4 6, 47 and 48
which a r e "wire ored" w it h t h e t h r e e o u t p u t s on t h e computer i n t e r f a c e
card.
These t h r e e l i n e s must be a t a l o g i c a l I t o c l e a r t h e t h r e e
f l a g s on each channel when t h e FCT l i n e i s a c t i v a t e d . ; Also t h i s
f o r c e s t h e mode o f each channel i n t o " i n p u t - o n " , " ec ho-o n" , " o u t ­
p u t - o f f " , and d a t a t e rm in a l ready f a l s e .
The PR l i n e i s enabled by
l i n e d r i v e r 45 which r e s e t s c e r t a i n p o r t i o n s o f t h e channel l o g i c t o
a s ta r tin g condition.
B i t 15 ( s i g n a l 151) o f t h e computer i n p u t word i s a l s o s e t to
a l o g i c a l I through d r i v e r 58 t o i n d i c a t e t h a t power has j u s t been
applied.
Gate 39 ca us e s one s h o t 52 (SN74121) t o t r i g g e r (one
microsecond p u l s e ) a t t h e e n d . o f t h e .1 sec power up d e l a y .
This s e t s
25
t h e f l a g on t h e I/O computer c a r d which s i g n a l s t o t h e computer
t o load t h e d a t a i n p u t word f o r p r o c e s s i n g .
The p o w e r - f a i l FF can then be c l e a r e d by s ig n a l RFC, gener ate d
by g a te 36 when s i g n a l s DC9 15" and 0" a r e a l l a t a l o g i c a l I .
A f te r
t h e p o w e r - f a i l FF has been c l e a r e d t h e MUX i s re ad y f o r o p e r a t i o n .
When t h e MUX i s re ad y t o e n t e r d a t a i n t o t h e computer, th e
HT s i g n a l
i s a c t i v a t e d by t h e channel d e s i r i n g s e r v i c e .
This t r i g g e r s
one s h o t 52 which a c t i v a t e s DF and s e t s t h e f l a g on t h e computer I/O
card.
The channel r e q u e s t i n g s e r v i c e a l s o a c t i v a t e s an RSXX s i g n a l .
RSl5 i s a c t i v a t e d by channel 16, RSl4 by channel 15, e t c . ending with
channel 2 because channel I d o e s n ' t a c t i v a t e a l i n e ;
Gates 53, 54,
55 and 56 g e n e r a t e t h e a p p r o p r i a t e b i n a r y a d d r e s s depending on which
RSXX l i n e i s a c t i v a t e d .
By d e f a u l t i f no RSXX l i n e i s a c t i v a t e d
b i n a r y a d d r e s s 0 (channel I ) i s g e n e r a t e d .
The channel l o g i c e n t e r s
t h e a p p r o p r i a t e d a t a f o r i n p u t b i t s 0 - 7 , and 12-14 ( s i g n a l s OT -
TI,
121 - 141).
When t h e computer lo a d s t h e in p u t d a t a t h e channel
a d d r e s s , c h a r a c t e r and f l a g s a r e e n t e r e d by l i n e d r i v e r s 57 through
73 which b u f f e r t h e i n p u t s i g n a l s and d r i v e t h e c a b l e going to th e
computer I/O i n t e r f a c e board.
3.5
CHANNEL LOGIC
The channel l o g i c (Fig ure 3.2 ) c o n t a i n s a l l l o g i c needed to
o p e r a t e one. s p e c i f i c ch an n e l.
This l o g i c uses t h e s i g n a l s ge ner at e d
26
by t h e computer I/O i n t e r f a c e and t h e common l o g i c group as p r e ­
viously discussed.
I t a l s o g e n e r a t e s t h e La, RSXX and d a t a in put
b i t s 0-7 and 12-14.
The channel l o g i c group must handle t h e f o ll o w i n g t a s k s :
(I)
Four mode f l i p - f l o p s loaded by t h e MS"and CSXX s i g n a l s determine
t h e "mode" o r s t a t u s o f each c h a n n e l.
(2)
All t h e u s e r i n p u t and
o u t p u t s i g n a l s a r e b u f f e r e d wit h c a b l e l i n e r e c e i v e r s and c ab le
line drivers.
(3)
The i n p u t d a t a i s loaded i n t o an i n p u t b u f f e r
r e g i s t e r with s e r i a l - t o - p a r a l I e l 5 b i t - c o n v e r s i o n l o g i c .
(4)
The
o u t p u t d a t a i s t r a n s m i t t e d wit h p a r a l l e l - t o - s e r i a l , b i t - c o n v e r s i o n
logic.
(5)
When any o p e r a t i o n i s completed ( c h a r a c t e r o u t p u t ,
c h a r a c t e r i n p u t , o r a change in r i n g i n d i c a t o r o r c a r r i e r d e t e c t ) ,
the appropriate s ta tu s fla g s are s e t.
(6)
The s t a t u s f l a g s a re
c l e a r e d by t h e FC and CSXX s i g n a l s a f t e r s e r v i c i n g .
(7)
The UO
and RSXX s i g n a l s a r e a c t i v a t e d when any f l a g g e t s s e t and no ch annels
of higher p r i o r i t y are requesting s e rv ic e .
(8)
When a channel
a c t i v a t e s t h e ,10" and RSXX s i g n a l s , d a t a b i t s 0-7 and 12-14 ( s i g n a l s
UT-TT, 121-141) a r e loaded onto t h e d a t a in p u t bus.
R efer to
Figure 3.2 f o r t h e f o ll o w i n g d e t a i l e d c i r c u i t s d e s c r i p t i o n .
The channel "mode" i s s t o r e d in f l i p f l o p s 9-12 (SN7475).
When t h e CSXX and MT s i g n a l s a r e t r u e , g a te 3 goes high and loads TZ
(by i n v e r t e r 7) i n t o f l i p - f l o p 12, Tl" (by i n v e r t e r 6) i n t o f l i p f l o p 11 and TT (by i n v e r t e r 5) i n t o f l i p - f l o p 10.
F l i p - f l o p 9. i s
DTR TTL
Cl TTL
Rl TTL
FIGURE 3.2
CHANNEL
LOGIC
28
s e t f a l s e (Q o u t p u t ground t r u e ) i f 13" and
4 ), otherwise the output i s s e t t r u e .
Tz
a r e both t r u e (by ga te
F l i p - f l o p 12 e n a b l e s or d i s ­
a b l e s o u t p u t , f l i p - f l o p 11 e n a b le s and d i s a b l e s e cho , f l i p - f l o p 9
e n a b l e s and t h e u s e r s i g n a l "data te rm in a l r e a d y " , and f l i p - f l o p 10
e n a b l e s and d i s a b l e s i n p u t .
The mode f l i p - f l o p s a r e a l s o loaded when PR and Ms" a r e t r u e .
This lo a d s t h e i n i t i a l s t a r t i n g mode as d i s c u s s e d in S e c ti o n 3.4
when power i s f i r s t tu r n e d on.
User i n p u t d a t a i s e n t e r e d on e i t h e r t h e DI EIA o r DT TTL l i n e
depending on s i g n a l l e v e l s .
IC61 (SN75154) c o n v e r t s EIA l e v e l s to
TTL and b u f f e r s 62-64 wire "or" t i e t h e EIA in p u t s t o t h e TTL i n p u t s .
R e s i s t o r s R7-R12 a r e c a b l e l i n e impedance matching and b i a s networks.
Diodes CRl t o CR3 p ro vid e i n p u t g a t e i s o l a t i o n by p r e v e n t i n g i n p u t
v ol ta ge s, g r e a t e r than 5 v o l t s on t h e g a t e s i d e o f t h e d i o d e s .
The i n p u t d a t a i s then s e n t
( a l l f l i p - f l o p s a r e SN7474 e xc e pt
through i n v e r t e r 25.
t o g a t e 35, Don f l i p - f l o p
9 , 10, 11 and
29
12) and g a te 23
I f echo i s enab le d t h e d a t a a l s o c o n ti n u e s
thr oug h g a t e 24 and o u t b u f f e r 27 as DO TTL and o u t IC26 (SN75150)
as DO EIA.
For t h i s c a s e d a t a in has been "echoed" back o u t on th e
data output l i n e .
I f i n p u t i s enab le d t h e i n p u t FF s e t s with t h e s t a r t pu ls e from
t h e d a t a i n p u t word.
I n i t i a l l y t h e 8 b i t s h i f t r e g i s t e r (SN74164) 71
i s c l e a r e d along w it h f l i p - f l o p s 31 and 32.
F l i p - f l o p 29, however.
29
has been p r e s e t t o a one.
The o u t p u t o f g a te 36 goes ground t r u e
e n a b l i n g t h e d i v i d e r IC30 (SN7492).
This IC d i v i d e s (by 12) the
o s c i l l a t o r o u t p u t from i n v e r t e r 22 which i s e n t e r e d i n t o A i f B i s
ground t r u e .
The o u t p u t (C) i s used t o s h i f t in t h e d a t a b i t s through
f l i p - f l o p 29 and s h i f t r e g i s t e r 71.
When t h e one o r i g i n a l l y s e t in f l i p - f l o p 29, and t h e s t a r t p u l s e
re a ch f l i p - f l o p 31 and t h e l a s t s t a g e o f IC71 r e s p e c t i v e l y , g a te 72
goes t r u e s e t t i n g t h e " c h a r a c t e r r e c e i v e d " f l a g f l i p - f l o p 60.
The
Q" o u t p u t o f f l i p - f l o p 60 p r e v e n t s t h e c h a r a c t e r which i s p r e s e n t l y
c o n ta i n e d in f l i p - f l o p 29 and t h e lower 7 s t a g e s o f IC71 from s h i f t i n g
by d i s a b l i n g t h e c l o c k d r i v e through g a t e 33.
The f l i p - f l o p s 31 and
32 a r e clocked once more however, and t h i s s h i f t s t h e o r i g i n a l one
o f f l i p - f l o p 29 i n t o f l i p - f l o p 32 which r e s e t s t h e i n p u t FF from o u t ­
p u t 32Q".
A f t e r t h e " c h a r a c t e r r e c e i v e d " f l i p - f l o p (60) i s c l e a r e d ,
f l i p - f l o p s 31, 32 and IC71 a r e c l e a r e d by g a te 34.
F l i p - f l o p 29 i s
p r e s e t t o an i n i t i a l one s t a t e and t h e l o g i c i s pre pa re d f o r t h e n e x t
character.
By c l e a r i n g t h e i n p u t mode f l i p - f l o p 10 t h e i n p u t FF
cann ot be s e t and hence no i n p u t c h a r a c t e r s can be e n t e r e d and in p u t
disabled.
Also t h e PR s i g n a l , when t r u e , c l e a r s t h e i n p u t FF through
g a te 8 th u s r e s e t t i n g t h e i n p u t c i r c u i t r y i n i t i a l l y .
C h a r a c t e r s a r e o u t p u t by f i r s t s e t t i n g t h e p r o p e r "mode" t o
" o ut pu t on" and "echo o f f " .
p u t o f g a t e 2 goes high .
Then when CSXX and FC a r e t r u e th e o u t ­
Now i f s ig n a l TH* i s a t a o ne , g a te 67 goes
30
high p u l s i n g g a t e 13 low s e t t i n g t h e o u t p u t FF5 l o a d i n g o u tp u t
signals
O' t o 7 i n t o t h e d a t a o u t p u t r e g i s t e r 16 (IC SN74165) and
s e t t i n g t h e s t a r t p u l s e i n t o f l i p - f l o p 18.
The d i v i d e by 12 c i r c u i t
17 (SN7492) i s now en abled and c l o c k s t h e c h a r a c t e r o u t through g a t e s
24, 26 and 27.
Counter 19 ( a l s o SN7492) r e s e t s t h e o u t p u t FF through
g a t e 20 a f t e r c o u n ti n g e i t h e r 10 o r 11 c l o c k p u l s e s t h u s t e r m i n a t i n g
the p a r a l l e l - t o - s e r i a l conversion.
A jumper o p ti o n ( J l ) deter mine s
whether a 10 o r 11 b i t code i s g e n e r a t e d .
As t h e o u t p u t FF c l e a r s
t h e " o u tp u t complete" f l a g f l i p - f l o p 59 i s s e t i n d i c a t i n g t h e c h a r a c ­
t e r has been t r a n s m i t t e d .
The o u t p u t FF and f l i p - f l o p 18 a r e c l e a r e d
when power i s i n i t i a l l y t u rn e d on by PR through g a te 8 , a l s o .
This
r e s e ts the output logic to the i n i t i a l s ta r tin g condition.
When e i t h e r t h e r i n g i n d i c a t o r (RI) o r c a r r i e r d e t e c t (CD)
change s t a t e , one o f t h e f l a g f l i p - f l o p s 57 o r 58 s e t s through g a t e s
64 o r 65.
When any o f t h e f l i p - f l o p s 57-69 a r e s e t , channel in for ma ti on
i s ready t o be e n t e r e d i n t o t h e computer.
The in fo r m a t io n can only be
e n t e r e d i f no o t h e r ch an ne ls a r e p r e s e n t l y lo a di ng t h e i r i n f o r m a t i o n .
When any f l i p - f l o p 57-60 g e t s s e t , g a t e 55 goes t r u e .
Then i f LO
i s no t t r u e (no o t h e r channel r e q u e s t i n g s e r v i c e ) t h e r e q u e s t s e r v i c e
FF i s s e t thro ugh g a t e 54.
This cau s e s HT t o go t r u e p r e v e n ti n g any
o t h e r c h a n n e ls from r e q u e s t i n g s e r v i c e .
I f no o t h e r channel o f hig h e r
31
p r i o r i t y a l s o wants s e r v i c e , PH i s t r u e and a c t i v a t e s RSXX through
g a t e 51 and i n v e r t e r 49.
Gate 51 a l s o lo ad s t h e s t a t u s o f the
" c h a r a c t e r r e c e i v e d f l i p - f l o p " , " o utp ut complete FF" and t h e s t a t u s
o f c a r r i e r d e t e c t thr ou gh g a t e s 38, 39 and 40 onto t h e d a t a in p u t
bus b i t s 141, 131 and 121.
I f the "character received" f li p - f l o p
i s s e t , th e c h a r a c t e r i s loaded onto bus b i t s OT-TT through g a t e s 27
and 41-48.
When t h e r e q u e s t s e r v i c e FF i s s e t PL goes f a l s e through ga te
50.
PL becomes PH o f t h e n e x t lower channel and p r e v e n t s any c han ne ls
o f lower p r i o r i t y from r e q u e s t i n g s e r v i c e u n t i l t h e p r e s e n t channel
has been s e r v i c e d and a l l f l a g f l i p - f l o p s (57-60) c l e a r e d .
F l i p - f l o p s 57-60 a r e c l e a r e d by t h e s i g n a l s CSXX, FC", and th e
a p p r o p r i a t e o u t p u t b i t (12, TT or T4).
TT c l e a r s "change in RI or
CD s t a t u s f l i p - f l o p s " ( 5 7 - 5 8 ) , TT c l e a r s t h e " c h a r a c t e r r e c e iv e d
f l i p - f l o p " (60) and 12 c l e a r s t h e " o u tp u t complete FF" (5 9 ) .
Once
t h e s e f l i p - f l o p s a r e c l e a r e d , g a te 55 goes f a l s e c l e a r i n g t h e r e q u e s t
s e r v i c e f l i p - f l o p and e n a b l i n g t h e PL s i g n a l through g a t e 50.
3 .6
TESTING OF THE MULTIPLEXOR
The i n i t i a l t e s t i n g o f t h e l o g i c was done by breadboarding
small subgroups.
These groups were then t e s t e d by e n t e r i n g i n p u t
d a t a w it h sw it ch e s and m oni to ri ng o u t p u t s on an o s c i l l o s c o p e .
The
p a r a l l e l - t o - s e r i a l and s e r i a l - t o - p a r a l l e l c o n v e r t e r s were t e s t e d in
32
t h i s way.
Various o s c i l l a t o r s were b u i l t up and t e s t e d a l s o f o r use
with t h e s e b i t c o n v e r t e r s .
Temperature t e s t s were run t o check th e
^ s t a b i l i t y of the o s c i l l a t o r s .
Next t h e p r i o r i t y l o g i c was breadboarded and s i m u l a t i o n i n t e r ­
r u p t s were e n t e r e d w it h s w i t c h e s .
A g a in , t h e o u t p u t s were monitored
wit h an o s c i l l o s c o p e .
The l a s t c i r c u i t s t o be breadboarded and t e s t e d were t h e powerf a i l FF s e t (PFS) g e n e r a t o r and t h e f l a g c l e a r and mode s e t common
logic c i r c u i t s .
The e n t i r e MUX was ne ver t o t a l l y t e s t e d u n t i l t h e p r o t o t y p e was
constructed.
This was b u i l t with p r i n t e d c i r c u i t c a r d s and i n t e r ­
connected w ith a hand wired back pla ne .
The l o g i c was p a r t i t i o n e d q u i t e
d i f f e r e n t l y on t h e o r i g i n a l p r o t o t y p e , however.
Those f u n c t i o n s shown
in F ig ur e 3.2 were a c t u a l l y on t h r e e d i f f e r e n t p r i n t e d c i r c u i t c a r d s .
One c ar d c o n t a i n e d t h e s e r i a l - t o - p a r a l l e l and p a r a l l e l - t o - s e r i a l b i t c o n v e r t e r s and t h e o s c i l l a t o r .
Another board c o n ta i n e d t h e f l a g s ,
mode, i n t e r f a c e and bus si ng l o g i c .
S t i l l a t h i r d board c onta in ed
a l l t h e p r i o r i t y l o g i c common t o 8 c h a n n e l s .
With t h e l o g i c p a r t i t i o n e d in t h i s manner only e i g h t channels
co uld be implemented in one ca rd f i l e .
P r o v is io n s were made to con nec t
t o a n o t h e r ca rd f i l e , however, t o implement th e o t h e r 8 c han ne ls .
The 8-channel MUX p r o t o t y p e was then connected t o t h e computer
and two simple programs were w r i t t e n t o . t e s t th e b a s i c o p e r a t i o n o f
33
t h e MUX.
A f t e r g e t t i n g t h e i n i t i a l bugs o u t o f t h e system ( c a b l e ,
backplane and p r i n t e d c i r c u i t w ir in g e r r o r s ) t h e system was ready, to
be t e s t e d with ti m e ^ s h a re B asi c.
These d r i v e r s were w r i t t e n acc ord in g
t o t h e s p e c i f i c a t i o n s o f Chapter 2 and s e v e r a l months were r e q u i r e d
t o f i n i s h debugging t h e system.
Next a second 8-channel. MUX was c o n s t r u c t e d having a l l the
c o r r e c t i o n s o f t h e f i r s t MUX and inc lud ed a wire-wrap backplane.
L a t e r , t h e 16-channel MUX was b u i l t and inc lud ed t h e combination o f
a l l channel l o g i c on one p r i n t e d c i r c u i t c a r d .
Included w ith t h i s was
some l o g i c r e d u c t i o n and t h e f i n a l r e s u l t s a r e shown in Figure 3 .2 .
The common l o g i c could a l s o be s i m p l i f i e d and i s shown in Figure 3 . 1 .
3.7
SUMMARY
This concludes t h e d e s c r i p t i o n o f t h e o p e r a t i o n o f t h e MUX.
F i r s t , s i g n a l names, l e v e l s , c u r r e n t s and t r a n s i t i o n tim e s were
defined.
Next t h e o p e r a t i o n o f t h e common and channel l o g i c was
d e s c r i b e d and f i n a l l y t e s t i n g p ro c e ed u re s were p r e s e n t e d .
CHAPTER IV
THE MECHANICAL DESIGN OF THE MUX
4.1
INTRODUCTION
This c h a p t e r d i s c u s s e s t h e p h y s ic a l and mechanical c o n s t r u c t i o n
o f t h e MUX.
Various c a r d c a g e s , p r i n t e d c i r c u i t c a r d s i z e s , power
s u p p l i e s , i n t e r c o n n e c t i n g c a b l e s and c a b l e c o n n e c t o r s were t r i e d
b e fo re t h e f i n a l c o n f i g u r a t i o n was deci de d upon.
This c h a p t e r shows
t h e e v o l u t i o n , problems en co un te red and c o n s i d e r a t i o n s made during
construction.
4. 2
CARD CAGES
The f i r s t problem en co un te red was t r y i n g t o f i n d a s u i t a b l e
housing o r c a b i n e t f o r t h e l o g i c .
P r i n t e d c i r c u i t c a r d s were decided
upon t o i n t e r c o n n e c t t h e l o g i c and hence a c a b i n e t c a p a b le o f housing
many (19 in t h e f i n a l c o n f i g u r a t i o n ) c a r d s was d e s i r e d .
C ab in et s and c a r d cages come in s t a n d a r d h e i g h t s and widths
f o r mounting in r e l a y r a c k s and o t h e r e n c l o s u r e s .
The most common
width i s 19" which was a c c e p t a b l e f o r t h i s a p p l i c a t i o n .
o f 19" an i n s i d e width o f 17" i s o b t a i n e d .
With a width
P r i n t e d c i r c u i t c a r d s can .
be mounted 1/2" a p a r t and hence a pp ro x im a te ly 32 c a r d s can be i n s t a l l e d
in one ca rd c ag e .
This i s more than enough space to house t h e MUX
l o g i c which r e q u i r e s o n ly T6 channel l o g i c b o a rd s , two common l o g i c
35
boards and one plug board ( f o r MUX c o n nec tio n t o t h e computer).
The f i r s t ca rd cage selected! was a commercial v e r s i o n .
The
p r o t o t y p e was c o n s t r u c t e d usi ng t h i s c a r d cage but e x t e n s i v e modi­
f i c a t i o n was r e q u i r e d because t h e c a r d gu id e s were q u i t e s h o r t and
t h e maximum c a r d width (w it h o u t m o d i f i c a t i o n ) was 4 1 / 2 " .
Because
o f t h e u n s a t i s f a c t o r y r e s u l t s o b ta in e d with t h e commercial u n i t , a
custom c a r d cage was designe d and c o n s t r u c t e d usin g 1/8" s h e e t
aluminum.
This r e s u l t e d in a much more s a t i s f a c t o r y c a b i n e t and i s
shown in Fig ur e 4 . 1 .
4 .3
PRINTED CIRCUIT CARDS
At t h e p r e s e n t t h e r e a r e two common ways o f i n t e r c o n n e c t i n g
integrated c ir c u its .
The f i r s t and most r e l i a b l e i s with t h e use o f
printed c ir c u it cards.
The second i s with a wire-wrap t e c h n i q u e .
The wire-wrap t e c h n i q u e i s somewhat c h ea p e r f o r low volume work and i s
e a s i e s t t o c o r r e c t i f an i n t e r c o n n e c t i o n e r r o r i s made.. However, i t
i s slower and more prone t o e r r o r s , once a p r i n t e d c i r c u i t card i s
c o rre c tly la id out.
Other problems in c l u d e a l a r g e board spacing
width and s p e c i a l t o o l s and IC s o c k e t s r e q u i r e d f o r c o n s t r u c t i o n .
T h e r e f o r e , p r i n t e d c i r c u i t c a r d s were used f o r mounting th e
logic.
Double s id ed c i r c u i t s on 1/8" epoxy board were used with
plate-through holes.
All boards a r e i n t e r c o n n e c t e d w ith 44 pin edge
c o n n e c to r s t h a t plug onto gold p l a t e d f i n g e r s f o r high wear r e s i s t a n c e .
W
Ox
'connector
FIGURE
4.1
MUX
PHYSICAL
LAYOUT
37
These boards were l a i d o u t on mylar w ith bla ck t a p e , twice a c t u a l
size.
These were then reduced on n e g a t i v e s t o a c t u a l s i z e f o r use
in f a b r i c a t i o n o f t h e p r i n t e d c i r c u i t c a r d s .
Fig ur e 4.1 i l l u s t r a t e s
t h e p r i n t e d c i r c u i t c a r d sizes, and l o c a t i o n s .
4 .4
CABLES, CONNECTORS AND BACKPLANE WIRING
J u s t as t h e r e a r e v a r i o u s t e c h n i q u e s f o r i n t e r c o n n e c t i n g
c i r c u i t s on one b o a r d , t h e r e a r e a l s o v a r i o u s t e c h n i q u e s f o r i n t e r -
,
c o n n e c ti n g p r i n t e d c i r c u i t c a r d s and c i r c u i t modules.
The most c o n v e n ie n t way t o co n n ec t t o a p r i n t e d c i r c u i t card
i s wit h t h e use o f an edge c o n n e c t o r .
Therefore, the prin ted c i r c u i t
c ar d I/O i n t e r f a c e in t h e computer i s connected t o t h e plug ca rd in
t h e MUX thro ugh a c a b l e co nnected t o two edge c o n n e c t o r s .
The c a b le
i s a 68 c o n d u c t o r , t w i s t e d p a i r , low v o l t a g e c a b l e twelv e f e e t long.
Twisted p a i r s were s e l e c t e d with one l i n e c a r r y i n g t h e s ig n a l and th e
o t h e r ground.
This minimizes c r o s s t a l k and n o i s e problems and p ro v id e s
enough c ond uc to r s f o r t h e r e t u r n ground c u r r e n t s .
The 16 u s e r s and t h e mon itor t e l e t y p e a r e s i m i l a r l y i n t e r f a c e d
us in g edge c o n n e c to r s but because l e s s s i g n a l s a r e i n v o l v e d , s h o r t e r
edge c o n n e c to r s were s e l e c t e d f o r t h i s a p p l i c a t i o n .
A ls o, because
o f t h e r e l a t i v e l y slow s ig n a l s w i tc h i n g speeds t w i s t e d p a i r c a b le i s
not required.
There a r e t h r e e common ways t o i n t e r c o n n e c t back pla ne c o n n e c t o r s .
38
The f i r s t i s wire s o l d e r e d t o pin t a b s , t h e second i s wire wrap and
t h e t h i r d i s with a mother board p r i n t e d c i r c u i t c a r d .
The p r o t o t y p e
MUX was i n t e r c o n n e c t e d u s in g t h e f i r s t te c h n i q u e o f s o l d e r i n g wire s
between t h e a p p r o p r i a t e c o n n e c to r t a b s .
The second MUX was b u i l t
usi ng t h e wire wrap t e c h n i q u e but was n o t used ag ain because i t was
slow and r e q u i r e d s p e c i a l t o o l s .
The n e x t t h r e e 16-channel MUX
u n i t s were b u i l t us in g t h e f i r s t te c h n i q u e o f s o l d e r e d w i r e , but th e
b us si ng had been s i m p l i f i e d enough t o a ll ow t h e use o f bare bus wire
i n s u l a t e d with t e f l o n t u b i n g .
4 .5
POWER SUPPLY
The MUX r e q u i r e s t h r e e r e g u l a t e d power supply v o l t a g e s o f +5V
a t 4 amps, ( f o r t h e l o g i c ) +12V a t I amp and -12V a t I amp ( f o r th e
EIA i n t e r f a c e ! C s ) .
Ripp le and r e g u l a t i o n must be l e s s than 5% on
t h e s e t h r e e power sup ply v o l t a g e s f o r e r r o r f r e e o p e r a t i o n .
A
commercial power sup ply module meeting t h e s e v o l t a g e , c u r r e n t and
r i p p l e s p e c i f i c a t i o n s was s e l e c t e d f o r t h i s a p p l i c a t i o n .
This module was mounted on a 3 1/2" x 19" f r o n t panel and an
o n - o f f s w i t c h , i n d i c a t o r lamp and AC p r o t e c t i o n f u s e i n s t a l l e d .
The MUX was then connected t o t h e power supply with f o u r 16 gage
c on du ct or s connected t o a te rm in a l s t r i p mounted on t h e power supply.
The e n t i r e MUX and power supp ly u n i t t o g e t h e r occupy a t o t a l
o f 10 1/2" o f f r o n t panel space in a s t a n d a r d 19" c a b i n e t and r e -
39
q u i r e s a maximum depth o f 12".
4 .6
SUMMARY
This c oncl udes t h e mechanical d e s c r i p t i o n o f t h e MUX.
F irst,
t h e c a b i n e t and p r i n t e d c i r c u i t c ar d a ss e m b li e s were d e s c r i b e d .
Then, p r i n t e d c i r c u i t and module i n t e r c o n n e c t i o n systems were d i s ­
c u s s e d , and f i n a l l y power supply s e l e c t i o n and mounting was p r e s e n t e d .
CHAPTER V
FINAL EVALUATION, PERFORMANCE AND CONCLUSION
5.1
INTRODUCTION
The MUX has now been t h o ro u g h l y t e s t e d a f t e r b u i l d i n g and
o p e r a t i n g two p r o t o t y p e s and t h r e e p ro d u c ti o n models.
The system
o p e r a t i o n and performance can now be e v a l u a t e d by d i s c u s s i n g the
f o l l o w i n g it e m s :
e a s e o f c o n s t r u c t i o n , t e s t i n g and t r o u b l e - s h o o t i n g ,
r e l i a b i l i t y , r e l a t i v e c o s t and performance (as r e l a t e d t o t h e s p e c i ­
f i c a t i o n s and g o a ls s e t f o r t h in C hapt ers I and 2 ) .
5 .2
CONSTRUCTION, TESTING AND TROUBLE-SHOOTING
The e a s e with which a p ro duc t can be c o n s t r u c t e d and t e s t e d
d i r e c t l y a f f e c t s t h e c o s t o f p ro d u c ti o n and ma intenance.
The p r e s e n t
MUX i s c o n s t r u c t e d with 18 p r i n t e d c i r c u i t c ar d s which a r e q u i t e
e as y and f a s t t o b u i l d .
The channel l o g i c boa rd, which i s th e most
complex, c o n t a i n s o nly 26 i n t e g r a t e d c i r c u i t s , 8 c a p a c i t o r s , 3 diodes
and 18 r e s i s t o r s .
I t can be b u i l t in l e s s than two hours and computer
checked in 5 m in u te s .
The o t h e r two common l o g i c boards a r e even
f a s t e r and e a s i e r t o b u i l d and check.
Since a l l t h e e l e c t r o n i c s a r e c o n ta i n e d on p r i n t e d c i r c u i t c a r d s ,
t r o u b l e - s h o o t i n g a MUX in t h e f i e l d c o n s i s t s o f board swapping u n t i l
t h e problem i s s o lv e d .
Also a computer program d i a g n o s t i c can be
41
used which t e s t s t h e o p e r a t i o n s o f t h e computer i n t e r f a c e board,
common l o g i c , and each i n d i v i d u a l channel board t o help determine
which p r i n t e d c i r c u i t c a r d i s m a l f u n c t i o n i n g .
The two time consuming c o n s t r u c t i o n s e c t i o n s o f t h e MUX a t
p r e s e n t a r e t h e hand w i r i n g and checkout o f t h e backplane and i n t e r ­
c o n n e c ti n g c a b l e t o t h e computer.
Both a r e slow and prone to m i s t a k e s ,
though once completed and checke d, a r e q u i t e r e l i a b l e .
Below i s . a
l i s t o f t y p i c a l times t o c o n s t r u c t and t e s t v a r i o u s p a r t s o f th e
MUX:
Channel Board C o n s t r u c t i o n and Te s t
(one c han ne l)
2 hours
Common Logic Board C o n s t r u c t i o n and Te st
4 hours
Card Cage Mechanical Assembly
2 hours
Card Cage Backplane Wiring
16 hours
Computer I n t e r f a c e Cable
8 hours
Total C o n s t r u c t i o n Time
62 hours
Final T e s t i n g , Burn-in and Check-out
Total
5.3.
8 hours
-
70 hours
COST
The c o s t o f t h e 16-channel MUX i s about h a l f t h e c o s t o f th e
two i n t e r f a c i n g methods d e s c r i b e d in c h a p t e r one.
This i n c l u d e s t h e
c o s t o f t h e computer i n t e r f a c e board and power supply r e q u i r e d by t h e
MUX.
A ls o , only as many c hann el s as d e s i r e d , need be implemented
42
in t h e MUX.
I f an e i g h t channel system i s needed only e i g h t channel
l o g i c boards need t o . b e i n s t a l l e d th u s c u t t i n g t h e c o s t from th e
16-channel system s u b s t a n t i a l l y .
By u s in g t h i s MUX, from 5 t o 16
c ha nn e ls can be implemented more in e x p e n s i v e l y than t h e a l t e r n a t e
i n t e r f a c i n g s o l u t i o n s d i s c u s s e d in c h a p t e r one.
A d d i t i o n a l l y only one
I/O s l o t in t h e computer i s u s e d , t h u s l e a v i n g t h e r e s t f r e e f o r o t h e r
interfacing tasks.
5 .4
RELIABILITY AND PERFORMANCE
The MUX has proven t o be a v e ry r e l i a b l e p ie c e o f equipment.
There has n o t been one f a i l u r e in a MUX once i t has been pla ced in
o p e r a t i o n and t h e o r i g i n a l p r o t o t y p e ran f o r one y e a r .
I t was then
r e p l a c e d by a 16-channel MUX, and ag ain t h e r e has been no down-time
f o r t h i s MUX e i t h e r , d u ri n g i t s f i r s t one y e a r p e r io d o f o p e r a t i o n .
With o nly two u n i t s in o p e r a t i o n , however, t r u e r e l i a b i l i t y i s not
ve ry a c c u r a t e l y d e te r m in e d.
The r e l i a b i l i t y o f t h e MUX i s b a s i c a l l y
determined by t h e r e l i a b i l i t y o f t h e i n t e g r a t e d c i r c u i t s .
I t has been
t h e e x p e r i e n c e o f t h e a u t h o r t h a t t y p i c a l l y no t more tha n one IC in
500 w i l l f a i l in a 12 month pe ri o d a f t e r i n i t i a l b u r n - i n .
Between 1% and 2% f a i l u r e o f I C s d urin g i n i t i a l t e s t i n g and
b u r n - i n ( f i r s t week) has been e n c o u n te re d .
This i s t y p i c a l o f semi­
co n d u ct o r performance t h r o u g h o u t t h e i n d u s t r y a t t h e p r e s e n t , but
wit h t h e use o f a s u f f i c i e n t b u r n - i n p e r io d and computer c h e c k - o u t ,
43
most problems can be e l i m i n a t e d b e fo re p u t t i n g t h e MUX in s e r v i c e .
No long term r e l i a b i l i t y f i g u r e s have been d e t e r m i n e d , e i t h e r ,
because o f t h e s h o r t (2 y e a r ) o p e r a t i o n ti m e .
The long term r e ­
l i a b i l i t y o f t h e MUX, however, w i l l be determined by t h e l i f e of
the ! C s .
5 .5
CONCLUSION
The MUX has met e ver y r e qui re m e nt and s p e c i f i c a t i o n s e t f o r t h
in c h a p t e r s one and two.
I t i s a ve ry eas y dev ice t o program, very
r e l i a b l e and i f problems do occur i t i s e as y t o s e r v i c e and r e p a i r .
The p r o j e c t was h ig h ly s u c c e s s f u l and because i t was c a r r i e d
from o r i g i n a l de sig n to f i n a l t e s t i n g and m a n u fa c tu r in g , a g r e a t deal
about v a r i o u s a s p e c t s o f a c t u a l p ro duc t e n g in e e r in g was l e a r n e d .
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